CN109417033A - 半导体装置以及半导体集成电路 - Google Patents

半导体装置以及半导体集成电路 Download PDF

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CN109417033A
CN109417033A CN201680087172.4A CN201680087172A CN109417033A CN 109417033 A CN109417033 A CN 109417033A CN 201680087172 A CN201680087172 A CN 201680087172A CN 109417033 A CN109417033 A CN 109417033A
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吉谷正章
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Abstract

本发明提供一种半导体装置以及半导体集成电路，具有元件分离区域(14)、凸状的半导体区域(11)、形成于凸状的半导体区域的一部分的两个侧面以及上表面的栅电极，且是形成在元件分离区域的对置的一对端部之间的多个第一栅电极(12A)、在与多个第一栅电极相同的层形成在多个第一栅电极之间，并施加将晶体管设为截止状态的电压的至少一个第二栅电极(12B)以及源极区域和漏极区域，形成于第一栅电极和第二栅电极的两侧的凸状的半导体区域，在具有第一栅电极的晶体管之间，配置具有施加成为截止状态的电压的第二栅电极的晶体管，从而不降低晶体管的饱和电流而减少晶体管中的发热。

Description

半导体装置以及半导体集成电路
技术领域
本发明涉及半导体装置以及半导体集成电路。
背景技术
具有一种场效应晶体管(Fin Field Effect Transistor：FinFET)，对于形成在基板上的沿单向延伸的凸状(肋片形状)的半导体区域的一部分，具有在其两个侧面以及上表面形成栅极绝缘膜以及栅电极，在栅电极的两侧的凸状的半导体区域形成源极区域以及漏极区域的肋片形状的结构(例如，参照专利文献1)。FinFET在其结构上，由于容易留下热量，所以需要想办法通过布局来减少发热。
图8是表示具有将多个栅电极形成为梳齿状(指状)的多指结构的FinFET的构成例的图。在图8中，101是形成在基板上的沿单向延伸的凸状(肋片形状)的半导体区域。
对于凸状的半导体区域101的一部分，形成为经由栅极绝缘膜覆盖其两个侧面以及上表面的栅电极102与凸状的半导体区域101交叉，在栅电极102的两侧的凸状的半导体区域101形成源极区域以及漏极区域。多个栅电极102例如由多晶硅构成，经由导通孔与金属布线103连接。
另外，在图8中，104是用于分离形成晶体管的区域的元件分离绝缘膜(ShallowTrench Isolation：STI)，105是虚设栅电极，配置在栅电极102与STI104之间，形成在与栅电极102相同的层。虚设栅电极102例如也由多晶硅构成。
具有多指结构的FinFET受到相邻的晶体管的发热的影响，如图9所示，指状物的数量越多越容易发热。换句话说，若FinFET为图8所示的多指结构，则与指状物的数量为1的情况相比容易发热。
作为抑制FinFET的发热的一个方法，如图10所示，考虑将指状物的数量设为1等，降低来自相邻的晶体管的发热的影响并抑制发热的方法。图10是表示将指状物的数量设为1的FinFET的构成例的图，对于与图8所示的构成要素相同的构成要素标注相同的附图标记。
但是，如图10所示，在将指状物的数量设为1的FinFET中，配置于栅电极102的两侧的STI104间的距离x变短。若STI104间的距离x变短，则由于STI应力(基于STI104的应力)，图11所示晶体管的饱和电流Ion减少。因此，为了获得与具有例如图8所示的多指结构的FinFET相同的饱和电流Ion，需要增加晶体管数，而导致消耗电力、面积增加。
专利文献1:日本特开2015－220420号公报
发明内容
本发明的目的在于提供一种能够不降低晶体管的饱和电流而减少晶体管中的发热的FinFET型的半导体装置。
半导体装置的一个方式具有：元件分离区域；凸状的半导体区域；形成于凸状的半导体区域的一部分的两个侧面以及上表面的栅电极，且是形成于元件分离区域的对置的一对端部之间的多个第一栅电极；在与多个第一栅电极相同的层形成在多个第一栅电极之间，并施加将晶体管设为截止状态的电压的第二栅电极；以及源极区域和漏极区域，形成于第一栅电极以及第二栅电极的两侧的凸状的半导体区域。
公开的半导体装置通过在具有第一栅电极的晶体管之间，配置具有施加成为截止状态的电压的第二栅电极的晶体管，能够不使晶体管的饱和电流降低而减少晶体管中的发热。
附图说明
图1是表示本实施方式中的半导体装置的构成例的图。
图2A是沿着图1的I－I线的简要剖视图。
图2B是沿着图1的II－II线的简要剖视图。
图2C是沿着图1的III－III线的简要剖视图。
图3是表示本实施方式中的半导体装置的其它构成例的图。
图4是表示本实施方式中的半导体装置的其它构成例的图。
图5是表示本实施方式中的半导体装置的其它构成例的图。
图6A是表示作为本实施方式中的半导体装置的应用例的振荡电路的构成例的电路图。
图6B是表示图6A所示的P沟道晶体管的构成例的图。
图6C是表示图6A所示的N沟道晶体管的构成例的图。
图7A是表示作为本实施方式中的半导体装置的应用例的偏置电路的构成例的电路图。
图7B是表示图7A所示的晶体管的构成例的图。
图8是表示具有多指结构的FinFET的构成例的图。
图9是表示与FinFET中的指状物的数量相应的发热的变化的图。
图10是对抑制FinFET的发热的方法进行说明的图。
图11是表示与FinFET中的STI间的距离相应的饱和电流的变化的图。
具体实施方式
以下，基于附图对本发明的实施方式进行说明。
图1是表示作为本发明的一个实施方式中的半导体装置的具有肋片形状的结构的场效应晶体管(Fin Field Effect Transistor：FinFET)的构成例的图。图2A是沿着图1的I－I线的简要剖视图，图2B是沿着图1的II－II线的简要剖视图，图2C是沿着图1的III－III线的简要剖视图。
本实施方式中的FinFET在基板17上形成有沿单向延伸的凸状(肋片形状)的半导体区域11。对于凸状的半导体区域11的一部分，在其两个侧面以及上表面形成有未图示的栅极绝缘膜。在凸状的半导体区域11的一部分，在两个侧面以及上表面形成有经由栅极绝缘膜覆盖的栅电极12A、12B。在凸状的半导体区域11的栅极绝缘膜的覆盖部分，换言之栅电极12A、12B的两侧的凸状的半导体区域11形成有源极区域以及漏极区域。
栅电极12A、12B在元件分离区域的对置的一对端部之间形成于相同的层，例如由多晶硅构成。栅电极12A分别经由导通孔16A与供信号输入的金属布线13A连接。栅电极12B分别经由导通孔16B同施加与背栅相同的电压的金属布线13B连接。另外，形成于凸状的半导体区域11的源极区域以及漏极区域分别经由未图示的接触电极与源电极以及漏电极连接。
另外，在基板17上形成有用于分离形成晶体管的区域的元件分离绝缘膜(ShallowTrench Isolation：STI)14。在STI14与栅电极12A或者12B之间，在与栅电极12A、12B相同的层形成有例如由多晶硅构成的虚设栅电极15。此外，图1、图2A、图2B以及图2C所示的半导体装置能够使用公知的制造方法来形成，例如，能够使用上述专利文献1所记载的制造方法的至少一部分来形成。
像这样，本实施方式中的FinFET在配置有STI14的元件分离区域的对置的一对端部之间，具有多个施加信号的栅电极12A形成为梳齿状(手指状)的多指结构，并在施加信号的栅电极12A之间，设置有施加与背栅相同的电压的栅电极12B。即，在根据信号驱动的晶体管MA之间配置有晶体管MB，该晶体管MB将栅电极12B的电位限制为截止状态。
由此，能够抑制FinFET中的发热。另外，形成于栅电极的两侧的STI14间的距离也充分变长，而能够缓和STI应力维持饱和电流Ion。
此外，在上述的例子中，交替地设置有输入信号的栅电极12A和施加与背栅相同的电压的栅电极12B。即，在根据信号驱动的晶体管之间设置有一个晶体管，该晶体管将栅电极的电位限制为截止状态。但是，本发明并不限于此。
设置在供信号输入的栅电极12A间的施加与背栅相同的电压的栅电极12B的数量是任意的，例如，也可以如图3所示，在供信号输入的栅电极12A之间设置施加与背栅相同的电压的2个栅电极12B。即，也可以在根据信号驱动的晶体管之间设置2个将栅电极的电位限制为截止状态的晶体管。
另外，例如，也可以如图4所示，每2个供信号输入的栅电极12A相邻配置，并在其间设置施加与背栅相同的电压的1个栅电极12B。即，也可以使2个根据信号驱动的晶体管相邻，并在其间设置1个将栅电极的电位限制为截止状态的晶体管。
另外，例如，也可以如图5所示，每2个供信号输入的栅电极12A相邻配置，并在其间设置2个被施加与背栅相同的电压的栅电极12B。即，也可以使2个根据信号驱动的晶体管相邻，并在其间设置2个将栅电极的电位限制为截止状态的晶体管。此外，由于若增加相邻配置根据信号驱动的晶体管的数量则发热增加，所以优选相邻配置1个或者2个根据信号驱动的晶体管。
接下来，对应用本实施方式中的FinFET的半导体集成电路进行说明。图6A是表示作为本实施方式中的FinFET的应用例的电压控制振荡电路(VCO)的构成例的电路图。电压控制振荡电路具有P沟道晶体管M11、M13、N沟道晶体管M12、M14、电感器L11、电容C11以及电压控制的可变电容C12。
P沟道晶体管M11的源极与供给电源电压VDD的信号线连接，漏极与N沟道晶体管M12的漏极连接。N沟道晶体管M12的源极与供给基准电压(例如地线GND)的信号线连接。
同样地，P沟道晶体管M13的源极与供给电源电压VDD的信号线连接，漏极与N沟道晶体管M14的漏极连接。N沟道晶体管M14的源极与供给基准电压的信号线连接。
另外，P沟道晶体管M11的栅极以及N沟道晶体管M12的栅极与P沟道晶体管M13的漏极和N沟道晶体管M14的漏极的相互连接点连接。P沟道晶体管M13的栅极以及N沟道晶体管M14的栅极与P沟道晶体管M11的漏极和N沟道晶体管M12的漏极的相互连接点连接。即，由晶体管M11、M12构成的第一逆变器和由晶体管M13、M14构成的第二逆变器交叉耦合。
在晶体管M11、M12的漏极的相互连接点与晶体管M13、M14的漏极的相互连接点之间，并联连接电感器L11、电容C11以及可变电容C12。
图6A所示的振荡电路的振荡频率f由电感器L11、电容C11以及可变电容C12决定，通过f＝1/(2π√(L11(C11+C12)))来表示。为了实现高频的振荡频率减小电感器L11、电容C11，但若过度减小电感器L11则难以振荡，所以一般地减小电容C11。
作为电容C11的成分，布线的寄生负载、交叉耦合的晶体管负载是主要的。另外，由于振荡信号是正弦波，所以存在晶体管M11～M14成为导通状态的期间相对较长，且容易发热的趋势。在这里，例如若想要如图10所示抑制发热，则由布线引起的负载增加并且晶体管的饱和电流Ion降低，所以需要增加晶体管的数量。其结果，电容C11增加，而难以实现所希望的振荡频率。
作为晶体管M11～M14，通过应用本实施方式中的FinFET，能够不使晶体管的饱和电流Ion降低而抑制发热，并能够抑制由布线负载引起的电容C11的增加，而输出所希望的振荡频率的信号。
例如，通过将P沟道晶体管M11、M13作成图6B所示的结构，并将N沟道晶体管M12、M14设为图6C所示的结构，能够不使晶体管的饱和电流Ion降低而抑制发热。图6B以及图6C是表示图6A所示的P沟道晶体管M11、M13以及N沟道晶体管M12、M14的构成例的图，对于与图1所示的构成要素相同的构成要素标注相同的附图标记。
图6B所示的FinFET将以栅电极12A为栅电极的晶体管的源极区域形成在栅电极12A与栅电极12B(或者虚设栅电极15)之间的半导体区域11，漏极区域形成在相邻的栅电极12A之间的半导体区域11。以栅电极12A为栅电极的晶体管的源极区域经由未图示的接触电极与供给电源电压VDD的源电极连接，漏极区域经由未图示的接触电极与漏电极连接。
另外，图6C所示的FinFET将以栅电极12A为栅电极的晶体管的源极区域形成于栅电极12A与栅电极12B(或者虚设栅电极15)之间的半导体区域11，漏极区域形成于相邻的栅电极12A之间的半导体区域11。以栅电极12A为栅电极的晶体管的源极区域经由未图示的接触电极与供给基准电压(例如地线GND)的源电极连接，漏极区域经由未图示的接触电极与漏电极连接。
图7A是表示作为本实施方式中的FinFET的应用例的偏置电路的构成例的电路图。图7A所示的偏置电路是P沟道晶体管M21、M22电流镜连接，作为电流I2流动电流I1的2倍的电流的电路。
例如，通过将P沟道晶体管M21、M22设为如图7B所示的结构，能够不使晶体管的饱和电流Ion降低而抑制发热。图7B是表示图7A所示的P沟道晶体管M21、M22的构成例的图，对于与图1所示的构成要素相同的构成要素标注相同的附图标记。通过使用具有1组2个相邻的栅电极12A的晶体管作为P沟道晶体管M21，并使用具有2组2个相邻的栅电极12A的晶体管作为P沟道晶体管M22，从而能够流经在晶体管M21中流动的电流I1的2倍的电流作为电流I2。
另外，上述实施方式均只是表示在实施本发明时的具体化的一个例子，不能通过它们限定性地解释本发明的技术范围。即，本发明能够不脱离其技术思想、或者其主要的特征地以各种形式来实施。
根据本发明，通过在FinFET中，在具有施加信号的栅电极的晶体管之间，配置具有施加成为截止状态的电压的栅电极的晶体管，能够不降低晶体管的饱和电流而减少晶体管中的发热。

Claims (12)

1.一种半导体装置，其特征在于，具有：
元件分离区域；
凸状的半导体区域；
形成于上述凸状的半导体区域的第一部分的两个侧面以及上表面的栅电极，且是形成于上述元件分离区域的对置的一对端部之间的多个第一栅电极；
形成于与上述第一部分不同的上述凸状的半导体区域的第二部分的两个侧面以及上表面的栅电极，且是在与上述多个第一栅电极相同的层形成于上述多个第一栅电极之间，并施加将晶体管设为截止状态的电压的至少一个第二栅电极；以及
源极区域和漏极区域，形成于上述第一栅电极以及上述第二栅电极的两侧的上述凸状的半导体区域。
2.根据权利要求1所述的半导体装置，其特征在于，
向上述第二栅电极施加与上述晶体管的背栅相同的电压。
3.根据权利要求1或2所述的半导体装置，其特征在于，
在上述多个第一栅电极的各个电极之间形成有上述第二栅电极。
4.根据权利要求1或2所述的半导体装置，其特征在于，
将2个上述第一栅电极设为1组，在上述第一栅电极的组的各个组之间，形成有上述第二栅电极。
5.根据权利要求1～4中任一项所述的半导体装置，其特征在于，
上述晶体管是FinFET。
6.一种半导体集成电路，其特征在于，是形成于具有以下部件的基板的电路，且具有使用至少包含上述第一栅电极、上述源极区域以及漏极区域的晶体管的电路：
元件分离区域；
凸状的半导体区域；
形成于上述凸状的半导体区域的第一部分的两个侧面以及上表面的栅电极，且是形成于上述元件分离区域的对置的一对端部之间的多个第一栅电极；
形成于与上述第一部分不同的上述凸状的半导体区域的第二部分的两个侧面以及上表面的栅电极，且是在与上述多个第一栅电极相同的层，形成于上述多个第一栅电极之间，并施加将晶体管设为截止状态的电压的至少一个第二栅电极；以及
源极区域和漏极区域，形成于上述第一栅电极以及上述第二栅电极的两侧的上述凸状的半导体区域。
7.根据权利要求6所述的半导体集成电路，其特征在于，
使用上述晶体管的电路是振荡电路，该振荡电路具有：
逆变器，使用上述晶体管构成且交叉耦合；
电感器，连接在上述逆变器的输出节点间；以及
电容，在上述逆变器的输出节点间与上述电感器并联连接。
8.根据权利要求6所述的半导体集成电路，其特征在于，
使用上述晶体管的电路是偏置电路，该偏置电路具有：
第一上述晶体管；以及
第二上述晶体管，与上述第一晶体管电流镜连接。
9.根据权利要求6～8中任一项所述的半导体集成电路，其特征在于，
向上述晶体管的上述第二栅电极施加与该晶体管的背栅相同的电压。
10.根据权利要求6～9中任一项所述的半导体集成电路，其特征在于，
在上述多个第一栅电极的各个电极之间形成有上述第二栅电极。
11.根据权利要求6～9中任一项所述的半导体集成电路，其特征在于，
将2个上述第一栅电极设为1组，在上述第一栅电极的组的各个组之间，形成有上述第二栅电极。
12.根据权利要求6～11中任一项所述的半导体集成电路，其特征在于，
上述晶体管是FinFET。
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Publication number Priority date Publication date Assignee Title
CN113345955A (zh) * 2020-03-03 2021-09-03 铠侠股份有限公司 半导体装置
CN113345955B (zh) * 2020-03-03 2024-02-23 铠侠股份有限公司 半导体装置
US11923299B2 (en) 2020-03-03 2024-03-05 Kioxia Corporation Semiconductor device

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CN109417033B (zh) 2022-03-18
JP6823270B2 (ja) 2021-02-03
US20190131303A1 (en) 2019-05-02
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