TWI552305B - 積體電晶體及反熔絲作為編程元件用於高壓積體電路 - Google Patents

積體電晶體及反熔絲作為編程元件用於高壓積體電路 Download PDF

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TWI552305B
TWI552305B TW100115873A TW100115873A TWI552305B TW I552305 B TWI552305 B TW I552305B TW 100115873 A TW100115873 A TW 100115873A TW 100115873 A TW100115873 A TW 100115873A TW I552305 B TWI552305 B TW I552305B
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蘇吉特 班納吉
馬丁 曼利
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電源整合公司
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Description

積體電晶體及反熔絲作為編程元件用於高壓積體電路
本發明大體上和製作具有可編程電連接之高壓積體電路的半導體製程有關。
常見類型的積體電路(Integrated Circuit，IC)裝置為金屬氧化物半導體場效電晶體(Metal-Oxide-Semiconductor Field Effect Transistor，MOSFET)。MOSFET係一種場效裝置，其包含一源極區、一汲極區、一延伸在該等源極區和汲極區之間的通道區、以及一位於該通道區上方的閘極。該閘極包含一被設置在該通道區上方的導體閘極結構。該導體閘極通常係藉由一薄氧化物層和該通道區絕緣。
高壓場效電晶體(High-Voltage Field-Effect Transistor，HVFET)同樣係半導體技術中所熟知。許多HVFET所運用的裝置結構包含一延伸汲極區(亦稱為漂移區)，其係在該裝置處於「關閉(off)」狀態中時支援或「阻隔」外加高電壓(舉例來說，150伏或更大)。高壓積體電路(High-Voltage Integrated Circuit，HVIC)製程中的HVFET通常係被形成橫向裝置結構，其中，源極和汲極係在該半導體晶粒的頂端表面。通道區和漂移區會分隔源極和汲極。通道區上方的閘極係用來切換該HVFET使其導通或關閉，而且該漂移區會支援汲極電壓。介於通道和汲極之間的漂移區的長度會決定該裝置能夠支援的最大電壓。藉由修正該漂移長度便能夠在相同的HVIC製程中整合具有不同電壓能力的裝置。在本申請案內文中，中壓裝置所指的係電壓在50V至150V的範圍中。中壓FET能夠被整合在讓HVFET能夠支援高於150V電壓的相同HVIC製程之中。
一高壓或功率IC裝置的操作特徵通常係藉由選擇性張開(或閉合)一或多條電連接而被設定或編程。齊納二極體係一種用於修整或編程一功率IC。
裝置的類比參數(舉例來說，頻率)的電元件。齊納二極體會提供一正常為關閉或不導通的電連接。為改變齊納元件的導通狀態，通常會施加一高電壓(>10V)來崩潰該齊納元件，大額最終電流(150至200mA)會永久性短路該齊納元件的陽極終端和陰極終端。流經該等齊納元件的累積電流可以用來編程一或多個類比參數。舉例來說，一類比參數(例如，頻率)可以一或多個齊納元件的狀態為基礎在該功率IC的控制器區段中被設定在指定的公差內。
一種半導體裝置包含一位於P型基板之中的N型井區。一MOSFET的源極區係和包含該MOSFET之汲極的井區的邊界橫向分隔。該MOSFET的絕緣閘極係從該源極區橫向延伸至至少剛好越過該井區的邊界處。一構成一電容式反熔絲之第一平板的多晶矽層係和該井區中構成該反熔絲之第二平板的區域絕緣。該反熔絲係藉由跨越該等第一與第二電容板施加一足以破壞該第二介電層之至少一部分的電壓而被編程，從而電短路該多晶矽層至該HVFET的汲極。
一種高壓裝置，其包含：一第一導電類型的基板；一第二導電類型的井區，其係被設置在該基板之中；一第二導電類型的第一區，其係藉由一通道區自該井區的邊界而橫向分隔，該第一區包含一高壓場效電晶體(HVFET)的源極；一第一導電層，其係藉由一具有第一厚度的第一介電層而與該通道區絕緣，該第一介電層係在該通道區的上方從該源極橫向延伸至該井區的一第一區域上方至少剛好越過該邊界處，該第一導電層包含該HVFET的閘極而該第一井區包含該HVFET的漂移區；一第二導電層，其係藉由一具有第二厚度的第二介電層而與該井區的一第二區域絕緣，該第一介電層和該第二介電層係在該基板的一表面藉由一具有第三厚度的第三介電層而橫向分隔，該第三厚度實質上大於該等第一或第二厚度，該第二導電層包含一反熔絲的一第一電容板，該井區的該第二區域包含該反熔絲的一第二電容板，該井區的一第三區域係被設置在該第三介電層的下方，該第三區域係分隔該井區的該等第一及第二區域；其中，該反熔絲係藉由施加一足以導通該HVFET的第一電壓於該閘極及施加一足以破壞該第二介電層之至少一部分的第二電壓於該第一電容板而被編程，從而將該HVFET的源極電連接至該第一電容板。
一種功率半導體裝置，其包含：一第一導電類型的基板；一第二導電類型的第一井區，其係被設置在該基板之中；一第一導電類型的第二井區，其係被設置在該第一井區鄰近的該基板之中；一第二導電類型的第一區，其係被設置在該第二井區之中，該第一區係藉由一通道區自該第一井區鄰接該第二井區的邊界而橫向分隔，該第一區包含一MOSFET的源極；該MOSFET的閘極係被設置在該通道區上方並且和該通道區絕緣；一導電層，其係被設置在該第一井區的一第二區域上方並且藉由一第一介電層而與該第一井區的該第二區域絕緣，該導電層包含一第一電容板，該第一井區的該第二區域包含一第二電容板；一第二導電類型的第二區，其係被設置在該第一井區之中，該第二區係鄰接該第二區域並且係在該基板的一表面處部分被該第一介電層覆蓋，該第二區包含一MOSFET的汲極；一第二介電層，其係在該基板的該表面處橫向鄰接該第一介電層並且部分覆蓋該第二區，該第二介電層實質上厚於該第一介電層；以及其中，該功率半導體裝置係藉由施加一足以導通該MOSFET的第一電壓於該閘極及施加一足以破壞該第一介電層之至少一部分的第二電壓於該第一電容板而被編程，從而短路該MOSFET的汲極至該第一電容板。
本文揭示一種新穎的積體反熔絲裝置結構。在下面的說明中，會提出特定的細節，例如，材料類型、電壓、結構特點、製造步驟...等，以便透澈瞭解本發明。然而，熟習相關技術的人士便會明白，沒有此等特定細節仍可實行本文所述的實施例。整份說明中引用的「其中一實施例」、「一實施例」、「其中一範例」、或是「一範例」的意義為配合該實施例或範例所述的一特殊特點、結構、或特徵會包含在至少其中一實施例之中。整份說明中各處的「在其中一實施例中」、「在一實施例中」、「其中一範例」、或是「一範例」未必全部表示相同實施例或範例。再者，該等特殊特點、結構、或特徵可以任何合宜的組合及/或子組合方式組合在一或多個實施例或範例中。
應該瞭解的係，圖中的元件僅為代表性，而且為清楚起見，並未依比例繪製造。還要明白的係，本文中雖然揭示的係運用主要為N通道電晶體裝置的IC(高壓與低壓)；不過，在所有適當的摻雜區中運用相反的導電類型亦可製作P通道電晶體。
在本申請案內文中，高壓或功率電晶體係能夠在「關閉」狀態或條件中支援150伏或更大的任何半導體電晶體結構。中壓電晶體係能夠支援50V至150V的半導體電晶體結構。本文中所使用的功率電晶體係能夠支援50V至150V或更高的任何半導體電晶體結構。功率電晶體或功率半導體裝置可為中壓和高壓電晶體兩者。功率IC或功率IC裝置代表一包含中壓及/或高壓電晶體裝置的半導體裝置。於其中一實施例中，高壓電晶體或中壓電晶體係被圖解為金屬氧化物半導體場效電晶體(MOSFET)，其電壓係由源極區和汲極區之間的漂移區來支援。
為達本發明的目的，「接地」或「接地電位」所指的係一參考電壓或電位，一電路或IC的所有其它電壓或電位皆以其為基準來界定或測量。「接針」提供一連接至一IC裝置或封裝的外部電連接點，從而讓外部組件、電路、訊號、電力、負載、...等被耦接至該功率IC裝置的內部組件和電路系統。
本文中使用的反熔絲係一種電路元件，其如同電容器係在一裝置結構中提供正常為張開的電連接，其具有藉由一介電層(舉例來說，氧化物、氮化物、...等)來分隔的二或多層金屬、多晶矽、或有摻雜的半導體材料。該等兩層金屬之間的電連接會因跨越該等金屬導體施加一大電壓而永久閉合，該大電壓係用來崩潰或破壞該介電層，從而電短路該等兩個金屬層。
圖1為一反熔絲編程元件50的其中一實施例的範例剖面圖，其包含一積體中壓或高壓場效電晶體(HVFET)和反熔絲裝置結構。圖2為圖1中所示的積體裝置結構的等效電路圖。從圖中可以看見，圖2中所示的反熔絲電容器32包含一多晶矽層48，其係藉由一薄介電(舉例來說，閘極氧化物)層49和下方的N型井區47分隔(參見圖1)。多晶矽層48和N型井區47會構成該電容式反熔絲結構的兩塊平板。N型井區47還會構成MOSFET 33的延伸汲極或漂移區。
源極電極58會提供和N+源極區57及P+區56的電連接，此兩區係被設置在一鄰接N井區47的P型井區55之中。圖中所示的源極電極58係被電連接至N+源極區57及P+區56兩者。於其它實施例中，P+區56可能和N+源極區57隔開，俾使得源極電極58僅連接N+源極區57。P井區55中的一區域會構成MOSFET 33的通道區61，其係橫向分隔N+源極區57和P井區55與N井區47之間的邊界或邊緣。MOSFET 33的閘極包含一多晶矽層52，其係藉由一薄介電(舉例來說，閘極氧化物)層51和下方的P型基板25及N+井區絕緣。閘極電極59會電連接多晶矽層52。
一編程或修整HV脈衝可在電連接多晶矽層48的節點60處被施加至反熔絲編程元件50。在施加編程HV脈衝至節點60之前，閘極電極59會提升至一高電位(以便導通MOSFET 33)且源極電極58係被連接至接地(舉例來說，經由一低阻抗開關)。於其中一實施例中，該編程電壓脈衝係在30至50V的範圍中。該編程電壓會相依於介電層49的厚度。當該編程電壓脈衝被施加時，分隔該等兩個終端或電容板的介電層49會破裂，導致多晶矽層48和N井區47之間永久短路，從而編程該反熔絲結構。
在編程之前，反熔絲編程元件50不係在一正電壓被施加至閘極電極59用以導通MOSFET 33時在電極60與58之間流通任何電流；也就是，對正常的DC操作電壓(舉例來說，VDD=5至6V)來說，其似乎是一開路電路。一旦反熔絲編程元件50被編程且一正電壓被施加至閘極電極59(用以導通MOSFET 33)，反熔絲編程元件50的表現就如同一阻值通常為數千歐姆的電阻。
本技術中的從事者便會明白，用於修整或編程反熔絲編程元件50所需要的電流量明顯小於通常需要>150mA的既有齊納二極體。編程元件50的典型電流係在0.1mA至2mA的範圍中。除此之外，熟習本技術的人士便會瞭解，相較於先前技術的設計，本文所揭示的積體反熔絲裝置結構可以將功率IC裝置的修整方塊的整體大小縮減約五倍或更多。
於其中一施行方式中，MOSFET 33係被設計成具有約50V的崩潰電壓，而該電容式反熔絲結構的介電層(舉例來說，閘極氧化物)49則係被製造成具有約25V的崩潰電壓。
圖3為另一積體反熔絲編程元件70的範例剖面圖。除了反熔絲編程元件70還包含被設置在較厚的介電(舉例來說，場氧化物)層41下方的N井47的左邊區域中的第一複數個實質平行、垂直隔開的P型埋置區53之外，圖3範例中所示的裝置結構皆和圖1相同。圖中所示的對應複數個JFET傳導通道55係由埋置區53的垂直間隔所形成。圖中所示的第二複數個實質平行、垂直隔開的P型埋置區54係被設置在厚的場氧化物層42下方的N井47的右邊區域之中。圖中所示的最上方埋置區和分別位於N井47的左側及右側的場氧化物區41&42一致。於其它實施例中，該等最上方埋置區可能係被設置在場氧化物區41&42下方的某一距離處，俾便係在該最上方埋置區及對應的場氧化物區之間形成一JFET傳導通道。
從圖中可以看見，P型埋置區53和54並未橫向延伸在薄氧化物層51或49的下方。於其中一實施例中，可以使用一深植入(未顯示)或任何其它類型等效結構來電連接每一個埋置區53&54。這係在反熔絲編程元件50希望保持不被修整或開路時讓P型埋置區53和54(其包含該JFET的閘極)被電連接至(連同源極電極58)接地或接近接地的電位。要明白的係，P型埋置區53和54的併入係本文所述的積體反熔絲編程元件中的非必要特點。此外，圖3的範例中雖然顯示三個埋置區53(和三個埋置區54)；但是，熟習本技術的人士便會瞭解，垂直隔開的P型埋置區53和54的數量在不同的實施例中可以不同，其範圍從一個(單一埋置區)到六個或更多。
圖4為另一反熔絲裝置結構的範例電路佈局的俯視圖。圖5為沿著切割線A-A’所取得之圖4中所示的反熔絲裝置結構的範例剖面圖。如圖所示，反熔絲編程元件80包含和圖1之裝置結構中所示相同的基本元件，並且進一步包含一被設置在N井47之中的重摻雜N+區43，其部分位於薄介電(氧化物)層49的下方且部分位於厚的場氧化物層41的漸細邊緣的下方。圖中所示的多晶矽層48雖然被設置在介電層49上方；但是，僅延伸在N+區43其中一側的略為上方處。半導體技術中的從事者便明白，N+區43可被形成自動對齊多晶矽層48。
要進一步明白的係，圖1至5中所示的任何實施例亦可以被設置在該N井區相反橫向側的兩個MOSFET閘極結構來製造，取代範例所示的單一閘極結構。舉例來說，圖5中所示的實施例可以位於N井47相反側的兩個MOSFET閘極結構(兩者和N+區43等距)來製作。
還應該瞭解的係，圖5中所示的裝置結構的另一變化例可能包含一或多個垂直隔開的P型埋置區，它們會和N+區43分隔並且以和圖3的範例中所示雷同的方式被設置在場氧化物層41的下方(且視情況亦位於場氧化物層42的下方)。
雖然本文已經配合特定實施例說明過本發明；但是，熟習本技術的人士便會明白，許多修正與變更亦落在本發明的範疇中。據此，說明書和圖式均應被視為解釋性，而沒有限制意義。
25．．．P型基板
32．．．反熔絲電容器
33．．．MOSFET
41．．．場氧化物層
42．．．場氧化物層
43．．．N+區
47．．．N型井區
48．．．多晶矽層
49．．．介電層
50．．．反熔絲編程元件
51．．．介電層
52．．．多晶矽層
53．．．P型埋置區
54．．．P型埋置區
55．．．P井區
56．．．P+區
57．．．N+源極區
58．．．源極電極
59．．．閘極電極
60．．．節點
61．．．通道區
70．．．反熔絲編程元件
80．．．反熔絲編程元件
從前面的詳細說明和附圖中會更完整瞭解本發明；然而，其不應被視為將本發明限制於所示的特定實施例，而僅係為達解釋和瞭解的目的。
圖1為一編程元件的範例剖面圖，該編程元件包含一積體電晶體和反熔絲裝置結構。
圖2為圖1中所示的積體裝置結構的等效電路圖。
圖3為另一反熔絲裝置結構的範例剖面圖。
圖4為另一反熔絲裝置結構的範例電路佈局的俯視圖。
圖5為沿著切割線A-A’所取得之圖4中所示的反熔絲裝置結構的範例剖面圖。
25．．．P型基板
41．．．場氧化物層
42．．．場氧化物層
47．．．N型井區
48．．．多晶矽層
49．．．介電層
50．．．反熔絲編程元件
51．．．介電層
52．．．多晶矽層
55．．．P井區
56．．．P+區
57．．．N+源極區
58．．．源極電極
59．．．閘極電極
60．．．節點

Claims (27)

  1. 一種半導體裝置，其包含：一第一導電類型的一基板；一第二導電類型的一第一井區，其係被設置在該基板之中；該第一導電類型的一第二井區，其係被設置在該第一井區鄰近的該基板之中；該第二導電類型的一第一區，其係被設置在該第二井區之中，該第一區係藉由一通道區自該第一井區鄰接該第二井區的邊界而橫向分隔，該第一區包含一MOSFET的一源極；一第一導電層，其係藉由一第一介電層而與該基板的一第一區域絕緣，該第一介電層係在該通道區的上方從該第一區橫向延伸至至少剛好越過該第一井區的一第一區域上方之邊界處，該第一導電層包含該MOSFET的一閘極而該第一井區包含該MOSFET的一漂移區；一第二導電層，其係藉由一第二介電層而與該第一井區的一第二區域絕緣，該第一介電層和該第二介電層係在該基板的一表面藉由一厚介電層橫向分隔，該第二導電層包含一第一電容板，該第一井區的該第二區域包含一第二電容板，該第一井區的一第三區域係被設置在該厚介電層的下方，該第三區域分隔該第一井區的該等第一及第二區域； 其中，高壓的該半導體裝置係編程為藉由施加一足以導通該MOSFET的第一電壓於該閘極及施加一足以破壞該第二介電層之至少一部分的第二電壓於該第一電容板，從而將該MOSFET的該源極電連接至該第一電容板。
  2. 如申請專利範圍第1項之半導體裝置，其進一步包含該第一導電類型的一或多個第一埋置區，其係被設置在該第一井區的該第三區域中，該等一或多個第一埋置區係被垂直隔開，以便在該第一井區的該第三區域之中界定接面場效電晶體(JFET)傳導通道。
  3. 如申請專利範圍第2項之半導體裝置，其進一步包含該第一導電類型的一或多個第二埋置區，其係被設置在和該第二區域相鄰的該第一井區之一第四區域中，該等一或多個第二埋置區係被彼此垂直隔開。
  4. 如申請專利範圍第2項之半導體裝置，其中，該等第一埋置區中的最上方者係鄰接該厚介電層。
  5. 如申請專利範圍第2項之半導體裝置，其中，該等傳導通道係被界定在每一個該等第一埋置區之間，並且還被界定在該等第一埋置區中的最下方者和該基板之間。
  6. 如申請專利範圍第1項之半導體裝置，其進一步包含該第一導電類型的一第二區，該第二區係被設置 在和該第一區相鄰的該第二井區之中。
  7. 如申請專利範圍第1項之半導體裝置，其中，該第一導電類型為P型且該第二導電類型為N型。
  8. 如申請專利範圍第6項之半導體裝置，其進一步包含：一源極電極，其係電連接該等第一區和第二區；一閘極電極，其係電連接該第一導電層；以及一反熔絲電極，其係電連接該第二導電層。
  9. 如申請專利範圍第1項之半導體裝置，其進一步包含該第二導電類型的一第二區，其係被設置在該等第一區域和第二區域之間的該第一井區之中，該第二區包含該MOSFET的汲極區。
  10. 如申請專利範圍第1項之半導體裝置，其中，該等第一與第二介電層包含氧化物。
  11. 如申請專利範圍第2項之半導體裝置，其中，該等一或多個第一埋置區係被耦接至該第一區。
  12. 一種高壓裝置，其包含：一第一導電類型的一基板；一第二導電類型的一井區，其係被設置在該基板之中；具有第二導電類型的一第一區，其係藉由一通道區自該井區的邊界而橫向分隔，該第一區包含一高壓場效電晶體(HVFET)的一源極；一第一導電層，其係藉由具有一第一厚度的一 第一介電層而與該通道區絕緣，該第一介電層係在該通道區的上方從該源極橫向延伸至至少剛好越過該井區的一第一區域上方之該邊界處，該第一導電層包含該HVFET的一閘極而該第一井區包含該HVFET的一漂移區；一第二導電層，其係藉由具有一第二厚度的一第二介電層而與該井區的一第二區域絕緣，該第一介電層和該第二介電層係在該基板的一表面藉由具有一第三厚度的一第三介電層而橫向分隔，該第三厚度實質上大於該等第一或第二厚度，該第二導電層包含一反熔絲的一第一電容板，該井區的該第二區域包含該反熔絲的一第二電容板，該井區的一第三區域係被設置在該第三介電層的下方，該第三區域係分隔該井區的該等第一及第二區域；其中，該反熔絲係編程為藉由施加一足以導通該HVFET的第一電壓於該閘極及施加一足以破壞該第二介電層之至少一部分的第二電壓於該第一電容板，從而將該HVFET的該源極電連接至該第一電容板。
  13. 如申請專利範圍第12項之高壓裝置，其進一步包含該第一導電類型的一或多個第一埋置區，其係被設置在該井區的該第三區域中，該等一或多個第一埋置區係被垂直隔開，以便在該井區的該第三區域之中界定接面場效電晶體(JFET)傳導通道。
  14. 如申請專利範圍第13項之高壓裝置，其進一步包含該第一導電類型的一或多個第二埋置區，其係被設置在和該第二區域相鄰的該井區之一第四區域中，該等一或多個第二埋置區係被彼此垂直隔開。
  15. 如申請專利範圍第12項之高壓裝置，其進一步包含該第一導電類型的一第二井區，其係被設置在和該第二導電類型的該井區橫向相鄰的該基板之中，該源極和該通道區係被設置在該第二井區之中。
  16. 如申請專利範圍第13項之高壓裝置，其中，該等JFET傳導通道係被界定在每一個該等第一埋置區之間，並且還被界定在該等第一埋置區中的最下方者和該基板之間。
  17. 如申請專利範圍第15項之高壓裝置，其進一步包含該第一導電類型的一第二區，該第二區係被設置在和該第一區相鄰的該第二井區之中。
  18. 如申請專利範圍第12項之高壓裝置，其中，該第一導電類型為P型且該第二導電類型為N型。
  19. 如申請專利範圍第17項之高壓裝置，其進一步包含：一源極電極，其係電連接該等第一區和第二區；一閘極電極，其係電連接該第一導電層；以及一反熔絲電極，其係電連接該第二導電層。
  20. 如申請專利範圍第12項之高壓裝置，其中，該等 第一和第二導電層包含多晶矽。
  21. 如申請專利範圍第12項之高壓裝置，其中，該等第一和第二介電層包含氧化物。
  22. 如申請專利範圍第12項之高壓裝置，其中，該第三介電層包含一場氧化物。
  23. 如申請專利範圍第12項之高壓裝置，其中，該等第一和第二介電層之厚度實質上相等。
  24. 一種功率半導體裝置，其包含：一第一導電類型的一基板；一第二導電類型的一第一井區，其係被設置在該基板之中；該第一導電類型的一第二井區，其係被設置在該第一井區鄰近的該基板之中；該第二導電類型的一第一區，其係被設置在該第二井區之中，該第一區係藉由一通道區自該第一井區鄰接該第二井區的邊界而橫向分隔，該第一區包含一MOSFET的一源極；該MOSFET的一閘極係被設置在該通道區上方並且和該通道區絕緣；一導電層，其係被設置在該第一井區的一第二區域上方並且藉由一第一介電層而與該第一井區的該第二區域絕緣，該導電層包含一第一電容板，該第一井區的該第二區域包含一第二電容板；該第二導電類型的一第二區，其係被設置在該 第一井區之中，該第二區係鄰接該第二區域並且係在該基板的一表面處部分被該第一介電層覆蓋，該第二區包含一MOSFET的一汲極；一第二介電層，其係在該基板的該表面處橫向鄰接該第一介電層並且部分覆蓋該第二區，該第二介電層實質上厚於該第一介電層；以及其中，該功率半導體裝置係編程為藉由施加一足以導通該MOSFET的第一電壓於該閘極及施加一足以破壞該第一介電層之至少一部分的第二電壓於該第一電容板，從而短路該MOSFET的該汲極至該第一電容板。
  25. 如申請專利範圍第24項之功率半導體裝置，其進一步包含該第一導電類型的一第三區，該第三區係被設置在和該第一區相鄰的該第二井區之中。
  26. 如申請專利範圍第24項之功率半導體裝置，其中，該第一導電類型為P型且該第二導電類型為N型。
  27. 如申請專利範圍第24項之功率半導體裝置，其進一步包含：一源極電極，其係電連接該第一區；一閘極電極，其係電連接該閘極；以及一反熔絲電極，其係電連接該導電層。
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Families Citing this family (24)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8129815B2 (en) 2009-08-20 2012-03-06 Power Integrations, Inc High-voltage transistor device with integrated resistor
US9330979B2 (en) 2008-10-29 2016-05-03 Tower Semiconductor Ltd. LDMOS transistor having elevated field oxide bumps and method of making same
US9484454B2 (en) * 2008-10-29 2016-11-01 Tower Semiconductor Ltd. Double-resurf LDMOS with drift and PSURF implants self-aligned to a stacked gate “bump” structure
EP2453475A4 (en) * 2009-07-09 2016-05-11 Murata Manufacturing Co ANTI MELTING ELEMENT
US8305826B2 (en) 2010-05-07 2012-11-06 Power Integrations, Inc. Method and apparatus for programming an anti-fuse element in a high-voltage integrated circuit
US8164125B2 (en) * 2010-05-07 2012-04-24 Power Integrations, Inc. Integrated transistor and anti-fuse as programming element for a high-voltage integrated circuit
US7932738B1 (en) 2010-05-07 2011-04-26 Power Integrations, Inc. Method and apparatus for reading a programmable anti-fuse element in a high-voltage integrated circuit
KR20130072524A (ko) * 2011-12-22 2013-07-02 에스케이하이닉스 주식회사 반도체 장치 및 그 제조 방법
JP5978031B2 (ja) * 2012-07-03 2016-08-24 株式会社日立製作所 半導体装置
CN103531589B (zh) * 2012-07-05 2016-06-22 中芯国际集成电路制造(上海)有限公司 半导体器件及其制造方法
US9087713B2 (en) 2012-10-12 2015-07-21 Power Integrations, Inc. Semiconductor device with shared region
US9269808B2 (en) 2014-02-21 2016-02-23 Vanguard International Semiconductor Corporation Method and apparatus for power device with depletion structure
CN105849861B (zh) * 2014-04-03 2018-08-10 新诺普系统公司 反熔丝存储器单元
CN105097771B (zh) * 2014-05-12 2017-12-19 中芯国际集成电路制造(上海)有限公司 反熔丝元件、反熔丝元件的制造方法及半导体器件
US10032783B2 (en) * 2015-10-30 2018-07-24 Globalfoundries Singapore Pte. Ltd. Integrated circuits having an anti-fuse device and methods of forming the same
US10490548B2 (en) 2016-04-08 2019-11-26 Power Integrations, Inc. Integrated resistor for semiconductor device
WO2017201709A1 (zh) * 2016-05-26 2017-11-30 中山港科半导体科技有限公司 一种坚固的功率半导体场效应晶体管结构
US9806084B1 (en) * 2016-06-06 2017-10-31 International Business Machines Corporation Anti-fuse with reduced programming voltage
US10229919B2 (en) 2016-08-25 2019-03-12 International Business Machines Corporation Vertical field effect transistor including integrated antifuse
US10135357B1 (en) 2017-09-07 2018-11-20 Power Integrations, Inc. Threshold detection with tap
US11276697B2 (en) * 2018-04-02 2022-03-15 Intel Corporation Floating body metal-oxide-semiconductor field-effect-transistors (MOSFET) as antifuse elements
KR102051752B1 (ko) * 2018-06-14 2020-01-09 매그나칩 반도체 유한회사 반도체 소자 및 그 제조방법
TWI677982B (zh) * 2018-11-06 2019-11-21 旺宏電子股份有限公司 半導體元件及其製造方法
US11063034B2 (en) 2019-06-27 2021-07-13 Micron Technology, Inc. Capacitor structures

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6168983B1 (en) * 1996-11-05 2001-01-02 Power Integrations, Inc. Method of making a high-voltage transistor with multiple lateral conduction layers
US20020132405A1 (en) * 2000-11-27 2002-09-19 Power Integrations, Inc. Method of fabricating a high-voltage transistor
US20030178646A1 (en) * 2001-01-24 2003-09-25 Power Integrations, Inc. High-voltage transistor with buried conduction layer
JP2004179351A (ja) * 2002-11-27 2004-06-24 Matsushita Electric Ind Co Ltd 接合電界効果トランジスタおよび接合電界効果トランジスタの製造方法
US20060284276A1 (en) * 2005-06-21 2006-12-21 Hamza Yilmaz High voltage semiconductor devices with JFET regions containing dielectrically isolated junctions
US20090315109A1 (en) * 2008-06-20 2009-12-24 Kim Min-Seok Semiconductor device having otp cells and method for fabricating the same

Family Cites Families (24)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5282107A (en) 1992-09-01 1994-01-25 Power Integrations, Inc. Power MOSFET safe operating area current limiting device
US5285369A (en) 1992-09-01 1994-02-08 Power Integrations, Inc. Switched mode power supply integrated circuit with start-up self-biasing
US5977763A (en) 1996-02-27 1999-11-02 Micron Technology, Inc. Circuit and method for measuring and forcing an internal voltage of an integrated circuit
KR100504433B1 (ko) 1999-01-09 2005-07-29 주식회사 하이닉스반도체 앤티퓨즈를 이용한 메모리소자의 리페어 회로
US6266291B1 (en) 1999-02-23 2001-07-24 Micron Technology, Inc. Voltage independent fuse circuit and method
US6388853B1 (en) 1999-09-28 2002-05-14 Power Integrations, Inc. Method and apparatus providing final test and trimming for a power supply controller
US6630724B1 (en) 2000-08-31 2003-10-07 Micron Technology, Inc. Gate dielectric antifuse circuits and methods for operating same
US6640435B2 (en) 2001-02-20 2003-11-04 Power Integrations, Inc. Methods for trimming electrical parameters in an electrical circuit
US6635544B2 (en) * 2001-09-07 2003-10-21 Power Intergrations, Inc. Method of fabricating a high-voltage transistor with a multi-layered extended drain structure
US7221011B2 (en) * 2001-09-07 2007-05-22 Power Integrations, Inc. High-voltage vertical transistor with a multi-gradient drain doping profile
US6555873B2 (en) * 2001-09-07 2003-04-29 Power Integrations, Inc. High-voltage lateral transistor with a multi-layered extended drain structure
FR2838233A1 (fr) 2002-04-04 2003-10-10 St Microelectronics Sa Procede de programmation de cellules memoire par claquage d'elements antifusible
US6693481B1 (en) 2002-08-20 2004-02-17 Intel Corporation Fuse circuit utilizing high voltage transistors
US6855985B2 (en) 2002-09-29 2005-02-15 Advanced Analogic Technologies, Inc. Modular bipolar-CMOS-DMOS analog integrated circuit & power transistor technology
US7638841B2 (en) 2003-05-20 2009-12-29 Fairchild Semiconductor Corporation Power semiconductor devices and methods of manufacture
US7002398B2 (en) 2004-07-08 2006-02-21 Power Integrations, Inc. Method and apparatus for controlling a circuit with a high voltage sense device
US7102951B2 (en) 2004-11-01 2006-09-05 Intel Corporation OTP antifuse cell and cell array
US7268577B2 (en) 2004-12-17 2007-09-11 International Business Machines Corporation Changing chip function based on fuse states
KR101146972B1 (ko) 2005-03-16 2012-05-22 페어차일드코리아반도체 주식회사 고내압 다이오드를 갖는 고전압 집적회로 장치
KR20100079705A (ko) 2008-12-31 2010-07-08 주식회사 동부하이텍 수평형 디모스 소자
US8207580B2 (en) 2009-05-29 2012-06-26 Power Integrations, Inc. Power integrated circuit device with incorporated sense FET
US8164125B2 (en) * 2010-05-07 2012-04-24 Power Integrations, Inc. Integrated transistor and anti-fuse as programming element for a high-voltage integrated circuit
US7932738B1 (en) 2010-05-07 2011-04-26 Power Integrations, Inc. Method and apparatus for reading a programmable anti-fuse element in a high-voltage integrated circuit
US8854065B2 (en) 2012-01-13 2014-10-07 Infineon Technologies Austria Ag Current measurement in a power transistor

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6168983B1 (en) * 1996-11-05 2001-01-02 Power Integrations, Inc. Method of making a high-voltage transistor with multiple lateral conduction layers
US20020132405A1 (en) * 2000-11-27 2002-09-19 Power Integrations, Inc. Method of fabricating a high-voltage transistor
US20030178646A1 (en) * 2001-01-24 2003-09-25 Power Integrations, Inc. High-voltage transistor with buried conduction layer
JP2004179351A (ja) * 2002-11-27 2004-06-24 Matsushita Electric Ind Co Ltd 接合電界効果トランジスタおよび接合電界効果トランジスタの製造方法
US20060284276A1 (en) * 2005-06-21 2006-12-21 Hamza Yilmaz High voltage semiconductor devices with JFET regions containing dielectrically isolated junctions
US20090315109A1 (en) * 2008-06-20 2009-12-24 Kim Min-Seok Semiconductor device having otp cells and method for fabricating the same

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