CN105493264A - 半导体集成电路装置 - Google Patents
半导体集成电路装置 Download PDFInfo
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Abstract
标准单元(1)具有沿第一方向延伸的鳍片(11)。由沿垂直于第一方向的第二方向延伸且被设置在鳍片(11)上的栅极布线(12)、以及鳍片(11)构成有源晶体管(N1)。由鳍片(11)和与栅极布线(12)并列设置的虚拟栅极布线(14)构成虚拟晶体管(D1),所述虚拟晶体管(D1)与有源晶体管(N1)共用源极的节点和漏极的节点中的一节点。
Description
技术领域
本申请涉及一种半导体集成电路装置,该半导体集成电路装置包括使用鳍片(fin)结构的晶体管的标准单元。
背景技术
作为在半导体基板上形成半导体集成电路的方法,标准单元法已为人所知。标准单元法是指,预先准备好具有特定逻辑功能的基本单位(例如,反相器、锁存器、触发器以及全加器等)以作为标准单元,然后将多个标准单元布置在半导体基板上后,将这些标准单元之间用布线连接起来,由此设计出LSI(LargeScaleIntegration,大规模集成电路)芯片的方法。
近年来,在半导体器件领域,提出了利用鳍片结构的晶体管(以下称作“鳍式晶体管”)的方案。图12是示出鳍式晶体管的简要结构的示意图。不同于现有二维结构的MOS(Metal-OxideSemiconductor,金属氧化物半导体)晶体管,鳍式晶体管的源极和漏极具有被称为鳍片的隆起的立体结构。并且鳍式晶体管的栅极以围住该鳍片的方式布置。借助这样的鳍片结构,沟道区域就会由鳍片的三个面形成,因此,与现有结构相比,对沟道的控制性得到了大幅改善。由此,能够实现减少漏功率、提高通态电流、以及降低工作电压等效果,从而能够提高半导体集成电路的性能。
作为对鳍片结构制作方面的改进,专利文献1中示出了下述方法,即,使鳍片的形成方向与硅基板的结晶方向相一致后,选择性地进行蚀刻的方法。
专利文献1:日本公开专利公报特开2008-219002号
发明内容
-发明所要解决的技术问题-
就鳍片结构而言,鳍片未必会在其整个长度方向上均一地形成。即,鳍片的宽度未必在其整个长度方向上都相等,会产生一定程度的偏差。特别是,鳍片的宽度有越靠近鳍片的终端部越变窄的倾向。由此,如果将晶体管形成在鳍片的终端部附近,就很有可能无法获得所期望的性能。
另外,将布线、接触部(contact)连接到鳍片的终端部上时,就有可能因鳍片的终端部出现形成不良及/或布线、接触部的掩膜位置错位,而导致鳍片与布线、接触部的电气接触劣化,使得电阻特性产生偏差。该偏差有可能导致半导体芯片的成品率降低。
本申请的目的在于:在包括使用鳍式晶体管的标准单元的半导体集成电路装置中,能够抑制鳍片终端部的宽度变窄所造成的影响,从而能够抑制性能偏差。
-用以解决技术问题的技术方案-
本申请的一个方案为:半导体集成电路装置包括具有沿第一方向延伸的鳍片的标准单元,所述标准单元包括:有源晶体管(activetransistor),其由所述鳍片和栅极布线构成,所述栅极布线沿垂直于所述第一方向的第二方向延伸且被设置在所述鳍片上;以及虚拟晶体管(dummytransistor),其由所述鳍片和虚拟栅极布线构成,所述虚拟栅极布线与所述栅极布线并列设置在所述鳍片上,所述虚拟晶体管与所述有源晶体管共用源极的节点和漏极的节点中的一节点。
根据该方案,因为有虚拟晶体管存在,所以有源晶体管的源极的节点和漏极的节点中的一节点就会位于离开鳍片终端部附近的位置。即,鳍片宽度很可能变窄的鳍片终端部偏离开有源晶体管的节点所在的位置。由此,能够避免鳍片终端部的宽度变窄对有源晶体管所造成的影响,从而能够抑制有源晶体管的性能偏差。
-发明的效果-
根据本申请,在包括使用鳍式晶体管的标准单元的半导体集成电路装置中,能够抑制鳍片终端部的宽度变窄所造成的影响。因此,能够抑制半导体集成电路装置的性能偏差。
附图说明
图1是示出第一实施方式所涉及的半导体集成电路装置具备的标准单元的布局结构示例的俯视图。
图2是图1中的标准单元的电路图。
图3是示出图1中的布局结构的比较例的俯视图。
图4是示出第二实施方式所涉及的半导体集成电路装置具备的标准单元的布局结构示例的俯视图。
图5是示出图4中的布局结构的比较例的俯视图。
图6是示出在第二实施方式中的标准单元的其它布局结构示例的俯视图。
图7是示出在第二实施方式中的标准单元的其它布局结构示例的俯视图。
图8是示出在实施方式中的标准单元的其它布局结构示例的俯视图。
图9是图8中的标准单元的电路图。
图10是示出在实施方式中的标准单元的其它布局结构示例的俯视图。
图11是图10中的标准单元的电路图。
图12是示出鳍片结构的晶体管的简要结构的示意图。
具体实施方式
下面,参照附图对实施方式进行说明。在以下实施方式中,假设半导体集成电路装置包括多个标准单元,并且其中至少一部分标准单元使用鳍式晶体管。
此外,在本说明书中,将有助于标准单元的逻辑功能的晶体管称为“有源晶体管”,将有源晶体管以外的晶体管即对标准单元的逻辑功能没有助益的晶体管称为“虚拟晶体管”。
(第一实施方式)
图1是示出第一实施方式所涉及的半导体集成电路装置具备的标准单元的布局结构示例的俯视图。图2是图1中的标准单元的电路图。如图2所示,图1中的标准单元1是形成双输入NOR(或非)电路的单元。在图1和其它俯视图中,由鳍片和在该鳍片上形成的栅极来构成鳍式晶体管。局部布线在当俯视时与鳍片或者栅极重叠的部分形成为与鳍片或者栅极中的上侧部分抵接,从而电连接。金属布线位于局部布线的上层,并经由接触部而与局部布线连接。需要说明的是,在图1中,为了便于看图,对鳍片标注了斜线。然而,对于位于栅极下侧的部分则未标注斜线。此外,对局部布线和金属布线也标注了种类不同的斜线,将金属布线与局部布线经由接触部连接的部分涂成了黑色。在其它俯视图中亦同。
如图1所示,标准单元1具有沿图1中的横向(第一方向)延伸的鳍片11、16。鳍片11用于在N型区域构成N型晶体管,鳍片16则用于在P型区域构成P型晶体管。即,由鳍片11和沿图1中的纵向(垂直于第一方向的第二方向)延伸且被设置在鳍片11上的栅极布线12、13分别构成有源晶体管即N型晶体管N1、N2。N型晶体管N1、N2共用漏极。另外,由鳍片16和沿图1中的纵向延伸且被设置在鳍片16上的栅极布线17、12、13、18分别构成有源晶体管即P型晶体管P1、P2、P3、P4。
在标准单元1的下端设置有沿图1中的横向延伸且供给接地电位的接地布线8a;在标准单元1的上端设置有沿图1中的横向延伸且供给电源电位的电源布线8h。在标准单元1的左右端分别设置有沿图1中的纵向延伸的虚拟栅极布线9a、9b。
进而,在鳍片11上构成有虚拟晶体管D1、D2。即,由鳍片11和与栅极布线12并列设置在鳍片11上的虚拟栅极布线14构成虚拟晶体管D1。N型晶体管N1与虚拟晶体管D1共用源极,作为电源电位之一例的接地电位被供给该源极。由鳍片11和与栅极布线13并列设置在鳍片11上的虚拟栅极布线15构成虚拟晶体管D2。N型晶体管N2与虚拟晶体管D2共用被供给接地电位的源极。虚拟晶体管D1、D2的源极、漏极以及栅极都连接到作为电源布线之一例的接地布线8a上。
N型晶体管N1与虚拟晶体管D1共用源极,并与作为第三晶体管的N型晶体管N2共用漏极。N型晶体管N2与虚拟晶体管D2共用源极,并与作为第三晶体管的N型晶体管N1共用漏极。即,在图1中的布局结构下,在N型区域,所有的有源晶体管N1、N2与其它晶体管共用源极和漏极两者的节点。
根据图1中的布局结构,在鳍片11的终端部附近构成有虚拟晶体管D1、D2,有源晶体管即N型晶体管N1、N2被布置在离开鳍片11终端部附近的位置。即,鳍片宽度很可能变窄的鳍片11的终端部偏离开有源晶体管N1、N2所在的位置。由此,能够避免鳍片11终端部的宽度变窄对有源晶体管N1、N2所造成的影响,从而能够抑制有源晶体管N1、N2的性能偏差,实现与局部布线良好的电气接触,提高半导体芯片的成品率。
图3是示出图1中的布局结构的比较例的俯视图。在图3的布局结构中,布置有比鳍片11短的鳍片11A,在鳍片11A的终端部(用一点划线示出)附近布置有N型晶体管N1、N2。没有形成虚拟晶体管。
如果只考虑实现图2中的NOR电路的逻辑功能的话,就不需要虚拟晶体管D1、D2。因此,如果只考虑实现图2中的NOR电路的逻辑功能,而不考虑鳍片终端部的宽度变窄所造成的影响来进行布局设计的话,就可以想到像图3那样的、不具备虚拟晶体管D1、D2的布局结构。
然而,在图3的布局结构中,由于N型晶体管N1、N2布置在鳍片11A的终端部,因而会受到由于鳍片11A终端部的宽度变窄所造成的影响,有可能无法获得所期望的性能。因此,如果采用图3中的布局结构的话,半导体芯片的性能产生偏差或者成品率降低的可能性就会很高。特别是,就构成传输时钟信号的时钟树的单元而言,因为需要抑制性能偏差,所以采用图1中的布局结构代替图3中的布局结构更为有效。当然,抑制偏差的效果不仅对于构成时钟树的单元有效,对其它单元也有效。
需要说明的是,在本实施方式中,假设作为有源晶体管的N型晶体管与虚拟晶体管共用源极,但并不限于此。例如,有源晶体管也可以与虚拟晶体管共用漏极。或者,也可以是这样的:作为有源晶体管的P型晶体管与虚拟晶体管共用源极或漏极。另外,也可以是这样的:与虚拟晶体管共用的源极的节点和漏极的节点中的另一节点被其它虚拟晶体管共用。或者,也可以是这样的:与虚拟晶体管共用的源极的节点和漏极的节点中的另一节点不被其它晶体管共用。
(第二实施方式)
图4是示出第二实施方式所涉及的半导体集成电路装置具备的标准单元的布局结构示例的俯视图。图4中的标准单元2是形成如图2中所示的双输入NOR电路的单元,图2中的各个晶体管分别由两个鳍片构成。
如图4所示,标准单元2具备沿图4中的横向(第一方向)延伸的鳍片11、16、21、22。鳍片11、21用于在N型区域形成N型晶体管,鳍片16、22则用于在P型区域形成P型晶体管。即,由鳍片11和沿图4中的纵向(垂直于第一方向的第二方向)延伸且被设置在鳍片11上的栅极布线12、13分别构成有源晶体管即N型晶体管N1、N2。由作为第二鳍片的鳍片21、和在鳍片21上延伸的栅极布线12、13分别构成作为第二有源晶体管的N型晶体管N1a、N2a。
由鳍片16和沿图4中的纵向延伸且被设置在鳍片16上的栅极布线17、12、13、18分别构成有源晶体管即P型晶体管P1、P2、P3、P4。由鳍片22和在鳍片22上延伸的栅极布线17、12、13、18分别构成P型晶体管P1a、P2a、P3a、P4a。
在标准单元2的下端设置有沿图4中的横向延伸且供给接地电位的接地布线8a,在标准单元2的上端设置有沿图4中的横向延伸且供给电源电位的电源布线8h。在标准单元2的左右端分别设置有沿图4中的纵向延伸的虚拟栅极布线9a、9b。
进而,在鳍片11上构成有虚拟晶体管D1、D2,在鳍片21上则构成有虚拟晶体管D1a、D2a。即,由鳍片11和与栅极布线12并列设置在鳍片11上的虚拟栅极布线14构成虚拟晶体管D1。此外,由鳍片11和与栅极布线13并列设置在鳍片11上的虚拟栅极布线15构成虚拟晶体管D2。N型晶体管N1与虚拟晶体管D1共用被供给接地电位的源极,N型晶体管N2与虚拟晶体管D2共用被供给接地电位的源极。而且,由鳍片21和在鳍片21上延伸的虚拟栅极布线14构成虚拟晶体管D1a。此外,由鳍片21和在鳍片21上延伸的虚拟栅极布线15构成虚拟晶体管D2a。N型晶体管N1a与虚拟晶体管D1a共用被供给接地电位的源极,N型晶体管N2a与虚拟晶体管D2a共用被供给接地电位的源极。虚拟晶体管D1、D2、D1a、D2a的源极、漏极以及栅极都连接到接地布线8a上。
N型晶体管N1与虚拟晶体管D1共用源极,并与N型晶体管N2共用漏极。N型晶体管N2与虚拟晶体管D2共用源极,并与N型晶体管N1共用漏极。N型晶体管N1a与虚拟晶体管D1a共用源极,并与N型晶体管N2a共用漏极。N型晶体管N2a与虚拟晶体管D2a共用源极,并与N型晶体管N1a共用漏极。即,在图4中的布局结构下,在N型区域,所有的有源晶体管N1、N2、N1a、N1b与其它晶体管共用源极和漏极两者的节点。
根据图4中的布局结构,在鳍片11的终端部附近布置有虚拟晶体管D1、D2,N型晶体管N1、N2被布置在离开鳍片11终端部附近的位置。即,鳍片宽度很可能变窄的鳍片11终端部偏离开有源晶体管N1、N2所在的位置。再有,在鳍片21的终端部附近布置有虚拟晶体管D1a、D2a,N型晶体管N1a、N2a被布置在离开鳍片21终端部附近的位置。即,鳍片宽度很可能变窄的鳍片21终端部偏离开有源晶体管N1a、N2a所在的位置。由此,能够避免鳍片11终端部的宽度变窄对有源晶体管N1、N2所造成的影响、以及鳍片21终端部的宽度变窄对有源晶体管N1a、N1b所造成的影响,从而能够抑制有源晶体管N1、N2、N1a、N1b的性能偏差,实现与局部布线良好的电气接触,提高半导体芯片的成品率。
图5是示出图4中的布局结构的比较例的俯视图。在图5的布局结构中,为了形成N型晶体管只设置有一个鳍片11B,在该鳍片11B终端部(用一点划线示出)的附近布置有N型晶体管N1a、N1b。没有形成虚拟晶体管。
若当各个晶体管由两个鳍片构成时在不考虑鳍片终端部的宽度变窄所造成的影响的情况下对图2中所示的NOR电路(但不包括虚拟晶体管D1、D2)进行布局设计的话,就可以想到像图5那样的布局结构。
在图5的布局结构中,由于N型晶体管N1a、N2a布置在鳍片11B的终端部附近,因而会受到由于鳍片11B终端部的宽度变窄所造成的影响,有可能无法获得所期望的性能。因此,如果采用图5中的布局结构,半导体芯片的性能产生偏差或者成品率降低的可能性就会很高。特别是,就构成传输时钟信号的时钟树的单元而言,因为需要抑制性能偏差,所以采用图4中的布局结构代替图5中的布局结构是较为有效的。当然,抑制偏差的这一效果不仅对于构成时钟树的单元有效,对其它单元也有效。
图6是示出在本实施方式中的标准单元的其它布局结构示例的俯视图。图6中的标准单元2A是形成与图4相同的电路结构的单元,但N型晶体管N1、N2、N1a、N1b分别与虚拟晶体管D1、D2、D1a、D2a共用漏极。虚拟晶体管D1、D2、D1a、D2a的源极和栅极连接到接地布线8a上。
与图4中的布局结构同样,在图6中的布局结构下,鳍片宽度很可能变窄的鳍片11、21终端部被布置在偏离开有源晶体管N1、N2、N1a、N2a所在的位置。由此,能够避免鳍片11终端部的宽度变窄对有源晶体管N1、N2所造成的影响、以及鳍片21终端部的宽度变窄对有源晶体管N1a、N1b所造成的影响,从而能够抑制有源晶体管N1、N2、N1a、N1b的性能偏差。
图7是示出在本实施方式中的标准单元的其它布局结构示例的俯视图。图7中的标准单元2B是形成与图4相同的电路结构的单元,但N型晶体管N1、N2、N1a、N1b分别与虚拟晶体管共用漏极和源极两者。P型晶体管P1、P4、P1a、P4a分别与虚拟晶体管共用漏极。
也就是说,在区域DN1,由鳍片31、32和虚拟栅极布线33构成与N型晶体管N1、N1a共用源极的虚拟晶体管。在区域DN2,由鳍片31、32和虚拟栅极布线34构成与N型晶体管N1、N1a共用漏极的虚拟晶体管,由鳍片31、32和虚拟栅极布线35构成与N型晶体管N2、N2a共用漏极的虚拟晶体管。在区域DN3,由鳍片31、32和虚拟栅极布线36构成与N型晶体管N2、N2a共用源极的虚拟晶体管。
另外,在区域DP1,由鳍片37、38和虚拟栅极布线39构成与P型晶体管P1、P1a共用漏极的虚拟晶体管。在区域DP2,由鳍片37、38和虚拟栅极布线40构成与P型晶体管P4、P4a共用漏极的虚拟晶体管。
在图7中的布局结构下也能够实现与图4中的布局结构相同的效果。需要说明的是,在图7的布局结构下,在标准单元2B中的所有的有源晶体管N1、N2、N1a、N2a、P1、P2、P3、P4、P1a、P2a、P3a、P4a与其它晶体管共用源极和漏极两者的节点,因此,上述所有的有源晶体管N1、N2、N1a、N2a、P1、P2、P3、P4、P1a、P2a、P3a、P4a都被布置在离开鳍片31、32、37、38的终端部的位置上,从而能够抑制所有的有源晶体管的性能偏差。
(其它布局结构示例)
图8是示出在实施方式中的标准单元的其它布局结构示例的俯视图,图9是图8中的标准单元的电路图。其中,图9中的各个晶体管在图8中分别由两个鳍片构成。在图8的布局结构下,在鳍片41、42的终端部形成有虚拟晶体管。在图8中位于左侧的区域DN4,由鳍片41、42和虚拟栅极布线43、44构成虚拟晶体管。在图8中位于右侧的区域DN5,由鳍片41、42和虚拟栅极布线45、46构成虚拟晶体管。
图10是示出在实施方式中的标准单元的其它布局结构示例的俯视图,图11是图10中的标准单元的电路图。其中,图11中的各个晶体管在图10中分别由两个鳍片构成。在图10中的布局结构下,在鳍片51、52的终端部形成有虚拟晶体管。在图10中位于左侧的区域DN6,由鳍片51、52和虚拟栅极布线53构成虚拟晶体管。在图10中位于右侧的区域DN7,由鳍片51、52和虚拟栅极布线54、55、56构成虚拟晶体管。
需要说明的是,在上述实施方式中以NOR电路为例进行了说明,但不限于此。本申请同样可以适用于实现例如反相器、NAND(与非)电路以及触发器等所具有的其它逻辑功能的半导体集成电路装置。
此外,在上述实施方式中,就虚拟晶体管而言,例如当该虚拟晶体管是N型晶体管时,采用了对栅极供给接地电位并使栅极电位保持一定不变的结构,但并不限于此。也可以采用对逻辑功能没有贡献作用的其它结构。例如当该虚拟晶体管是N型晶体管时,也可以对栅极供给电源电位,对源极和漏极供给接地电位。
-产业实用性-
根据本申请,在包括使用鳍式晶体管的标准单元的半导体集成电路装置中,能够抑制鳍片终端部的宽度变窄所造成的影响。因此,对抑制半导体集成电路装置的性能偏差很有用。
-符号说明-
1、2、2A、2B标准单元
8a接地布线(电源布线)
11鳍片
12、13栅极布线
14、15虚拟栅极布线
16、22鳍片
21鳍片(第二鳍片)
31、32、37、38鳍片
33、34、35、36、39、40虚拟栅极布线
41、42鳍片
43、44、45、46虚拟栅极布线
51、52鳍片
53、54、55、56虚拟栅极布线
N1、N2、N1a、N2a有源晶体管
D1、D2、D1a、D2a虚拟晶体管
Claims (11)
1.一种半导体集成电路装置,其特征在于:
所述半导体集成电路装置包括具有沿第一方向延伸的鳍片的标准单元,
所述标准单元包括:
有源晶体管,其由所述鳍片和栅极布线构成,所述栅极布线沿垂直于所述第一方向的第二方向延伸且被设置在所述鳍片上;以及
虚拟晶体管,其由所述鳍片和虚拟栅极布线构成,所述虚拟栅极布线与所述栅极布线并列地设置在所述鳍片上,所述虚拟晶体管与所述有源晶体管共用源极的节点和漏极的节点中的一节点。
2.根据权利要求1所述的半导体集成电路装置,其特征在于:
所述标准单元包括第三晶体管,该第三晶体管由所述鳍片和第二栅极布线构成,所述第二栅极布线以与所述栅极布线并列且位于以所述栅极布线为基准的与所述虚拟栅极布线相反一侧的位置上的方式设置在所述鳍片上,所述第三晶体管与所述有源晶体管共用源极的节点和漏极的节点中的另一节点。
3.根据权利要求2所述的半导体集成电路装置,其特征在于:
所述第三晶体管为有源晶体管。
4.根据权利要求2所述的半导体集成电路装置,其特征在于:
所述第三晶体管为虚拟晶体管。
5.根据权利要求1所述的半导体集成电路装置,其特征在于:
所述有源晶体管与所述虚拟晶体管共用的节点为被供给电源电位的源极。
6.根据权利要求5所述的半导体集成电路装置,其特征在于:
所述虚拟晶体管的源极、漏极以及栅极都连接到电源布线上。
7.根据权利要求1所述的半导体集成电路装置,其特征在于:
所述有源晶体管与所述虚拟晶体管共用的节点是漏极的节点,所述虚拟晶体管的源极和栅极连接到电源布线上。
8.根据权利要求1所述的半导体集成电路装置,其特征在于:
所述标准单元具有第二鳍片,该第二鳍片在形成有所述鳍片的第一导电型区域与所述鳍片并列而设,
所述栅极布线以及所述虚拟栅极布线都延伸至所述第二鳍片上,
所述标准单元包括:
第二有源晶体管,其由所述第二鳍片和所述栅极布线构成;以及
第二虚拟晶体管,其由所述第二鳍片和所述虚拟栅极布线构成,并且与所述第二有源晶体管共用源极的节点和漏极的节点中的一节点。
9.根据权利要求1所述的半导体集成电路装置,其特征在于:
在所述标准单元中,在形成有所述鳍片的第一导电型区域,所有的有源晶体管与其它晶体管共用源极和漏极两者的节点。
10.根据权利要求9所述的半导体集成电路装置,其特征在于:
在所述标准单元中,所有的有源晶体管与其它晶体管共用源极和漏极两者的节点。
11.根据权利要求1所述的半导体集成电路装置,其特征在于:
所述标准单元为构成时钟树的单元。
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WO2015025441A1 (ja) | 2015-02-26 |
JPWO2015025441A1 (ja) | 2017-03-02 |
US20180130799A1 (en) | 2018-05-10 |
US20190109133A1 (en) | 2019-04-11 |
US20160172360A1 (en) | 2016-06-16 |
US20230387116A1 (en) | 2023-11-30 |
US11362088B2 (en) | 2022-06-14 |
CN105493264B (zh) | 2018-06-01 |
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US10833075B2 (en) | 2020-11-10 |
US20220278096A1 (en) | 2022-09-01 |
CN108630607A (zh) | 2018-10-09 |
US20210013201A1 (en) | 2021-01-14 |
US10181469B2 (en) | 2019-01-15 |
US9899381B2 (en) | 2018-02-20 |
US11764217B2 (en) | 2023-09-19 |
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