CN103187450A - 具有高击穿电压的半导体器件及其制造方法 - Google Patents

具有高击穿电压的半导体器件及其制造方法 Download PDF

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CN103187450A
CN103187450A CN2012105851788A CN201210585178A CN103187450A CN 103187450 A CN103187450 A CN 103187450A CN 2012105851788 A CN2012105851788 A CN 2012105851788A CN 201210585178 A CN201210585178 A CN 201210585178A CN 103187450 A CN103187450 A CN 103187450A
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back gate
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CN103187450B (zh
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高田和彦
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Socionext Inc
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Fujitsu Semiconductor Ltd
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Abstract

一种半导体器件及其制造方法，该半导体器件包括：第一和第二n型阱，形成在p型半导体衬底中，第二n型阱深于第一n型阱；第一和第二p型背栅区，形成在第一和第二n型阱中；第一和第二n型源极区，形成在第一和第二p型背栅区中；第一和第二n型漏极区，形成在第一和第二n型阱中，且位于与第一和第二n型源极区相对的位置处，将第一和第二p型背栅区夹在中间；以及场隔离膜，形成在该衬底上，该场隔离膜在第一和第二p型背栅区之间以及第一和第二n型漏极区之间的位置处；由此第一晶体管形成在第一n型阱中，而具有高于第一晶体管的反向电压耐受性的第二晶体管形成在第二n型阱中。本发明可形成具有反向电压耐受性的高击穿电压MOS晶体管。

Description

具有高击穿电压的半导体器件及其制造方法
技术领域
本发明的实施例涉及一种半导体器件及其生产过程。
背景技术
近年来，例如汽车的电子控制业已得到研发。已经花费了大量精力来研发将数字电路和高击穿电压晶体管合成一个系统的LSI芯片。例如，作为高击穿电压晶体管的DMOS（双扩散MOS）晶体管是众所周知的。例如，在n沟道晶体管中，p型背栅区形成在n型外延层的表面部分中，而n+型源极区形成在该p型背栅区中。N型漏极区形成为与源极区相对，并将n型外延层和p型背栅区的部分夹在其间。即使当没有通过扩散形成浓度梯度时，这种具有源极区和周围背栅区的双结构的晶体管结构也被称为DMOS晶体管。
例如，n型外延层在p型硅衬底上生长，而p型背栅区形成在该n型外延层中。N+型源极区形成在p型背栅区中，而p型背栅区和n+型源极区连接至相同的电位。P型背栅区暴露在邻近源极区的表面的部分构成沟道区，而n型漏极区形成在与沟道区相对的n型外延层中，在n型漏极区和沟道区之间夹有LOCOS场隔离膜。N型高浓度区形成在沟道区和LOCOS场隔离膜之间，而栅隔离膜形成在沟道区和n型高浓度区上。栅电极形成在栅隔离膜上，且延伸至LOCOS场隔离膜上。因此，形成DMOS晶体管。施加到漏极区的高压通过位于LOCOS场隔离膜下方的n型区的电阻在平行于表面的方向上被减小（例如，参见日本未经审查的专利申请公布（Kokai）第2009239096号）。
通过使用外延生长制造的衬底是昂贵的。为了降低成本，优选地，不使用外延衬底来形成高击穿电压晶体管。
车载LSI被称为CAN（控制器局域网）驱动器。CAN被设计为用于在电子模块之间通过通用总线进行通信，且通常由电池电源（12V到24V）施加电压。即使由于某些移动故障使LSI与接地断开，也不需要改变总线电位。为了满足这种需要，DMOS晶体管应当耐受反向极性电压。耐受极性反向于正常施加的电压极性的电压的能力被称为反向电压耐受性（reverse voltagedurability）。
发明内容
本发明的一个目的在于提供一种半导体器件及其制造方法，在该半导体器件中，具有反向电压耐受性的高击穿电压MOS晶体管与其他类型半导体元件同时存在。
根据本发明的一个方案，一种装置包括：
p型半导体衬底；
第一n型阱，形成在该p型半导体衬底中，该第一n型阱距所述衬底表面具有第一深度；
第二n型阱，形成在该p型半导体衬底中，该第二n型阱距所述衬底表面具有第二深度，所述第二深度小于所述第一深度；
第一p型背栅区和第二p型背栅区，分别形成在所述第一n型阱和所述第二n型阱中；
第一n型源极区和第二n型源极区，分别形成在所述第一p型背栅区和所述第二p型背栅区中；
第一n型漏极区和第二n型漏极区，分别形成在所述第一n型阱和所述第二n型阱中，且位于与所述第一n型源极区和所述第二n型源极区相对的位置处，所述第一p型背栅区和所述第二p型背栅区位于所述第一n型漏极区与第二n型漏极区之间；以及
场隔离膜，形成在所述衬底上，所述场隔离膜分别在所述第一p型背栅区和所述第二p型背栅区之间以及所述第一n型漏极区和所述第二n型漏极区之间的位置处；
其中具有低反向电压耐受性的第一晶体管形成在所述第一n型阱中，而具有高于所述第一晶体管的反向电压耐受性的第二晶体管形成在所述第二n型阱中。
根据本发明的另一个方案，一种制造装置的方法包括：
通过将n型杂质离子注入到p型半导体衬底中来形成第一n型阱；
通过热处理使所述第一n型阱的所述n型杂质扩散，从而形成深度增加的第一扩大n型阱；
在所述p型半导体衬底中形成隔离膜；
通过在所述p型半导体衬底中进行n型杂质的离子注入来形成第二n型阱，所述第二n型阱浅于所述第一扩大n型阱；
通过在所述第一扩大n型阱和所述第二n型阱中进行p型杂质的离子注入来形成第一p型背栅区和第二p型背栅区；
形成第一栅电极和第二栅电极，所述第一栅电极和第二栅电极从所述第一背栅区和所述第二背栅区上方延伸至所述隔离膜上；
通过在所述第一背栅区和所述第二背栅区中进行n型杂质的离子注入来形成第一n型源极区和第二n型源极区；以及
通过在与所述第一n型源极区和所述第二n型源极区相对的位置处进行n型杂质的离子注入来形成第一n型漏极区和第二n型漏极区，在所述第一扩大n型阱和所述第二n型阱中的所述第一背栅区和所述第二背栅区以及场隔离膜位于所述第一n型漏极区与第二n型漏极区之间。
附图说明
图1是示出根据本发明的实施例的高击穿电压晶体管的两个基本构造的剖面图。
图2A到图2S是示出根据本发明的实施例的包括多个不同类型的半导体元件的半导体器件制造过程的主要步骤的剖面图。
图3A和图3B是常规高压NDMOS晶体管的剖面图和局部截断平面图，图3C和图3D是反向电压耐受的高击穿电压NDMOS晶体管的剖面图和局部截断平面图，以及图3E是列出其特征的比较值的表格。
图4A和图4B是用于保护常规高压NMOS晶体管的齐纳二极管的剖面图和局部截断平面图，图4C和图4D是用于保护反向电压耐受的高击穿电压NMOS晶体管的齐纳二极管的剖面图和局部截断平面图，以及图4E是列出尺寸a、b和c的比较值的表格。
图5A是示出CAN系统应用的等效电路图，以及图5B是由图5A中的虚线限定的局部放大图。
具体实施方式
图1示出形成在p型硅衬底上的两个不同的n型DMOS晶体管。
如图1的右手部分所示，通过在高加速能量下进行离子注入形成n型漂移区ND1。常用的离子注入设备具有大约2MeV的最大加速能量。在注入P+离子的情况下，离子注入可形成深度约2.5μm的n型区。例如，通过公知方法，在硅衬底Psub的表面上形成氧化硅的浅沟槽隔离（STI），其可作为场隔离膜、器件隔离区等。由于制造STI不需要伴随杂质扩散的高温处理，因此，处理步骤的顺序可以各种方式改变。
在n型漂移区ND1中注入p型杂质以形成p型背栅阱PBG1。n型源极区S1形成在p型背栅阱PBG1中。夹在n型源极区S1与n型漂移区ND1之间的p型背栅阱PBG1的表面部分可构成沟道区CH1。N型漏极区D1经由STI布置在n型漂移区ND1中位于沟道区CH1的那侧上，该n型漏极区D1与n型源极区S1相对。用这种方式形成栅电极G1，使其覆盖沟道区CH1并延伸至STI区上。在下文中，连接至半导体区域的电极将被赋予与半导体区域相同的符号。衬底偏压电极SB连接至p型衬底Psub。因此，形成高击穿电压DMOS晶体管。
这里，假设高击穿电压DMOS晶体管由于某种原因或故障与接地断开。向漏极D1施加有例如相当于电源电压（12V到24V）的电压，且如果衬底与接地断开，衬底电压将在高压区的影响下提高到相当于电源电压（12V到24V）的电压。在连接至其它LSI的端子处的电压将保持在大约0V到4.1V，这取决于其它器件的正常电压状态。因此，在这种端子处的电压变得低于衬底电压。似乎是端子接收负电压。如果其不能耐受负电压，就可能将电源偏压从衬底施加到端子而干扰与其它LSI的通信，并且在最坏的情况下甚至可能导致部分部件的损坏。
高压将被施加到漏极D1，并且在大多数情况下，p型背栅阱PBG1和p型衬底Psub通常将处在大约接地电位（ground potential），即在几乎相同的电位处。因此，器件不需要耐受p型背栅阱PBG1和p型衬底Psub之间的高压的能力。然而，如果接地被断开或浮置，在p型衬底Psub上的电位将变得几乎等于电源电位（12V到24V），且p型背栅阱PBG1将具有几乎等于接地的电位。如果p型背栅阱PBG1与p型衬底Psub彼此间距离较小，则在p型背栅阱PBG1与p型衬底Psub之间的n型漂移区ND1将很容易穿通（punch through）。
对要耐受当接地故障发生而提高衬底电位时产生的负电位的器件而言，期望其能够防止n型漂移区穿通。在n型漂移区中杂质浓度的增加将给高击穿特性带来不利影响。因此，增加p型背栅阱PBG与p型衬底Psub之间的距离是可取的。当通过离子注入形成n型漂移区时，通过可用的加速能量来限制n型漂移区的深度。用于形成更深的n型漂移区的有效方法是在离子注入之后执行热扩散。
如图1的左手部分所示，首先执行对第二n型漂移区ND2的离子注入，然后通过热扩散使杂质分布变宽以形成更深的n型漂移区ND2。例如，在2MeV的加速能量下注入P+离子，然后在1,150℃下执行热处理6小时以使注入的杂质扩散，从而形成具有8μm量级深度的第二n型漂移区ND2。热扩散在面内（inplane）方向上发生，同时还在深度方向上发生，因此，增加了第二n型漂移区ND2的尺寸。例如，在形成背栅阱之后存留的第二n型漂移区被设计为具有即使在厚度方向上施加电源电压时也不能穿通的厚度。例如，在该阶段，可实现器件隔离区STI的形成。
在2MeV的加速能量下再次执行P+离子注入以形成如图1的右手部分所示的第一n型漂移区ND1。可形成较小的第一n型漂移区ND1。接着，参见在图1的右手部分中绘出的DMOS晶体管，执行如上所述的步骤以例如形成p型背栅阱PBG1和PBG2、栅电极G1和G2、n型源极区S1和S2、n型漏极区D1和D2、以及衬底偏压区SB。作为夹在p型背栅阱PBG2与p型衬底Psub之间的第二n型漂移区ND2的厚度增加的结果，可防止背栅区PBG2与衬底Psub之间的穿通。
用这种方法，可制造具有反向电压耐受性的高击穿电压DMOS晶体管NDMOS2，并且可在较小区域中制造不需要反向电压耐受性的高击穿电压DMOS晶体管NDMOS1。由于可以使用不具有外延层的常规衬底，因此可控制制造成本，并且还可以利用用常规衬底形成电路的设计资源。
下面将对根据实施例的半导体器件制造方法进行更详细的描述。例如，制备具有10Ωcm电阻率的p型硅衬底Psub。例如，在p型硅衬底中分配有六个区域，即，反向电压耐受的（RVD）齐纳二极管（ZD）形成区、反向电压耐受NDMOS形成区、常规高压（NHV）PMOS形成区、常规NDMOS形成区、常规齐纳二极管（ZD）形成区、以及逻辑晶体管形成区。作为示例，下面将对在逻辑晶体管形成区中形成1.8V驱动逻辑晶体管和5.0V驱动逻辑晶体管的情况进行描述。
在图2A中，上部绘出反向电压耐受齐纳二极管（ZD）形成区和反向电压耐受NDMOS形成区，中间部分绘出常规高压PMOS形成区和常规NDMOS形成区，以及下部绘出常规齐纳二极管（ZD）形成区和逻辑晶体管形成区。这六个区域被分配在一个p型硅衬底Psub上。将在所有随后的附图中的相同位置处绘出所述六个区域。通过热氧化在p型硅衬底Psub的表面上生长具有10nm量级厚度的氧化硅膜以作为衬底保护氧化膜ox1。
如图2B所示，形成抗蚀剂掩模RM1，该抗蚀剂掩模RM1在反向电压耐受NDMOS形成区和反向电压耐受齐纳二极管区具有开口，并在2MeV的加速能量和4.0×1012cm-2的剂量下注入P+离子以形成深度约2.5μm的n型阱1。接着，去除抗蚀剂掩模RM1。
如图2C所示，在1,150℃下的氮气气氛中执行热扩散处理6小时，使得n型阱1扩散以形成深度约8μm的n型阱2。N型阱2在反向电压耐受NDMOS区中起到如图1所示的n型漂移区ND2的作用。这里，形成深度约8μm的n型阱，旨在获得35V的反向电压耐受性。如果所需的耐受性更低，则深度可以更小和/或热处理条件可以放宽。然后，例如通过稀氢氟酸去除衬底保护氧化膜ox1。通过在900℃下进行热氧化使厚度例如约为15nm的新的氧化硅膜生长以作为衬底保护膜ox2。
如图2D所示，通过化学气相沉积（CVD）使厚度约150nm的氮化硅膜生长，并通过使用抗蚀剂图案等由热磷酸进行蚀刻来形成硬掩膜3，该硬掩膜3在与场氧化膜和器件隔离区对应的区域具有开口。在硬掩膜3下方的氧化膜ox2与硬掩膜（作为硬掩膜的部分）一并示出。
如图2E所示，通过使用氮化硅膜的硬掩膜3作为蚀刻掩模来去除衬底保护膜ox2的暴露部分，并蚀刻硅衬底的此暴露部分以形成深度约350nm的沟槽4。
如图2F所示，设置有沟槽的硅衬底Psub在1,100℃下在氧化气氛中经受退火（热氧化）以形成具有厚度约40nm的热氧化膜衬垫（liner）。接着，通过高密度等离子体（HDP）CVD使厚度例如为675nm的氧化硅膜生长以填充和嵌入沟槽，继而，通过化学机械抛光，抛光和去除在硬掩膜3上方的多余部分以形成浅沟槽隔离（STI）型场氧化膜和/或隔离区STI。
如图2G所示，通过热磷酸来去除氮化硅的硬掩膜3，以及通过稀释的氢氟酸来去除因此暴露的氧化硅的衬底保护膜ox2。因此暴露的硅衬底表面在900℃下在氧化气氛中经受热氧化以形成厚度约10nm的氧化硅膜的衬底保护膜ox3。
如图2H所示，抗蚀剂掩模RM3形成在硅衬底Psub的表面上，该抗蚀剂掩模RM3在待要形成于常规高压PMOS晶体管、常规NDMOS晶体管、以及常规齐纳二极管中的n型阱的区域具有开口，并且在2MeV的加速能量和2.5×1012cm-2的剂量下，以及在500keV的加速能量和1.5×1012cm-2的剂量下执行P+离子注入以形成深度约2.5μm的n型阱4。在常规NDMOS晶体管中的n型阱4起到如图1所示的n型漂移区ND1的作用。接着，去除抗蚀剂掩模RM3。
如图2I所示，抗蚀剂掩模RM4形成在硅衬底Psub上，该抗蚀剂掩模RM4在常规高压PMOS晶体管的p型漂移区具有开口，并在150KeV的加速能量和5.5×1012cm-2的剂量下执行B+离子注入以形成p型阱，该p型阱在常规高压PMOS晶体管中起到p型漂移区6的作用。接着，去除抗蚀剂掩模RM4。
如图2J所示，形成抗蚀剂掩模RM5，该抗蚀剂掩模RM5在待要形成常规NDMOS晶体管的p型背栅（PBG）阱和用于常规齐纳二极管的正极（A）的p型阱的区域具有开口，并且在420keV的加速能量和1.2×1013cm-2的剂量下、在150keV的加速能量和5.0×1012cm-2的剂量下、以及在15keV的加速能量和1.0×1013cm-2的剂量下执行B+离子的三次注入以形成p型阱区7。接着，去除抗蚀剂掩模RM5。因此，形成深度约1.5μm的常规NDMOS晶体管的p型背栅（PBG）阱7和用于常规齐纳二极管的正极（A）的p型阱7。留在p型阱7下方的n型阱4在深度方向上的尺寸约为1μm。
如图2K所示，形成抗蚀剂掩模RM6，该抗蚀剂掩模RM6在待要形成反向电压耐受NDMOS晶体管的p型背栅阱和用于反向电压耐受齐纳二极管的正极（A）的p型阱的区域具有开口，并在420keV的加速能量和1.6×1013cm-2的剂量下、在150keV的加速能量和5.0×1012cm-2的剂量下、以及在15keV的加速能量和1.0×1013cm-2的剂量下执行B+离子的三次注入以形成p型阱区8。接着，去除抗蚀剂掩模RM6。深度约3.0μm的p型区形成在待要形成反向电压耐受NDMOS晶体管的p型背栅（PBG）阱8和用于反向电压耐受齐纳二极管的正极（A）的p型阱8的区域中。在p型阱8下方的n型阱2在深度方向上的尺寸约为5μm。
能够形成从p型衬底Psub到p型背栅（PBG）区8的间距约为5μm的高反向电压耐受NDMOS结构，以及从p型衬底Psub到p型背栅（PBG）区7的间距约为1μm的低反向电压耐受DMOS。反向电压耐受NDMOS晶体管的P型背栅阱8深于常规NDMOS晶体管的p型背栅阱7。在p型背栅阱8下方的n型阱2厚于在p型阱7下方的n型阱4。
如图2L所示，使用各自的抗蚀剂掩模对用于5V驱动和1.8V驱动的CMOS晶体管的p型阱和n型阱进行离子注入。例如，在用于5V驱动的NMOS晶体管的区域中，在420keV的加速能量和2.0×1013cm-2的剂量下，以及在15keV的加速能量和4.0×1012cm-2的剂量下注入B+离子。在2MeV的加速能量和2.0×1013cm-2的剂量下执行P+离子注入。在用于5V驱动的PMOS晶体管的区域中，在600keV的加速能量和2.0×1012cm-2的剂量下，以及在60keV的加速能量和4.9×1012cm-2的剂量下注入P+离子。下面对在器件隔离区周围形成反向防止区的情况进行描述。在1,000℃下的氮气气氛中执行退火10秒以激活所注入的杂质。
同样地，例如在用于1.8V驱动的NMOS晶体管的区域中，在230keV的加速能量和3.0×1013cm-2的剂量下注入B+离子。在用于1.8V驱动的PMOS晶体管的区域中，在500keV的加速能量和2.8×1013cm-2的剂量下注入P+离子，并且还在180keV的加速能量和6.5×1012cm-2的剂量下注入As+离子。进而，为了1.8V驱动的NMOS晶体管的阈值控制，在13keV的加速能量和1.6×1013cm-2的剂量下注入B+离子。为了1.8V驱动的PMOS晶体管的阈值控制，在60keV的加速能量和1.3×1013cm-2的剂量下注入As+离子。在1,000℃下的氮气气氛中执行退火10秒以激活注入的杂质。
这里，逻辑晶体管具有公知结构。其可以通过公知制造过程形成。也可以采用各种公知的改型和替代。
如图2M所示，通过氢氟酸溶液去除先前形成的10nm厚的氧化硅的衬底保护膜，并在800℃下在潮湿的氧化气氛中使硅衬底的表面经受热氧化以生长厚度为15nm的氧化硅膜。在1.8V驱动的MOS晶体管区中，曾经通过氢氟酸溶液去除了氧化硅膜，并在潮湿的氧化气氛中使硅衬底的表面经受热氧化以生长厚度为3.2nm的新的氧化硅膜。先前形成的15nm厚的氧化硅膜的厚度增加，导致氧化硅膜的厚度为18nm。
接着，通过CVD在衬底的整个表面上方生长厚度为180nm的多晶硅膜。使用抗蚀剂掩模，在应变成n型的多晶硅膜中离子注入n型杂质，以及在应变成p型的多晶硅膜中离子注入p型杂质。在800℃下的氮气气氛中执行退火60秒以激活注入到多晶硅膜中的杂质。抗蚀剂掩模形成在多晶硅膜上，并使用抗蚀剂掩模作为蚀刻掩模来蚀刻多晶硅膜以图案化n型栅电极14和p型栅电极15。
如图2N所示，执行离子注入以形成1.8V驱动的CMOS晶体管的源/漏区。使用抗蚀剂掩模，在5keV的加速能量和3.0×1014cm-2的剂量下在PMOS区中注入BF2 +离子。因此，形成p型区16。可在20keV的加速能量和6.0×1013cm-2的剂量下通过P+离子的注入来形成袋区（pocket region）。使用另一个抗蚀剂掩模，在15keV的加速能量和5.0×1014cm-2的剂量下在NMOS区中注入As+离子。因此，形成n型区17。可在20keV的加速能量和1.0×1013cm-2的剂量下通过B+离子的注入来形成袋区。
接着，执行离子注入以形成p型区18，该p型区18将形成5V驱动的PMOS晶体管的LDD区、RVD和常规NMOS晶体管的p型背栅阱的接触部分、以及常规高压PMOS晶体管的源/漏区等。例如，在80keV的加速能量和4.5×1013cm-2的剂量下注入BF2 +离子。而且，执行离子注入以形成n型区19，该n型区19将形成5V驱动的NMOS晶体管的LDD区、RVD和常规NDMOS晶体管的源/漏结区、反向电压耐受区域的阱接触部分、NDMOS晶体管、以及齐纳二极管区。例如，在35keV的加速能量和4.0×1013cm-2的剂量下注入P+离子。
如图2O所示，例如，通过CVD在衬底的整个表面上方生长厚度为100nm的氧化硅膜，并执行诸如反应离子蚀刻（RIE）等各向异性蚀刻，以在栅电极侧壁上形成侧壁间隔部件20。
如图2P所示，形成覆盖n型区的抗蚀剂掩模RM11，并在5keV的加速能量和2.0×1015cm-2的剂量下注入B+离子，以及在8keV的加速能量和4.0×1014cm-2的剂量下注入F+离子，从而形成高浓度p型区21。接着，去除抗蚀剂掩模RM11。
如图2Q所示，形成覆盖p型区的抗蚀剂掩模RM12，并在15keV的加速能量和2.0×1015cm-2的剂量下注入P+离子以形成高浓度n型区22，该高浓度n型区22包括齐纳二极管的阴极区，以及n沟道晶体管的源/漏区。接着，去除抗蚀剂掩模RM12。
如图2R所示，形成抗蚀剂掩模RM13，该抗蚀剂掩模RM13在齐纳二极管的阴极上具有开口，并在65keV的加速能量和2.0×1013cm-2的剂量下注入用于齐纳电压调节的B+离子。因此，形成p型区23。接着，去除抗蚀剂掩模RM13。在1,000℃下的氮气气氛中执行退火10秒以激活所注入的杂质。
如图2S所示，使用厚度为6nm的钴膜，通过在540℃下的氮气气氛中进行硅化反应30秒执行硅化钴的初级形成、洗涤未反应的部分，以及在750℃下的氮气气氛中执行硅化钴的次级反应。因此，形成硅化物层24。形成层间隔离膜25，并嵌入导电塞PLG，以及形成布线26。用这种方法，可形成包括各种半导体元件的半导体器件。
由相同的离子注入形成的区域基本上具有等同的深度和等同的杂质分布。由相同的离子注入形成和由相同的热处理扩散的区域基本上具有等同的深度和等同的杂质分布。
图3A和图3B是常规高压NDMOS晶体管的剖面图和局部截断平面图，图3C和图3D是反向电压耐受、高击穿电压NDMOS晶体管的剖面图和局部截断平面图，以及图3E是对照列出各种特征的表格。在反向电压耐受NDMOS晶体管中，在n型漂移区Ndrift的离子注入之后，n型区通过热扩散而扩张，接着，扩张Ndrift区的深度和面积以获得足够高的反向电压耐受性。在常规NDMOS晶体管中，不执行积极的（positive）杂质的热扩散，因此，通过抗蚀剂掩模的尺寸和离子注入的加速能量来限制n型漂移区Ndrift的深度和面积，使得n型漂移区可容纳于较小空间中。
图4A和图4B是用于保护常规高压NDMOS晶体管的齐纳二极管的剖面图和局部截断平面图，图4C和图4D是用于保护高击穿电压NMOS晶体管的反向电压耐受齐纳二极管的剖面图和局部截断平面图，以及图4E给出了对尺寸a、b和c进行比较的表格。齐纳二极管区具有相同的尺寸。在用于保护反向电压耐受NDMOS晶体管的反向电压耐受齐纳二极管中，在齐纳二极管的阳极区周围的n型阱NW中注入离子，并接着通过热扩散来扩大n型区，由于n型阱NW的深度和面积上的增加，导致尺寸c增大了大约三倍。这能够确保对p型衬底的足够高的反向电压耐受性。对用于保护常规NMOS晶体管的常规齐纳二极管而言，其中不积极（positively）执行热杂质扩散，通过用于离子注入的抗蚀剂掩模的尺寸和加速能量来限制n型阱NW的深度和面积，使得其可容纳于较小区域中。
根据该实施例制造的半导体元件将具有如下特性：
常规NDMOS晶体管
阈值电压Vth：1.01V（在Vd处的电压Vg=15V，Psub=PBG=S=0V,Id=2μA）
接通状态电流Ion：5.79mA（在Vd处的漏极电流=40V，Psub=PBG=S=0V,Vg=5V）
BVsd：42V或更高（在Vg处的电压Vd=0V，Psub=PBG=S=0V，Id=0.1μA）
反向电压耐受性：-10V（p型背栅阱在Vd处的电压=0V，Psub=0V，G=S=浮置，p型背栅阱电流=-0.1μA）
反向电压耐受NDMOS晶体管
阈值电压Vth：1.0V（在Vd处的电压Vg=15V，Psub=PBG=S=0V，Id=2μA）
接通状态电流Ion：5.73mA(在Vd处的漏极电流=40V，Psub=PBG=S=0V,Vg=5V)
BVsd：42V或更高（在Vg处的电压Vd=0V，Psub=PBG=S=0V，Id=0.1μA）
反向电压耐受性：-35V（p型背栅阱在Vd处的电压=0V，Psub=0V，G=S=浮置，p型背栅阱电流=-0.1μA）
用于保护常规NDMOS晶体管的齐纳二极管
齐纳电压：6.5V
反向电压耐受性：-10V（在n阱处的阳极电压=0V，Psub=0V，阴极=浮置，阳极=0.1μA）
用于保护反向电压耐受NDMOS晶体管的齐纳二极管
齐纳电压：6.5V
反向电压耐受性：-35V（在n阱处的阳极电压=0V，Psub=0V，阴极=浮置，阳极=0.1μA）
CAN利用通用总线来进行多个车载模块之间的通信。作为（being of）车载型，正常施加的电压范围为电池电源电压（12V到24V）。即使当LSI由于某些移动故障而与GND断开时，也不需要改变CAN信号线的总线电位。
图5A是示出应用至CAN系统的等效电路图，以及图5B是由图5A中的虚线限定的局部放大图。对RTH端子而言，提供如虚线所示的接地故障保护电路以监测接地电位。RTH端子通常给出0.1V作为用于CAN总线的下部的标准电位。如图5B所示，接通状态电压通常被供应至反向电流阻挡电路，使得NDMOS处于接通状态以使RTH端子保持在等同于接地的电位。
如果接地故障检测电路检测到接地故障，则去往反向电流阻挡电路的输出被切断。半导体衬底电压已经增加，且此时NDMOS栅极电压等于总线电压以关闭NDMOS。在NDMOS的漏极处的浮置状态下的GND电位被切断。NDMOS栅极电压变为等于总线侧的RTH电位，且NDMOS沟道电压和源极电压也变为等于总线侧的RTH电位。因此得以保护总线。为了切断浮置状态的GND电位，NDMOS必须是反向电压耐受的。连接至反向电流阻挡NDMOS的漏极的GND的异常电压被NDMOS切断，从而能够防止异常电压被施加到RTH端子。
对反向电流阻挡NDMOS而言，即使当GND断开时也有必要将其与衬底电隔离。如果不是反向电压耐受的，即使其在电路中被断开，也允许电源电压被供应至RTH端子。使用如上述实施例中所述的反向电压耐受NDMOS和反向电压耐受齐纳二极管的来避免这一问题。反向电压耐受NDMOS用于经由电阻将p型背栅和源极连接至CAN的总线侧，并将漏极端子连接至其GND端子侧。
利用这种连接，高击穿电压DMOS的漏极侧端子阻挡LSI中由接地故障引起的反向电流，并且因此，电场通过n型漂移区被放宽以防止电池电压被施加到反向电压耐受NDMOS的栅氧化膜，从而防止栅极损坏。从p型衬底施加的电压通过反向电压耐受结构的p型背栅和n型漂移区被切断，从而能够防止电池电压泄漏到CAN的总线。
此处叙述的全部实例和条件性语言均是为了教示性的目的，试图帮助读者理解本发明以及发明人为了促进技术而贡献的概念，并应解释为不限制于这些具体描述的例子和条件，说明书中这些实例的组织也不是为了彰显本发明的优劣。尽管已详细描述了本发明的各实施例，然而应当可以理解，在不脱离本发明的精神和范围的前提下可以进行各种变化、替换和更改。

Claims (10)

1.一种半导体器件，包括：
p型半导体衬底；
第一n型阱，形成在该p型半导体衬底中，该第一n型阱距该衬底表面具有第一深度；
第二n型阱，形成在该p型半导体衬底中，该第二n型阱距该衬底表面具有第二深度，所述第二深度小于所述第一深度；
第一p型背栅区和第二p型背栅区，分别形成在所述第一n型阱和所述第二n型阱中；
第一n型源极区和第二n型源极区，分别形成在所述第一p型背栅区和所述第二p型背栅区中；
第一n型漏极区和第二n型漏极区，分别形成在所述第一n型阱和所述第二n型阱中，且位于与所述第一n型源极区和所述第二n型源极区相对的位置处，所述第一p型背栅区和所述第二p型背栅区位于所述第一n型漏极区与第二n型漏极区之间；以及
场隔离膜，形成在所述衬底上，所述场隔离膜分别在所述第一p型背栅区和所述第二p型背栅区之间以及所述第一n型漏极区和所述第二n型漏极区之间的位置处；
其中具有低反向电压耐受性的第一晶体管形成在所述第一n型阱中，而具有高于所述第一晶体管的反向电压耐受性的第二晶体管形成在所述第二n型阱中。
2.根据权利要求1所述的半导体器件，其中所述第一晶体管的面内区域小于所述第二晶体管的面内区域。
3.根据权利要求1所述的半导体器件，还包括第一齐纳二极管，所述第一齐纳二极管包括：
第三n型阱，形成为与所述第二n型阱的距所述p型半导体衬底的表面的深度和杂质浓度分布实质上相同；
第一p型阳极区，形成在所述第三n型阱中，该第一p型阳极区与所述第二p型背栅区的深度和杂质浓度分布实质上相同；以及
第一n型阴极区，形成在所述第一p型阳极区中，该第一n型阴极区与所述第二源极区的深度和杂质浓度分布实质上相同。
4.根据权利要求3所述的半导体器件，还包括第二齐纳二极管，所述第二齐纳二极管包括：
第四n型阱，形成为与所述第一n型阱的距所述p型半导体衬底的表面的深度和杂质浓度分布实质上相同；
第二p型阳极区，形成在所述第四n型阱中，该第二p型阳极区与所述第一p型背栅区的深度和杂质浓度分布实质上相同；以及
第二n型阴极区，形成在所述第二p型阳极区中，该第二n型阴极区与所述第一源极区的深度和杂质浓度分布实质上相同。
5.一种半导体器件制造方法，包括：
通过将n-型杂质离子注入到p-型半导体衬底中来形成第一n型阱；
通过热处理使所述第一n型阱的所述n型杂质扩散，从而形成深度增加的第一扩大n型阱；
在所述p型半导体衬底中形成隔离膜；
通过在所述p型半导体衬底中进行n型杂质的离子注入来形成第二n型阱，所述第二n型阱浅于所述第一扩大n型阱；
通过在所述第一扩大n型阱和所述第二n型阱中进行p型杂质的离子注入来形成第一p型背栅区和第二p型背栅区；
形成第一栅电极和第二栅电极，所述第一栅电极和第二栅电极从所述第一背栅区和所述第二背栅区上方延伸至所述隔离膜上；
通过在所述第一背栅区和所述第二背栅区中进行n型杂质的离子注入来形成第一n型源极区和第二n型源极区；以及
通过在与所述第一n型源极区和所述第二n型源极区相对的位置处进行n型杂质的离子注入来形成第一n型漏极区和第二n型漏极区，在所述第一扩大n型阱和所述第二n型阱中的所述第一背栅区和所述第二背栅区以及场隔离膜位于所述第一n型漏极区与第二n型漏极区之间。
6.根据权利要求5所述的半导体器件制造方法，其中通过在所述p型半导体衬底中形成沟槽，在所述沟槽中沉积隔离膜，并去除不必要的部分，从而形成所述隔离膜。
7.根据权利要求5所述的半导体器件制造方法，其中通过不同条件的离子注入来执行用于形成第一背栅区的离子注入和用于形成第二背栅区的离子注入。
8.根据权利要求5所述的半导体器件的制造方法，其中：
对第一n型阱的形成同时形成第三n型阱；
对第一p型背栅区的形成同时在所述第三n型阱中形成第一p型阳极区；以及
对第一n型源极区和第二n型源极区的形成同时在所述第一p型阳极区中形成第一n型阴极区，从而形成第一齐纳二极管。
9.根据权利要求5所述的半导体器件的制造方法，其中：
对第二n型阱的形成同时形成第四n型阱；
对第二p型背栅区的形成同时在所述第四n型阱中形成第二p型阳极区；以及
对第一n型源极区和第二n型源极区的形成同时在所述第二p型阳极区中形成第二n型阴极区，从而形成第二齐纳二极管。
10.一种CAN系统，包括多个通信模块和一反向电流阻挡电路，所述反向电流阻挡电路包括：
p型半导体衬底；
第一n型阱，形成在该p型半导体衬底中，该第一n型阱距该衬底表面具有第一深度；
第二n型阱，形成在该p型半导体衬底中，该第二n型阱距该衬底表面具有第二深度，所述第二深度小于所述第一深度；
第一p型背栅区和第二p型背栅区，分别形成在所述第一n型阱和所述第二n型阱中；
第一n型源极区和第二n型源极区，分别形成在所述第一p型背栅区和所述第二p型背栅区中；
第一n型漏极区和第二n型漏极区，分别形成在所述第一n型阱和所述第二n型阱中，且位于与所述第一n型源极区和所述第二n型源极区相对的位置处，所述第一p型背栅区和所述第二p型背栅区位于所述第一n型漏极区与第二n型漏极区之间；以及
场隔离膜，形成在所述衬底上，所述场隔离膜分别在所述第一p型背栅区和所述第二p型背栅区之间以及所述第一n型漏极区和所述第二n型漏极区之间的位置处；
其中具有反向电压耐受性的第一晶体管形成在所述第一n型阱中，而具有低于所述第一晶体管的反向电压耐受性的第二晶体管形成在所述第二n型阱中。
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