CN108346654B - 半导体装置 - Google Patents

半导体装置 Download PDF

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CN108346654B
CN108346654B CN201711266670.8A CN201711266670A CN108346654B CN 108346654 B CN108346654 B CN 108346654B CN 201711266670 A CN201711266670 A CN 201711266670A CN 108346654 B CN108346654 B CN 108346654B
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CN108346654A (zh
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张育麒
温文莹
邱瀚辉
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Nuvoton Technology Corp
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Abstract

本发明公开了一种半导体装置，包括高侧区域与低侧区域，其中的高侧区域包括多个半导体元件，且这些半导体元件中至少有两个不同操作电压的元件。在所述高侧区域中，还有至少一隔离结构位于所述不同操作电压的元件之间，以防止元件之间的短路。

Description

半导体装置
技术领域
本发明是有关于一种半导体装置的技术，且特别是有关于一种适用于半桥驱动电路(Half Bridge Gate Driver)的半导体装置。
背景技术
在一般半桥驱动电路会区分高侧(High Side)和低侧(Low Side)两个区域，而这两个区域的操作电压可能会相差到100V～600V以上，甚至到1200V。而目前的技术是在高压积体电路(High Voltage Integrated Circuit,HVIC)制作工艺中利用“埋层(又称NBL)”技术，以便对这两个区域进行电压隔离。
而信号是从低侧区域通过位准移位单元(level shift)电路传递至高侧区域，所以一般采用HVIC制作工艺所制作的半桥驱动IC，通常在高侧区域仅以高压元件完成。在高侧区域仅提供高压元件表示在高侧端只允许单一高电压操作。但是，由于高压元件的特性较差且元件布局规则(Layout rule)较大，实际应用上会影响整个芯片(Chip)的成本高及效能差等缺点。
发明内容
本发明提供一种半导体装置，能将低压元件用于高侧区域且可防止高低压元件之间的短路。
本发明的半导体装置，包括高侧区域与低侧区域，其中的高侧区域包括多个半导体元件，且这些半导体元件中至少有两个不同操作电压的元件。在所述高侧区域中，还有至少一隔离结构位于所述不同操作电压的元件之间。
在本发明的一实施例中，上述高侧区域的半导体元件是形成于一基板上，且高侧区域还可包括一第一导电型埋层(Buried Layer)，位于所述基板与所述半导体元件之间。
在本发明的一实施例中，上述隔离结构包括一第二导电型掺杂区，完全包覆不同操作电压的元件中的低压元件。
在本发明的一实施例中，上述第一导电型埋层为N型埋层，所述第二导电型掺杂区为P型掺杂区。
在本发明的一实施例中，上述隔离结构包括贯穿第一导电型埋层的浅沟渠隔离结构(STI)。
在本发明的一实施例中，上述隔离结构包括一第二导电型隔离区与一第二导电型埋层，第二导电型隔离区位于不同操作电压的元件之间，而第二导电型埋层是位于第二导电型隔离区底下的所述第一导电型埋层之间。
在本发明的一实施例中，上述第二导电型隔离区为完全空乏的(fully-depleted)。
在本发明的一实施例中，上述第一导电型埋层为N型埋层、第二导电型隔离区为P型隔离区以及第二导电型埋层为P型埋层，反之亦然。
在本发明的一实施例中，上述第二导电型隔离区的宽度可根据不同操作电压的元件之电位差而订定。
在本发明的一实施例中，其中所述低压元件包括低压N型金属氧化物半导体场效电晶体(LV NMOS)和低压P型金属氧化物半导体场效电晶体(LV PMOS)。
基于上述，本发明藉由在高侧区域内使用低压元件，以达到缩减元件尺寸的效果，且使用低压元件设计一般逻辑运算，再以高压输出会更有效益。而且本发明在高侧区域内还在不同操作电压的元件之间设置有隔离结构，因此还能确保高压元件与低压元间之间不会发生短路。
为让本发明的上述特征和优点能更明显易懂，下文特举实施例，并配合所附图式作详细说明如下。
附图说明
图1是依照本发明的一实施例的一种半导体装置的上视示意图。
图2是图1的半导体装置内的高侧区域的A-A’线段的第一例的剖面示意图。
图3是图1的半导体装置内的高侧区域的A-A’线段的第二例的剖面示意图。
图4是图1的半导体装置内的高侧区域的A-A’线段的第三例的剖面示意图。
图5是依照本发明的另一实施例的一种半导体装置的电路图。
图6是依照本发明的又一实施例的一种半导体装置的电路图。
【符号说明】
100、500：半导体装置
102：低侧区域
104：高侧区域
106、108：半导体元件
110：隔离结构
200：基板
202：第一导电型埋层
204：第二导电型掺杂区
206：LV NMOS
208：LV PMOS
210、226：栅极
212、228：源极
214、230：漏极
216：场氧化物
218、232：P型井
220、234：N型井
222：HV NMOS
224：HV PMOS
300：浅沟渠隔离结构
400：第二导电型埋层
402：第二导电型隔离区
502：低侧区域的电路
504：高侧区域的电路
506、512：位准移位单元电路
508、514：逻辑控制器
510、518：UVLO
516：LDO
GND：地
HIN：逻辑输入高
HO：高侧区域输出
LIN：逻辑输入低
LO：低次区域输出
VB：高侧区域浮动工作电压
VCC：工作电压
VLV：外部电路电压
VS：高侧区域浮动地
具体实施方式
下文列举实施例并配合所附图式来进行详细地说明，但所提供之实施例并非用以限制本发明所涵盖的范围。此外，图式仅以说明为目的，并未依照原尺寸作图。为了方便理解，下述说明中相同的元件将以相同之符号标示来说明。
另外，关于文中所使用的“第一”、“第二”...等用语，并非表示顺序或顺位的意思，应知其仅仅是为了区别以相同技术用语描述的元件或操作而已。
其次，在本文中所使用的用词“包含”、“包括”、“具有”、“含有”等等，均为开放性的用语，即意指包含但不限于。
图1是依照本发明的一实施例的一种半导体装置的上视示意图。
请参照图1，本实施例的半导体装置100包括低侧(Low side)区域102与高侧(Highside)区域104，其中低侧区域102可包含目前技术已知的元件，因此并未绘示详细布局。至于高侧区域104包括多个半导体元件，例如具有不同操作电压的低压元件106与高压元件108，且高压元件108元件符合布局规则(Layout rule)，所以在尺寸上明显大于低压元件106。而且，在本实施例中，不同操作电压的低压元件106与高压元件108之间设置有隔离结构110。
由于高侧区域104中的部分高压元件被以低压元件106取代，因此与传统高侧区域104全部都是高压元件相比，藉由这些低压元件106的设计，便可大大减小高侧区域104的面积。而且，在不同操作电压的元件(106和108)之间设置隔离结构110，还能防止短路发生，进而允许半导体装置100的高侧区域104执行多种电压操作。
另外，在图1的高侧区域104中，以方格代表单一元件，但是本发明并不限于此；根据本发明所属的技术领域，可以根据需求在高侧区域104中设计各种型态的半导体元件。此外，根据本实施例，低压元件106之间可设置隔离结构110，但是本发明并不限于此；低压元件106之间若是操作电压相当，也可不设隔离结构110。
图2是图1的半导体装置内的高侧区域的A-A’线段的第一例的剖面示意图。
请参照图2，第一例的半导体元件包括低压元件106与高压元件108，低压元件106与高压元件108是形成于一基板200上。而且，在基板200与低压元件106与高压元件108之间有一第一导电型埋层(buried layer)202，以与低侧区域(如图1的102)做电压隔离，其中第一导电型埋层202例如N型埋层(NBL)。在第一例中，隔离结构为一第二导电型掺杂区204，其可完全包覆不同操作电压的元件中的低压元件106。举例来说，图2中的低压元件106例如是由低压N型金属氧化物半导体场效电晶体(LV NMOS)206和低压P型金属氧化物半导体场效电晶体(LV PMOS)208构成，LV NMOS 206和LV PMOS 208都包括栅极210、源极212和漏极214，且有场氧化物(FOX)216之类的结构隔开LV NMOS 206和LV PMOS 208。再者，LV NMOS206底下通常有P型井(P well)218、LV PMOS 208底下通常有N型井(N well)220。至于图2中的高压元件108例如是由高压NMOS(HV NMOS)222和高压PMOS(HV PMOS)224构成，HV NMOS222和HV PMOS 224也包括有栅极226、源极228和漏极230，且有场氧化物(FOX)216之类的结构隔开HV NMOS 222和HV PMOS 224。HV NMOS 222底下通常有P型井232、HV PMOS 224底下通常有N型井234。
因此，当图2的高压元件108所含的HV PMOS 224与低压元件106的LV NMOS 206相接时，可使用P型掺杂区作为包覆低压元件106的第二导电型掺杂区204。第二导电型掺杂区204的形成可直接采行低压元件制作工艺中的P base制作工艺。也就是说，在形成P型井218和N型井220之前先做一道植入步骤，以形成P型掺杂区204。
图3是图1的半导体装置内的高侧区域的A-A’线段的第二例的剖面示意图，其中使用与图2相同的元件符号来代表相同或相似的构件。
请参照图3，本发明的隔离结构除了图2的形式，还可以采用贯穿至第一导电型埋层202的浅沟渠隔离结构(Shallow trench isolation,STI)300，其可为绝缘材料，如氧化物。由于高压积体电路(HVIC)制作工艺会导致高压元件108底下的第一导电型埋层202也存在于低压元件106的P型井218和N型井220下方，因此藉由设置在低压元件106与高压元件108之间的STI 300，可有效隔离漏电路径。此外，STI 300也可作为低压元件106与高压元件108内部的隔离用结构。
图4是图1的半导体装置内的高侧区域的A-A’线段的第三例的剖面示意图，其中使用与图2相同的元件符号来代表相同或相似的构件。
请参照图4，除了图2～图3的形式，隔离结构也可以包括一第二导电型埋层400与一第二导电型隔离区402，第二导电型隔离区402位于不同操作电压的低压元件106与高压元件108之间，而第二导电型埋层400是位于第二导电型隔离区402底下的第一导电型埋层202之间。因此，当第一导电型埋层202为NBL，第二导电型埋层400则是P型埋层(PBL)，且第二导电型隔离区402为P型隔离区(PISO)。相反地，如果第一导电型埋层202为PBL，第二导电型埋层400和第二导电型隔离区402就是NBL和N型隔离区(NISO)。此外，为了避免掺杂浓度较高的第二导电型隔离区402影响崩溃电压(breakdown voltage,BV)，第二导电型隔离区402较佳为完全空乏的(fully-depleted)，才能得到最高的BV的电压。
一般来说，第二导电型隔离区402(如PISO)的宽度会影响BV的电压，若是宽度太宽则无法完全空乏，崩溃电压会降低，但宽度太小容易发生击穿(punch through)(isolationBV)，所以较佳是参考在高侧区域内各个区域电位差来订定第二导电型隔离区402的宽度W，譬如根据不同操作电压的元件的电位差而订定。
图5则是依照本发明的另一实施例的一种半导体装置500的电路图。图5显示有低侧区域的电路502以及高侧区域的电路504，并藉由位准移位单元(level shift)506将信号从低侧区域传递至高侧区域。低侧区域的电路502内有低电压锁定(UVLO)510电路，UVLO510电路可确保IC在VCC电压未达到安全操作电压前不会启动，而逻辑控制器508主要接收外界传递的逻辑输入信号HIN及LIN做逻辑运算后输出至低侧输出端LO及位准移位单元506。高侧区域的电路504有低电压锁定(UVLO)518电路，UVLO 518电路可确保高侧区域VB-VS电压未达到安全操作电压前逻辑控制器514不会启动，逻辑控制器514接收位准移位单元506的信号做逻辑运算，再经位准移位单元512将低压信号转换为高压信号后输出至HO，其中逻辑控制器514与UVLO 518是低压元件，而低压元件的电源来自LDO 516的输出，LDO 516可将高侧区域VB-VS的高电压转换成低压元件可安全操作的电压，因此，高侧区域504内部的低压元件可很正常的进行动作，不会受到VB-VS的高压而误动作。
除了图5所示的电路图，本发明的半导体装置还可运用其他电路来执行，譬如省略图5的LDO 516，如图6直接利用外部电路产生VLV的低电压，来提供逻辑控制器514与UVLO518较低的电压，其余电路设计可参照图5的说明，故不再赘述。
综上所述，本发明的半导体装置能在高侧区域内同时设置高压元件与低压元件，并藉由低压元件来达到缩减元件尺寸的效果，且使用低压元件设计一般逻辑运算，再以高压输出会更有效益。而且，本发明在高侧区域内设有隔离结构来隔开不同操作电压的元件，因此还能确保元件之间不会发生短路或漏电的问题。
虽然本发明已以实施例揭露如上，然其并非用以限定本发明，任何所属技术领域中具有通常知识者，在不脱离本发明的精神和范围内，当可作些许的更动与润饰，故本发明的保护范围当以本发明权利要求范围所界定者为准。

Claims (10)

1.一种半导体装置，其特征在于，所述的半导体装置包括：
一高侧区域及一低侧区域，其中所述高侧区域包括：
多个半导体元件，具有至少两个不同操作电压的元件；以及
至少一隔离结构，位于所述不同操作电压的元件之间；
所述的隔离结构包括一第二导电型掺杂区，完全包覆所述不同操作电压的元件中的低压元件。
2.如权利要求1所述的半导体装置，其特征在于，所述的不同操作电压的元件更包括高压元件。
3.如权利要求1所述的半导体装置，其特征在于，所述的高侧区域的所述半导体元件是形成于一基板上，且所述高侧区域更包括一第一导电型埋层，位于所述基板与所述半导体元件之间。
4.如权利要求3所述的半导体装置，其特征在于，所述的第一导电型埋层为N型埋层，所述第二导电型掺杂区为P型掺杂区。
5.如权利要求3所述的半导体装置，其特征在于，所述的隔离结构更包括贯穿所述第一导电型埋层的浅沟渠隔离结构。
6.如权利要求3所述的半导体装置，其特征在于，所述的隔离结构更包括：
一第二导电型隔离区，位于所述不同操作电压的元件之间；以及
一第二导电型埋层，位于所述第二导电型隔离区底下的所述第一导电型埋层之间。
7.如权利要求6所述的半导体装置，其特征在于，所述的第二导电型隔离区为完全空乏的。
8.如权利要求6所述的半导体装置，其特征在于，所述的第一导电型埋层为N型埋层，所述第二导电型隔离区为P型隔离区以及所述第二导电型埋层为P型埋层，反之亦然。
9.如权利要求6所述的半导体装置，其特征在于，所述的第二导电型隔离区的宽度根据所述不同操作电压的元件的电位差而订定。
10.如权利要求1所述的半导体装置，其特征在于，所述的低压元件包括低压N型金属氧化物半导体场效电晶体和低压P型金属氧化物半导体场效电晶体。
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Publication number Priority date Publication date Assignee Title
TWI608592B (zh) * 2017-01-25 2017-12-11 新唐科技股份有限公司 半導體裝置
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Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN202616220U (zh) * 2012-04-28 2012-12-19 东南大学 一种基于绝缘体上硅的高压隔离结构
CN103515324A (zh) * 2012-06-30 2014-01-15 万国半导体股份有限公司 集成高压器件的方法
US9728632B2 (en) * 2012-05-30 2017-08-08 Tower Semiconductor Ltd. Deep silicon via as a drain sinker in integrated vertical DMOS transistor

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5666280A (en) 1993-05-07 1997-09-09 Philips Electronics North America Corporation High voltage integrated circuit driver for half-bridge circuit employing a jet to emulate a bootstrap diode
US5973368A (en) * 1996-06-05 1999-10-26 Pearce; Lawrence G. Monolithic class D amplifier
US7834575B2 (en) * 2008-04-01 2010-11-16 International Rectifier Corporation Gate-driver IC with HV-isolation, especially hybrid electric vehicle motor drive concept
US20110156682A1 (en) 2009-12-30 2011-06-30 Dev Alok Girdhar Voltage converter with integrated schottky device and systems including same
US9012979B2 (en) * 2013-03-12 2015-04-21 Dongbu Hitek Co., Ltd. Semiconductor device having an isolation region separating a lateral double diffused metal oxide semiconductor (LDMOS) from a high voltage circuit region
JP6008054B2 (ja) * 2013-10-07 2016-10-19 富士電機株式会社 半導体装置
TWI527241B (zh) * 2014-06-11 2016-03-21 新唐科技股份有限公司 半導體裝置
US9460926B2 (en) * 2014-06-30 2016-10-04 Alpha And Omega Semiconductor Incorporated Forming JFET and LDMOS transistor in monolithic power integrated circuit using deep diffusion regions
KR102246570B1 (ko) * 2014-09-05 2021-04-29 온세미컨덕터코리아 주식회사 전력 반도체 장치
US9651635B2 (en) * 2014-11-05 2017-05-16 Infineon Technologies Ag Bias circuit for stacked hall devices
US9553142B2 (en) * 2015-06-12 2017-01-24 Macronix International Co., Ltd. Semiconductor device having buried layer
TWI608592B (zh) * 2017-01-25 2017-12-11 新唐科技股份有限公司 半導體裝置

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN202616220U (zh) * 2012-04-28 2012-12-19 东南大学 一种基于绝缘体上硅的高压隔离结构
US9728632B2 (en) * 2012-05-30 2017-08-08 Tower Semiconductor Ltd. Deep silicon via as a drain sinker in integrated vertical DMOS transistor
CN103515324A (zh) * 2012-06-30 2014-01-15 万国半导体股份有限公司 集成高压器件的方法

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