201240085 I v 罾 f 六、發明說明： 【發明所屬之技術領域】 本發明之實施例是有關於半導體元件及其製造方 法，且特別是有關於一種可改良電性之超高電壓N型金屬 氧化物半導體（UHV NMOS)元件及其製造方法。 【先前技術】 近年來幾乎在所有的電子裝置製造方面都有裝置規 模縮小的趨勢。當裝置實質上具有相同的容量，較小型的 電子裝置比起較大且笨重的電子裝置更受到歡迎。因此， 具有製造較小的元件的技術可明確地促使業者生產出較 小的裝置以設置這些較小元件。然而，許多現代電子裝置 需要執行驅動功能（例如是交換裝置）及資料處理兩者、或 是執行其他的判斷功能。使用低電壓互補金屬氧化物半導 體（complementary metal-oxide-semiconductor，CMOS) 技術是不能使裝置具有這些雙重功能的。因此，目前已經 發展出高電壓集成電路(high-voltage integrated circuits, HVIC)或功率集成電路(power_jntegrated cjrcujts p丨c)以 試圖將高電壓裝置結構與低電壓裝置結構整合在單一晶 =上。在高電壓集成電路(HVIC)所遇到的兩大主要挑戰 疋·（1)使超兩電壓元件（ultra-high voltage，UHV)具有一 高崩潰電壓；以及(2)使超高電壓元件和鄰近的CM〇s電 路可有效地隔離絕緣。 在相對高電壓進行開關轉換的一些應用裝置中，例如 包括平板顯示器、光源及安定器應用（例如是發光二極體之 4 201240085 I v v， 發光應用）、電源供應器（例如是行動裝置充電器）以及其他 許多產品。可運用在這些應用裝置中的高電壓金屬氧化半 導體裝置應具有高崩潰電壓，以避免從高電壓區域到低電 壓區域的擊穿。再者，半導體元件，例如適合超高電壓操 作之N型金屬氧化物半導體元件，一般都需要良好的操作 性能、且能以低成本和容易實施的製程進行製造。 【發明内容】 本揭露係有關於一種超高電壓N型金屬氧化物半導 體（UHV NMOS)元件及其製造方法。實施例之具有改良電 性之UHV NMOS元件不但適合在超高電壓下操作，且可 利用低成本和容易實施的製程進行元件之製作。 根據本揭露之第一方面，係提出一種超高電壓N型 金屬氧化物半導體元件，包括：一 P型材料之基板；一第 一高壓 N 型井(first high-voltage N-welh HVNW)區域， 設置在基板之一部分；一源極和基體Ρ型井（source and bulk p-well)，係設置於鄰近第一高壓N型井區域之一側， 且源極和基體P型井包括一源極（source)和一基體 (bulk); —閘極，自源極和基體P型井延伸至第一高壓N 型井區域之一部分，和一汲極（drain)設置於第一高壓N型 井之另一部分且與閘極相對應；一 P型場限層（P-Top layer)，係設置於第一高壓Ν型井區域内，Ρ型場限層位 於汲極與源極和基體P型井之間；以及一 N型摻雜層 (n-type implant layer)，係形成於P型場限層上方。 根據本揭露之第二方面，係提出一種超高電壓N型 201240085 金屬氧化物半導體元件之製造方法。首先，提供一基板， 該基板包括P型材料。形成一第一高壓N型井區域於基板 之一部分。之後，形成一源極和基體P型井於鄰近第一高 壓N型井區域之一側。接著，形成一 P型場限層於第一高 壓N型井區域内；以及形成一 N型摻雜層於P型場限層 之上方。 為了對本發明之上述及其他方面有更佳的瞭解，下文 特舉實施例，並配合所附圖式，作詳細說明如下： 【實施方式】 在此揭露内容之實施例中，係提出一種超高電壓N 型金屬氧化物半導體（Ultra-high voltage n-type-meta卜oxide-semiconductor，UHV NM0S)元件及 其製造方法。在UHVNMOS元件中係採用一 N型摻雜層 (n-type implant layer)以改善元件電性，如改善I/V特性 曲線。以下係提出多組實施例，配合相關圖式，以說明揭 露内容中一些，但不是全部，的超高電壓N型金屬氧化物 半導體元件之態樣。事實上，本發明的各種實施例可用許 多不同型態來表示，而不應被此揭露内容之實施例内容所 限制；但此揭露内容中所提出的這些實施例係可滿足應用 上的需求。再者，實施例中之敘述，如細部結構、製程步 驟和材料應用等等，僅為舉例說明之用，並非對本發明欲 保護之範圍做限縮。再者，此揭露内容中所提出的多個實 施例中，相同元件係使用同樣的元件標號。 201240085 <第一實施例之UHV NMOS元件> 第1圖係為依照本揭露第一實施例之一超高電壓N 型金屬氧化物半導體（UHV NM〇S)元件之示意圖。在第一 實施例中，UHV NM0S元件包括一基板1〇 ,例如是P型 材料之基板。如第1圖所示，基板1〇包括一 N型金屬氧 化物半導體（NM0S)區域和一高壓侧操作區域(high-side operation region ’ HSOR) 〇 UHV NMOS 元件更包括位於 NM〇S 區域之一第一 N 型埋層（first N-doped buried layer ’ NBL)12 ’和位於高壓側操作區域hs〇R之一第二 N型埋層（second NBL)13，以提供隔離功能。在此實施例 中，一 P型磊晶層15可沈積於基板上。UHV NM0S 元件更包括一第一而壓N型井（first high-voltage N-well，HVNW)區域16和一第二高壓n型井區域18,分 別位於基板10之一部份和高壓侧操作區域HS〇R處。第 一、第二高壓N型井區域16和18係可提高臨界電場 (critical electrical field) ’以避免元件在高壓操作電壓下 (如大於650伏特之操作電壓）崩潰。 再者，P型磊晶層15可能包括多個p型井（pws)和 N型井（NWs)。如第1圖所示，一 P型井20、鄰近第一高 壓N型井區域16之一侧的一源極和基體p型井（s〇urce and bulk PW)22 ’係和N型井27和29形成於p型磊晶 層15處。再者，位於p型井空間（pws)内以進行高壓内 連接（high-voltage interconnection)之 P 型井，可分裂成 多個獨立的P型井，例如P型井241和242，以提供自 我遮蔽與隔離。在此實施例中’P型井區域中可更包括具 201240085 更问P型或N型材料摻雜濃度之區域，如圖式中標示p+ 和N+之區域。源極和基體P型井22中的P+區域可做為 兀件之一基體53 ’而源極和基體P型井22中的N+區域 可做為元件之—源極54。另外，位於第-高壓N型井區 域16中的一 N+區域可做為元件之一汲極邡。 再者 P型場限層（P-Top layer)32係設置於第— 南壓井區域16内’並位於沒極56和源極和基體p 型井22之間。元件在高壓操作電壓下崩潰之前，p型場 限層32的存在可降低表面電場（reduce surface fje|d)。在 此貫施例中，一 N型摻雜層（n_type jmp丨ant丨aye「)34係形 成於P型場限層32之上方。n型摻雜層34的存在可改善 元件電性，如改善UHV NMOS元件之|/v特性曲線。請參 照第2A、2B圖，係分別顯示具有N型摻雜層和不具N型 換雜層之UHV NMOS元件的|/v特性曲線圖。不具n型 摻雜層之UHV NM0S元件（第2B圖）呈現不正常的丨/v特 性曲線，而具N型摻雜層之UHVNM0S元件（第2A圖）則 呈現正常的丨/V特性曲線。 在此實施例中，多個場氧化物(field〇xide，F〇x)係 設置於P型磊晶層15處和/或任何或所有上p型井、N型 井和第-高壓N型井區域16處。如第，圖所示，第一場 氧化物41係鄰近P型井20之一部份處；第二場氧化物 4 3係鄰近N型井2 7處；第三場氧化物4 5係位於第一高 壓N型井區域16内並在N型摻雜層34上，且第三場氧 化物45係位於源極和基體P型井22與做為汲極之 N+區域之間。第四場氧化物47,係鄰近高壓内連接 201240085201240085 I v 罾f VI. Description of the Invention: [Technical Field] The present invention relates to a semiconductor device and a method of fabricating the same, and more particularly to an ultrahigh voltage N-type metal oxide capable of improving electrical properties Semiconductor (UHV NMOS) device and method of manufacturing the same. [Prior Art] In recent years, there has been a tendency for the scale of the apparatus to shrink in almost all electronic device manufacturing. While devices have substantially the same capacity, smaller electronic devices are more popular than larger and bulky electronic devices. Thus, techniques with smaller components can clearly motivate the industry to produce smaller devices to accommodate these smaller components. However, many modern electronic devices need to perform both drive functions (e.g., switching devices) and data processing, or perform other judgment functions. The use of low voltage complementary metal-oxide-semiconductor (CMOS) technology does not allow the device to have these dual functions. Therefore, high-voltage integrated circuits (HVICs) or power integrated circuits (power_jntegrated cjrcujts p丨c) have been developed in an attempt to integrate a high-voltage device structure and a low-voltage device structure on a single crystal. Two major challenges encountered in high voltage integrated circuits (HVICs): (1) making ultra-high voltage (UHV) have a high breakdown voltage; and (2) making ultra-high voltage components and Adjacent CM〇s circuits effectively isolate the insulation. Some application devices that perform switching at relatively high voltages include, for example, flat panel displays, light sources, and ballast applications (eg, LED 4 201240085 I vv, lighting applications), power supplies (eg, mobile device chargers) ) and many other products. High voltage metal oxide semiconductor devices that can be used in these applications should have high breakdown voltages to avoid breakdown from high voltage regions to low voltage regions. Further, a semiconductor element, for example, an N-type metal oxide semiconductor device suitable for ultra-high voltage operation generally requires good operational performance and can be manufactured at a low cost and an easily implemented process. SUMMARY OF THE INVENTION The present disclosure is directed to an ultra high voltage N-type metal oxide semiconductor (UHV NMOS) device and a method of fabricating the same. The UHV NMOS device with improved electrical conductivity of the embodiment is not only suitable for operation at an ultra-high voltage, but also can be fabricated using a low-cost and easy-to-implement process. According to a first aspect of the present disclosure, an ultra high voltage N-type metal oxide semiconductor device is provided, comprising: a substrate of a P-type material; a first high-voltage N-welh HVNW region, Provided in a portion of the substrate; a source and bulk p-well disposed on one side adjacent to the first high-pressure N-well region, and the source and base P-wells include a source (source) and a bulk; - a gate extending from the source and base P-type wells to one of the first high-pressure N-type well regions, and a drain disposed in the first high-pressure N-type well The other part corresponds to the gate; a P-type layer is placed in the first high-pressure Ν-type well, and the 场-type field is located in the bungee and source and the base P-type well. And an n-type implant layer formed over the P-type field limiting layer. According to a second aspect of the present disclosure, a method of manufacturing an ultra-high voltage N-type 201240085 metal oxide semiconductor device is proposed. First, a substrate is provided that includes a P-type material. A first high pressure N-well region is formed on a portion of the substrate. Thereafter, a source and a base P-type well are formed adjacent one side of the first high pressure N-type well region. Next, a P-type field limiting layer is formed in the first high-pressure N-type well region; and an N-type doped layer is formed over the P-type field limiting layer. In order to better understand the above and other aspects of the present invention, the following detailed description of the embodiments and the accompanying drawings will be described in detail as follows: [Embodiment] In the embodiment of the disclosure, a super high is proposed. An ultra-high voltage n-type-meta oxide-semiconductor (UHV NMOS) device and a method of manufacturing the same. An N-type implant layer is used in the UHV NMOS device to improve the device's electrical properties, such as improving the I/V characteristic curve. In the following, a plurality of sets of embodiments are proposed in conjunction with the related drawings to illustrate some, but not all, aspects of the ultrahigh voltage N-type metal oxide semiconductor device disclosed. In fact, the various embodiments of the present invention can be represented in many different forms and should not be limited by the embodiments of the disclosure; however, the embodiments presented in this disclosure are intended to meet the needs of the application. Furthermore, the description of the embodiments, such as the detailed structure, the process steps, and the application of the materials, are for illustrative purposes only and are not intended to limit the scope of the invention. Furthermore, in the various embodiments set forth in this disclosure, the same elements are labeled with the same elements. 201240085 <UHV NMOS device of the first embodiment> Fig. 1 is a schematic view showing an ultrahigh voltage N-type metal oxide semiconductor (UHV NM〇S) element according to the first embodiment of the present disclosure. In the first embodiment, the UHV NMOS device includes a substrate 1 〇 such as a substrate of a P-type material. As shown in FIG. 1, the substrate 1A includes an N-type metal oxide semiconductor (NMOS) region and a high-side operation region 'HSOR'. The UHV NMOS device further includes one of the NM〇S regions. A first N-doped buried layer 'NBL' 12' and a second N-type buried layer (second NBL) 13 on the high side operating region hs〇R provide isolation. In this embodiment, a P-type epitaxial layer 15 can be deposited on the substrate. The UHV NM0S component further includes a first high-voltage N-well (HVNW) region 16 and a second high-voltage n-well region 18 located at one of the substrate 10 and the high-voltage operating region, respectively. HS〇R. The first and second high pressure N-well regions 16 and 18 can increase the critical electrical field' to avoid component collapse at high voltage operating voltages (e.g., operating voltages greater than 650 volts). Furthermore, the P-type epitaxial layer 15 may include a plurality of p-type wells (pws) and N-type wells (NWs). As shown in FIG. 1, a P-type well 20, a source and a base p-type well (s〇urce and bulk PW) 22' and an N-type well 27 adjacent to one side of the first high-pressure N-type well region 16 And 29 are formed at the p-type epitaxial layer 15. Furthermore, P-type wells located in p-type well spaces (pws) for high-voltage interconnection can be split into multiple independent P-type wells, such as P-type wells 241 and 242, to provide self Shading and isolation. In this embodiment, the region of the 'P-type well region may further include a region where the doping concentration of the P-type or N-type material is more than 201240085, as shown in the figure, where p+ and N+ are indicated. The P+ region in the source and base P-well 22 can be used as one of the components 53' and the N+ region in the source and base P-well 22 can be used as the source-source 54. Alternatively, an N+ region located in the first high pressure N-well region 16 can be used as one of the components. Further, a P-Top layer 32 is disposed in the first-near well region 16 and is located between the gate 56 and the source and the base p-well 22. The presence of the p-type field layer 32 reduces the surface electric field (reduce surface fje|d) before the component collapses under high voltage operating voltage. In this embodiment, an N-type doped layer (n_type jmp丨ant丨aye ") 34 is formed over the P-type field limiting layer 32. The presence of the n-type doped layer 34 improves the electrical properties of the device, such as Improve the |/v characteristic curve of UHV NMOS device. Refer to Figures 2A and 2B for the |/v characteristic curve of UHV NMOS device with N-type doped layer and N-type miscellaneous layer, respectively. The UHV NM0S element of the doped layer (Fig. 2B) exhibits an abnormal 丨/v characteristic curve, while the UHVNM0S element with an N-type doped layer (Fig. 2A) exhibits a normal 丨/V characteristic curve. In the example, a plurality of field oxides (fields xide, F〇x) are disposed at the P-type epitaxial layer 15 and/or any or all of the upper p-type wells, the N-type wells, and the first high-pressure N-type well regions 16 As shown in the figure, the first field oxide 41 is adjacent to one part of the P-type well 20; the second field oxide 4 3 is adjacent to the N-type well 27; the third field oxide 4 5 It is located in the first high-voltage N-type well region 16 and on the N-type doped layer 34, and the third field oxide 45 is located between the source and the base P-type well 22 and the N+ region as the drain. Four field oxides 4 7, the system is adjacent to the high pressure connection 201240085
I vv /HOOrAAI vv /HOOrAA
(high-voltage interconnection，HVI)之 P 型井空間 PWS 的P型井241和242處；第五場氧化物49係鄰近高壓 側操作區域（high-side operation region，HSOR)之第二高 壓N型井區域18。 再者，一閘極52可形成於源極54和第三場氧化物 45之間。源極56則設置於第一高壓N型井16之另一部 分且與閘極52相對應。閘極52係自源極和基體P型井 22之源極54延伸至第一高壓N型井區域16之一部分， 例如延伸至第三場氧化物45之一部分。第1圖中，自基 體53邊緣到汲極56邊緣之間的範圍可定義為一 UHV NMOS。而高壓内連接（HVI)區域可提供UHV NMOS與同 一基板上其他元件之間的内連接，例如與基板上的高壓集 成電路（High voltage integrated circuit，HVIC)或功率集 成電路（Power Integrated Circuit，PIC)之元件之間的隔 離。(high-voltage interconnection, HVI) P-type wells 241 and 242 of the P-type well space PWS; the fifth field oxide 49 is adjacent to the second high-pressure N-type of the high-side operation region (HSOR) Well area 18. Further, a gate 52 can be formed between the source 54 and the third field oxide 45. The source 56 is disposed in another portion of the first high voltage N-type well 16 and corresponds to the gate 52. The gate 52 extends from the source 54 of the source and base P-well 22 to a portion of the first high voltage N-well region 16, for example to a portion of the third field oxide 45. In Fig. 1, the range from the edge of the substrate 53 to the edge of the drain 56 can be defined as a UHV NMOS. The high voltage interconnect (HVI) region provides an internal connection between the UHV NMOS and other components on the same substrate, such as a high voltage integrated circuit (HVIC) or a power integrated circuit (PIC) on the substrate. The isolation between the components.
在此實施例中，一絕緣層，例如一内絕緣介電層 (inter-layer dielectric，ILD)61 ’ 係形成於基板 1〇 且沈積 於可能暴露出的場氧化物（41, 43, 45, 47 and 49)、P型井 (20, 22, 241, 242 and 26)、N 型井（27 and 29)和部分 P 型蟲晶層15之上方。而一金屬層，例如一第一圖案化金 屬層（first patterned metal layer)64，則形成於内絕緣介電 層61上’用以連接UHV NMOS與其他各元件。内絕緣介 電層61中亦具有多個接觸孔(contacts) 63，以提供第一 圖案化金屬層64和P+/N +區域之間的電性連接。在某些 應用例中，金屬層可能跨越高壓内連接（HVI)區域，以提供 201240085 •零《 · 1W· f « UHV元件和鄰近元件之間達到内連接之目的。如第彳圖所 示，第一圖案化金屬層64之一部分係對應地跨越p型井 空間（PVVS)，以進行高壓内連接。在一些實施例中，另一 絕緣層’例如一内金屬介電層（丨nter_ metal dielectric， IMD)68 ’係形成於第一圖案化金屬層64上，而一第二圖 案化金屬層（second patterned metal layer)74 則形成於 内金屬介電層68上。内金屬介電層68中亦具有多個通孔 (vias) 69，以提供第一圖案化金屬層64和第二圖案化金 屬層74之間的電性連接。在某些應用例中，第二圖案化 金屬層74之一部分亦可對應地跨越p型井空間（PWS)， 以進行向壓内連接，如第1圖所示。 <第一實施例之UHV NM0S元件之製造方法> 第3A〜3E圖係繪示依照本揭露第一實施例之一超 高電壓N型金屬氧化物半導體（UHV NM0S)元件之製造方 法示意圖。 如第3A圖所示，首先提供一基板10(例如是一 P型 基板），且一第一 N型埋層（first NBL)12和一第二N型埋 層（second NBL)13，如透過微影製程（photolithography) 和佈植製程（implantation)，係形成於基板1〇上。在某些 應用例中，第一 N型埋層12和第二N型埋層13的形成 需藉由驅入(drive in)製程而完成。 如第3B圖所示，一 P型磊晶層15可沈積於基板 10上，例如是磊晶成長於基板10上。藉由微影製程和佈 植製程，一第一高壓N型井(first HVNW)區域16和一第 201240085 【νν,**»ΟΓ/Λ 二尚f Ν型井區域18，係分別形成於基板10之部份處。 第1塵Ν型井16係形成於基板1〇之一部份並和第— Ν型埋層12相距一距離。第二高壓Ν型井18係形 板1〇之-部份並鄰近第二Ν型埋層13。在利用微影製土 程和佈植製㈣在Ρ縣晶層彳5上提供多個ρ型井之 後，可使用驅入(drive in)製程以完成ρ型井、第一高壓ν 型井16和第二高壓Ν型井18之形成。至於ν型井27和 29 ’亦可透過微影製程和佈植製程之後再搭配驅入製程， 以於Ρ型蟲晶層15上完成ν型井27和29。 如第3Β圖戶斤示’ ρ型蟲晶層π處的多個ρ型井， 例如是包括- Ρ型井20、鄰近第一高塵问型井區域^之 一侧的一源極和基體Ρ型井（s〇urceandbuM<pw)22，位 於P型井空間（PWS)内且位於第一、二高壓_井區域 16和18之間的兩個獨立的p型井241和242。卩型井 241和242可在元件的高屢内連接(HV|)區域提供自我遮 蔽與隔離。 乂之後，如第3C圖所示，一 ρ型場限層（p_T〇p |aye「)32 係設置於第-高壓N型井區域16内，而—_推雜層 (n-type imp|ant |aye「)34係形成於ρ型場限層％之上 方N型摻雜層34可透過微影製程之後再以離子佈植或 推雜製程而形成。在第一實施例中’ N型摻雜層34之離 子佈植/摻雜濃度約在_1e11_____1/Cm2 〜_9e14__1/cm2 之範圍内，且形成的深度約二__3==^m。ρ 型場限層32的存在可降低表面電場以維持在崩潰前之電 子平衡。而Ν型摻雜層34的存在則可改善元件電性，如 201240085 改善UHV NMOS元件之丨/V特性曲線。在此實施例中，p 型場限層32和N型摻雜層34可使用同一光罩形成，可降 低成本和節省時間。在一實施例中，N型摻雜層34和下 方之P型場限層32實質上可具有相同尺寸。 之後，如第3D圖所示，多個場氧化物（F〇x，如41〜49) 係可利用微影製程，成長於對應之所屬區域。在此實施例 中，第一場氧化物41係鄰近P型井2〇之一部份處；第二 場氧化物43係鄰近N型井27處；第三場氧化物45係位 於第一高壓N型井區域16内並在n型摻雜層34上；第 四場氧化物47，係鄰近高壓内連接（high_v()|tage interconnection，HW)之P型井空間Pws的p型井241和 242處；第五場氧化物49係鄰近高壓側操作區 ==型井區域18。之後’-多晶石夕層係沈積於 暴露之部为上方，並將從源極和基體p型井a延伸 二場氧化物45的多晶矽以外的部分去 52;去除方法例如是利用微影製程。接:閘極 影製程和佈植製程，將不同濃度的 °疋藉由微 入Ρ型井20和26、源極和基體ρ型 守 型井區域…第二高㈣型井區：18井二？-_ 區域。例如，源極和基體Ρ型井22可31井29的各 域和- Ν型摻雜區域，以分別定義出—A 型摻雜區 M。而位於第三場氧化物45和第和—源極 形成於第-高㈣型井區域16的暴^ ^之間’且 區域，係可定義為一汲極56 ° :之- N型摻雜 ㈣和第三場氧化物形成於源 目/原極和基體P型井 201240085 ι**ι -r%/wi / * 22之源極54處延伸至第一高壓n型井區域16之一部分 處，如延伸至第三場氧化物45之一部分。元件中，自基 體53邊緣到汲極56邊緣之範圍可定義為一（JHV NMOS。 接著，如第3 E圖所示，沈積一絕緣層例如一内絕緣 介電層（inter-layer dielectric，ILD)61 於場氧化物（41，43, 45, 47 and 49)、P 型井（20, 22, 241, 242 and 26)、N 型 井（27 and 29)和暴露出的部分p型磊晶層15之上方。其 中’内絕緣介電層61更包括多個接觸孔（contacts) 63， 以對應基體53、源極54、沒極56和其他元件。之後，形 成一金屬層且利用如微影製程以移除部分金屬層，進而形 成一第一圖案化金屬層64，以做為元件應用所需之内連 線。 之後，將一内金屬介電層（inter- metal dielectric， IM D)68形成於第一圖案化金屬層64上，其中内金屬介電 層68包括多個通孔(vias) 69於適當位置。而另一金屬層 則形成於内金屬介電層68上，且利用如微影製程以移除 此金屬層之部分’進而形成一第二圖案化金屬層（second patterned metal layer)74，以做為元件應用所需之内連 線。在第一實施例中’第一圖案化金屬層64和第二圖案 化金屬層74之一部分皆對應地跨越p型井空間（pws)， 以進行高壓内連接，如第3E圖所示。 <元件佈局>In this embodiment, an insulating layer, such as an inter-layer dielectric (ILD) 61', is formed on the substrate 1 and deposited on the field oxide that may be exposed (41, 43, 45, 47 and 49), P-type wells (20, 22, 241, 242 and 26), N-type wells (27 and 29) and part of P-type insect layer 15 above. A metal layer, such as a first patterned metal layer 64, is formed on the inner insulating dielectric layer 61 for connecting the UHV NMOS to other components. The inner insulating dielectric layer 61 also has a plurality of contact contacts 63 to provide an electrical connection between the first patterned metal layer 64 and the P+/N+ regions. In some applications, the metal layer may span the high voltage interconnect (HVI) region to provide 201240085 • Zero “ · 1W· f « UHV components and adjacent components for internal connections. As shown in the figure, one portion of the first patterned metal layer 64 correspondingly spans the p-well space (PVVS) for high voltage internal connections. In some embodiments, another insulating layer 'eg, an inner metal dielectric layer (IMD) 68' is formed on the first patterned metal layer 64 and a second patterned metal layer (second) A patterned metal layer 74 is formed on the inner metal dielectric layer 68. The inner metal dielectric layer 68 also has a plurality of vias 69 to provide an electrical connection between the first patterned metal layer 64 and the second patterned metal layer 74. In some applications, a portion of the second patterned metal layer 74 may also correspondingly span the p-well space (PWS) for in-pressure connection, as shown in FIG. <Manufacturing Method of UHV NMOS Element of First Embodiment> FIGS. 3A to 3E are schematic views showing a manufacturing method of an ultrahigh voltage N-type metal oxide semiconductor (UHV NMOS) device according to the first embodiment of the present disclosure. . As shown in FIG. 3A, a substrate 10 (for example, a P-type substrate) is first provided, and a first N-type buried layer (first NBL) 12 and a second N-type buried layer (second NBL) 13 are transparent. A photolithography and an implantation process are formed on the substrate 1 . In some applications, the formation of the first N-type buried layer 12 and the second N-type buried layer 13 is accomplished by a drive in process. As shown in Fig. 3B, a P-type epitaxial layer 15 may be deposited on the substrate 10, for example, epitaxially grown on the substrate 10. By the lithography process and the implantation process, a first high-voltage N-type well (first HVNW) region 16 and a 201240085 [νν, **»ΟΓ/Λ 二尚f Ν-type well region 18 are formed on the substrate, respectively. Part of 10. The first dust mite well 16 is formed on a portion of the substrate 1 and is spaced apart from the first germanium buried layer 12. The second high pressure crucible well 18 is partially connected to the second crucible layer 13. After using the lithography soil and the planting system (4) to provide a plurality of p-type wells on the Jingxian 彳5, a drive in process can be used to complete the p-type well and the first high-pressure ν-type well 16 And the formation of the second high pressure weir type well 18. For the ν-type wells 27 and 29', the ν-type wells 27 and 29 can be completed on the enamel-type layer 15 by the lithography process and the implantation process followed by the priming process. For example, in Figure 3, a plurality of p-type wells at the π-type crystallization layer π, for example, include a Ρ-type well 20, a source and a substrate adjacent to one side of the first high-difference well type ^ A crucible well (s〇urceandbuM<pw) 22, two separate p-wells 241 and 242 located between the first and second high pressure well regions 16 and 18 in the P-well space (PWS). The 卩-type wells 241 and 242 provide self-masking and isolation in the high-internal (HV|) region of the component. After that, as shown in Fig. 3C, a p-type field limiting layer (p_T〇p | aye ") 32 is disposed in the first high-pressure N-well region 16, and the -_ push-pad layer (n-type imp| An ant |aye ") 34 is formed above the p-type field layer %. The N-type doped layer 34 can be formed by an ion implantation process or a snagging process after the lithography process. In the first embodiment, the 'N type The ion implantation/doping concentration of the doped layer 34 is in the range of about _1e11_____1/Cm2 to _9e14__1/cm2, and the depth formed is about two__3==^m. The presence of the p-type field limiting layer 32 can reduce the surface. The electric field maintains the electron balance before collapse. The presence of the doped layer 34 improves the device's electrical properties, as in 201240085 improves the 丨/V characteristic of UHV NMOS devices. In this embodiment, the p-type field layer The 32 and N-type doped layers 34 can be formed using the same mask, which can reduce cost and save time. In an embodiment, the N-type doped layer 34 and the underlying P-type field limiting layer 32 can be substantially the same size. Thereafter, as shown in FIG. 3D, a plurality of field oxides (F〇x, such as 41 to 49) can be grown in the corresponding region by using a lithography process. The first field oxide 41 is adjacent to one of the P-type wells; the second field oxide 43 is adjacent to the N-type well 27; and the third field oxide 45 is located in the first high-pressure N-type well region. 16 is on the n-type doped layer 34; the fourth field oxide 47 is adjacent to the p-type wells 241 and 242 of the P-type well space Pws of the high-voltage internal connection (high_v()|tage interconnection, HW); The five-field oxide 49 series is adjacent to the high-pressure side operating area == type well area 18. After that, the '-polycrystalline layer is deposited on the exposed part and will be extended from the source and the base p-type well a two-row oxidation. The portion other than the polysilicon of the object 45 is removed to 52; the removal method is, for example, a lithography process. The gate electrode process and the implantation process are performed, and different concentrations of 疋 are obtained by micro-injection wells 20 and 26, source and Base ρ-type well-being area...second high (four)-type well area: 18-well two?-- area. For example, the source and base Ρ-type well 22 can be 31 wells 29 and the Ν-type doped area The -type A doping region M is defined separately, and the third field oxide 45 and the first and the source are formed between the turbulences of the first-high (four)-type well region 16 and the region The system can be defined as a drain of 56 °: - N-type doping (four) and a third field oxide formed in the source / original and base P-type well 201240085 ι**ι -r% / wi / * 22 source The pole 54 extends to a portion of the first high voltage n-well region 16, such as to extend to a portion of the third field oxide 45. In the component, the range from the edge of the substrate 53 to the edge of the drain 56 can be defined as one (JHV NMOS). . Next, as shown in FIG. 3E, an insulating layer such as an inter-layer dielectric (ILD) 61 is deposited on the field oxides (41, 43, 45, 47 and 49) and the P-type well ( 20, 22, 241, 242 and 26), N-wells (27 and 29) and exposed portions of the p-type epitaxial layer 15 above. The inner insulating dielectric layer 61 further includes a plurality of contact contacts 63 to correspond to the base 53, the source 54, the pole 56 and other components. Thereafter, a metal layer is formed and a portion of the metal layer is removed by, for example, a lithography process to form a first patterned metal layer 64 for use as an interconnect for component applications. Thereafter, an inter-metal dielectric (IMD) 68 is formed over the first patterned metal layer 64, wherein the inner metal dielectric layer 68 includes a plurality of vias 69 in place. Another metal layer is formed on the inner metal dielectric layer 68, and a portion such as a lithography process is used to remove a portion of the metal layer to form a second patterned metal layer 74. Apply the required interconnects for the component. In the first embodiment, a portion of the first patterned metal layer 64 and the second patterned metal layer 74 respectively span the p-type well space (pws) for high voltage internal connection as shown in Fig. 3E. <Component layout>
第4A圖係為具有本揭露實施例之一超高電壓n型金 屬氧化物半導體（UHV NM0S)之一元件的上視圖。第4B 13 201240085 圖係為第4A圖元件之局部放大圖。如第4A圖所示之元 件’其具有兩個UHV NMOSs ’但可能分別施以不同的操 作電壓。其他組件（未顯示於圖面）如LVM〇s、雙載子接面 電晶體（BJT)、電容、電阻等組件，可設置於高壓操作區 域（如大於650V操作之區域）。實施例中，金屬（如第一圖 案化金屬層64或第二圖案化金屬層74)的位置和形狀，包 括基體53、源極54、汲極56，係顯示於第4B圖。再者， 利用同一光罩所形成的P型場限層32和N型摻雜層34 亦顯示於第4B圖。再者，相互分開的p型井241和242 以在高壓内連接_)區域提供自我遮蔽與隔離，亦顯示於 第4B圖。其中，汲極56的金屬部分(b)可為—τ字形' 且金屬部分（a)和（b)可施加不同電壓。再者，汲極: 伸部分（見第4B圖）係可做為高壓内連接之金屬部分， 設置在第4A圖元件中的其他組件（未顯示，如LVm〇s 雙載子接面電晶體（BJT)'電容、電阻等）完成電性連接。 <第二實施例之UHV NMOS元件> 第5圖係為依照本揭露第二實施例之一超内電壓n 型金屬氧化物半導體（UHVNMOS)元件之示意圖。第二實 施例之元件中可包括一層而非兩層金屬層。請同時參^第 1圖和第5圖。第1圖和第5圖之元件結構相同，除了第 1圖之元件的兩層金屬層減少至第5圖之一層金屬芦（即第 一圖案化金屬層64)。 <第三實施例之UHV NMOS元件 201240085 » vv 第6圖係為依照本揭露第三實施例之一超高電壓N 型金屬氧化物半導體（UHVNMOS)元件之示意圖。第三實 施例中，元件的N型埋層（NBL)可依不同應用情況所需而 移除。請同時參照第1圖和第6圖。第6圖和第1圖之元 件結構相同，除了第1圖中位於源極端的第一 N槊埋層 12在第6圖之元件結構中被移除而沒有顯示。 <第四實施例之UHV NMOS元件> 第7圖係為依照本揭露第四實施例之一超高電壓N 型金屬氧化物半導體（UHV NMOS)元件之示意圖。請同時 參照第1圖和第7圖。第7圖和第1圖之元件結構相同’ 除了第1圖中位於高壓操作區域（HSOR)的第二N型埋層 13在第7圖之元件結構中被移除而沒有顯示（當高壓操作 區域有適當地絕緣時第二N型埋層13可被移除）。 <第五實施例之UHV NMOS元件> 第8圖係為依照本揭露第五實施例之一超高電壓N 型金屬氧化物半導體（UHV NMOS)元件之示意圖。在第一 實施例中，p型井空間（PWS)中係具有兩個獨立的p型井 241和242 ’但本揭露並不限於此。在第五實施例中，高 壓内連線的P型井空間可包括N個P型井，N可以是正 整數。如第8圖所示，P型井空間中具有三個獨立且間隔 開來的P型井241、242和243’以提供自我遮蔽和隔離。 <第六實施例之UHV NMOS元件> 15 201240085 …奶客雷壓N 第9圖係為依照本揭露第六實施例之一趙 ^ 型金屬氧化物半導體（UHV NM0S)元件之示意圖。在第^ 實施例中，高壓内連線的p型井空間中其p裂井亦巧依& λ 镇9圖和 用所需而被移除。請同時參照第1圖和第9圖。 第1圖之元件、结構相同，除了第1 ®中在尚壓内連線典， 的P型井241和242在第9圖之元件結構中被移除而^ 有顯示在第9圖（當高壓内連接（HVI)區域有適當地自我遮 蔽時P型井241和242可被移除）。 <第七實施例之UΗV NMOS元件> 第10圖係為依照本揭露第七實施例之一超高電壓Ν 型金屬氧化物半導體（UHVNMOS)元件之示意圖。在第七 實施例中，一或多個N型埋層（NBL)可增設於元件中’以 改善隔離效果。請同時參照第1圖和第1〇圖。第10圖之 元件結構更包括了一第三N型埋層14，形成於汲極56和 P型井空間中的P型井241、242之間。 <第八實施例之UHV NMOS元件> 第11圖係為依照本揭露第八實施例之一超高電壓N 型金屬氧化物半導體（UHV NMOS)元件之示意圖。在第一 實施例中，P型場限層（P_Top layer)32和N型摻雜層 (n-type implant layer)34係設置於第一高壓N型井區域 16内’且係建構為一完整塊體，但本揭露並不限於此。在 第八實施例中，P型場限層32和N型摻雜層34亦可建 構成為多個獨立塊體，如第11圖所示。 201240085 〈第九實施例之UHV NM〇s元件> 第12圖係為依照本揭露第九實施例之一超高電壓N 型金屬氧化物半導體（UHV NMOS)元件之示意圖。在第一 實施例中，元件係包括第一場氧化物41、第二場氧化物 43、第三場氧化物45、第四場氧化物47和第五場氧化物’ 但本揭露並不限於此。請同時參照第1圖和第12圖。第1 圖中之第三場氧化物45,其形成於第一高壓N型井區域 16内並位於N型摻雜層34之上，亦可在第九實施例中自 第12圖之元件結構中移除，以提供其他應用態樣之實施 方式。 <第十實施例之UHV NMOS元件> 第13圖係為依照本揭露第十實施例之一超高電壓N 型金屬氧化物半導體（UHV NMOS)元件之示意圖。在半導 體製程中，熱生成氧化物主要用來做為隔離材料。有兩種 主要的製程可用來隔離相鄰的MOS電晶體，即區域氧化 隔離（Local Oxidation of Silicon，LOCOS)製程和淺溝槽 隔離（ShallowTrench Isolation，STI)製程。在第一實施例 中，如第1圖所示之元件係以LOCOS製程製造，且所生 長用來隔離之用的厚氧化石夕稱為場氧化物（41, 43, 45，47 和49)。由於整個LOCOS結構都是熱生成，LOCOS製程 的優點是製法簡單、可生成具有高品質氧化物。然而其缺 點是會產生"鳥嘴，，效應（“bird’s beak" effect)。為避免產生 “鳥嘴”狀之特徵，第十實施例之元件係以STI製程製造。 在沒有任何氧化物侵佔空間的情形下，STI製程可用來形 成更小範圍的隔離區域，而可更適合用來製造具高密度需 求之元件。因此，第1圖中的厚的第一、第二、第三、第 四和第五場氧化物41, 43, 45, 47和49係在第十實施例中 被第一、第二、第三、第四和第五隔離氧化物（isolated oxide)81, 83, 85, 87和89所取代，如第13圖所示。 〈第十一實施例之UHV NMOS元件> 第14圖係為依照本揭露第十一實施例之一超高電壓 N型金屬氧化物半導體（UHV NMOS)元件之示意圖。在第 十實施例中，元件具有第一隔離氧化物81、第二隔離氧化 物83、第三隔離氧化物85、第四隔離氧化物87和第五隔 離氧化物89。但本揭露並不限於此。請同時參照第13圖 和第14圖。第13圖中的第三隔離氧化物85，其形成於 第一高壓N型井區域16内並位於N型摻雜層34(即漂浮 區域）之上，亦可在第十一實施例中自第14圖之元件結構 中移除，以提供其他應用態樣之實施方式。 <第十二實施例之UHV NMOS元件> 第15圖係為依照本揭露第十二實施例之一超高電壓 N型金屬氧化物半導體（UHV NMOS)元件之示意圖。在第 十實施例中，元件具有第一隔離氧化物81、第二隔離氧化 物83、第三隔離氧化物85、第四隔離氧化物87和第五隔 離氧化物89,其中位於P型井空間（PWS)的第四隔離氧化 物87係為一完整體。但本揭露並不限於此。請同時參照 201240085 1 v v I ~rw\>/i t~\ 第13圖和第15圖。在第十二實施例中，P型井空間可包 括兩個獨立且相互間隔開來的隔離氧化物871和872，以 提供P型井遮蔽。 <第十三實施例之UHV NMOS元件> 第16圖係為依照本揭露第十三實施例之一超高電壓 N型金屬氧化物半導體（UHV NMQS)元件之示意圖。在第 一實施例中，以LOCOS製程製造之元件係具有第一、第 二、第三、第四和第五場氧化物41, 43, 45, 47和49。在 第十實施例中，以STI製程製造之元件係具有第一、第二、 第三、第四和第五隔離氧化物81, 83, 85, 87和89。但本 揭露並不限於此。在某些情況下，如考量製造成本，元件 之製造可以不需要使用LOCOS製程和STI製程，因此如 第16圖所示，第十三實施例中沒有任何場氧化物或隔離 氧化物之生成。 〈第十四實施例之UHV NM0S元件> 第17圖係為依照本揭露第十四實施例之一超高電壓 N型金屬氧化物半導體（UHV NMOS)元件之示意圖。請同 時參照第1圖和第17圖。在第一實施例中，第一圖案化 金屬層64和第二圖案化金屬層74之一部分皆對應地跨越 P型井空間（PWS)，以進行高壓内連接。但本揭露並不限 於此。在第十四實施例中，亦可只有第二圖案化金屬層74 之一部分跨越P型井空間（PWS)以進行高壓内連接，而第 一圖案化金屬層64則在對應P型井空間之兩側形成兩分 19 201240085 I V V f 離部64a和64b而沒有跨越P型井空間，如第17圖所示。 <第十五實施例之UHV NMOS元件> 第18圖係為依照本揭露第十五實施例之一超高電壓 N型金屬氧化物半導體（UHV NMOS)元件之示意圖。請同 時參照第1圖和第18圖。在第一實施例中，第一圖案化 金屬層64和第二圖案化金屬層74之一部分皆對應地跨越 P型井空間（PWS)，以進行高壓内連接。但本揭露並不限 於此。在第十五實施例中，亦可只有第一圖案化金屬層64 之一部分跨越P型井空間（PWS)以進行高壓内連接，而第 二圖案化金屬層74則在對應P型井空間之兩侧形成兩分 離部74a和74b而沒有跨越P型井空間，如第18圖所示。 〈第十六實施例之UHV NMOS元件> 第19圖係為依照本揭露第十六實施例之一超高電壓 N型金屬氧化物半導體（UHV NMOS)元件之示意圖。請同 時參照第1圖和第19圖。在第一實施例中，第一高壓N 型井區域16係位於基體和源極P型井22與P型井241 之間。但本揭露並不限於此。在第十六實施例中，第一高 壓N型井區域16’亦可延伸至基體和源極P型井22處，， 以提供其他應用態樣之實施方式。 <第十七實施例之UHV NMOS元件> 第20圖係為依照本揭露第十七實施例之另一種超高 電壓N型金屬氧化物半導體（UHV NMOS)元件之製造方法 20 201240085 • « « ( r~\ 之示意圖。請同時參照第3C、3D圖和第20圖。在第一 實施例之製造方法中，P型場限層32和N型摻雜層34 係在生成場氧化物（FOX)前已先形成，如第3C、3D圖所 示。但本揭露並不限於此。在某些情況下，P型場限層32 和N型摻雜層34可如第十七實施例所示，在生成場氧化 物（FOX)之後再形成，其中P型場限層32和N型摻雜層 34的離子佈植可穿過第三場氧化物45，以在第三場氧化 物45下方形成，如第20圖所示。 綜上所述，雖然本發明已以實施例揭露如上，然其並 非用以限定本發明。本發明所屬技術領域中具有通常知識 者，在不脫離本發明之精神和範圍内，當可作各種之更動 與潤飾。因此，本發明之保護範圍當視後附之申請專利範 圍所界定者為準。 【圖式簡單說明】 第1圖係為依照本揭露第一實施例之一超高電壓N 型金屬氧化物半導體（UHVNMOS)元件之示意圖。 第2A、2B圖係分別顯示具有N型摻雜層和不具N 型摻雜層之UHVNMOS元件的丨/V特性曲線圖。 第3A〜3E圖係繪示依照本揭露第一實施例之一超高 電壓N型金屬氧化物半導體（UHV NMOS)元件之製造方法 示意圖。 第4A圖係為具有本揭露實施例之一超高電壓N型金 屬氧化物半導體（UHVNMOS)之一元件的上視圖。 第4B圖係為第4A圖元件之局部放大圖。 21 201240085 第5圖係為依照本揭露第二實施例之一超高電壓N 型金屬氧化物半導體（UHVNMOS)元件之示意圖。 第6圖係為依照本揭露第三實施例之一超高電壓N 型金屬氧化物半導體（UHVNMOS)元件之示意圖。 第7圖係為依照本揭露第四實施例之一超高電壓N 型金屬氧化物半導體（UHVNMOS)元件之示意圖。 第8圖係為依照本揭露第五實施例之一超高電壓N 型金屬氧化物半導體（UHVNMOS)元件之示意圖。 第9圖係為依照本揭露第六實施例之一超高電壓N 型金屬氧化物半導體（UHVNMOS)元件之示意圖。 第10圖係為依照本揭露第七實施例之一超高電壓N 型金屬氧化物半導體（UHVNMOS)元件之示意圖。 第11圖係為依照本揭露第八實施例之一超高電壓N 型金屬氧化物半導體（UHVNMOS)元件之示意圖。 第12圖係為依照本揭露第九實施例之一超高電壓N 型金屬氧化物半導體（UHVNMOS)元件之示意圖。 第13圖係為依照本揭露第十實施例之一超高電壓N 型金屬氧化物半導體（UHVNMOS)元件之示意圖。 第14圖係為依照本揭露第十一實施例之一超高電壓 N型金屬氧化物半導體（UHVNMOS)元件之示意圖。 第15圖係為依照本揭露第十二實施例之一超高電壓 N型金屬氧化物半導體（UHVNMOS)元件之示意圖。 第16圖係為依照本揭露第十三實施例之一超高電壓 N型金屬氧化物半導體（UHVNMOS)元件之示意圖。 第17圖係為依照本揭露第十四實施例之一超高電壓 22 201240085 I » W f -TWWI ft N型金屬氧化物半導體（UHVNMOS)元件之示意圖。 第18圖係為依照本揭露第十五實施例之一超高電壓 N型金屬氧化物半導體（UHVNMOS)元件之示意圖。 第19圖係為依照本揭露第十六實施例之一超高電壓 N型金屬氧化物半導體（UHV NMOS)元件之示意圖。 第20圖係為依照本揭露第十七實施例之另一種超高 電壓N型金屬氧化物半導體（UHV NMOS)元件之製造方法 之示意圖。 【主要元件符號說明】 10 :基板 12 :第一 N型埋層 13 :第二N型埋層 14 :第三N型埋層 15 : P型磊晶層 16、16’ ：第一高壓N型井區域 18:第二高壓N型井區域 20、241、242、243 : P 型井 22 :源極和基體P型井 27、29 : N 型井 32 : P 型場限層（P-Top layer) 34 : N 型摻雜層（n-type implant layer) 41 :第一場氧化物 43 :第二場氧化物 45 :第三場氧化物 201240085 47 :第四場氧化物 49 :第五場氧化物 52 :閘極 53 :基體 54 :源極 56 :汲極 61 :内絕緣介電層 63 :接觸孔 64 :第一圖案化金屬層 64a、64b:第一圖案化金屬層之兩分離部 68:内金屬介電層 69 :通孔 74 :第二圖案化金屬層 74a、74b:第二圖案化金屬層之兩分離部 81 :第一隔離氧化物 83 :第二隔離氧化物 85 :第三隔離氧化物 87 :第四隔離氧化物 89 :第五隔離氧化物 NMOS : N型金屬氧化物半導體 HSOR :高壓側操作區域 HVI :高壓内連接 PWS : P型井空間 24Fig. 4A is a top view of one of the elements of the ultrahigh voltage n-type metal oxide semiconductor (UHV NMOS) having one of the embodiments of the present disclosure. 4B 13 201240085 The figure is a partial enlarged view of the element of Figure 4A. The element '' has two UHV NMOSs' as shown in Fig. 4A but may be applied with different operating voltages, respectively. Other components (not shown) such as LVM〇s, bipolar junction transistor (BJT), capacitors, resistors, etc., can be placed in high voltage operating areas (eg, areas larger than 650V operation). In the embodiment, the position and shape of the metal (e.g., the first patterned metal layer 64 or the second patterned metal layer 74), including the substrate 53, the source 54 and the drain 56, are shown in Figure 4B. Furthermore, the P-type field limiting layer 32 and the N-type doping layer 34 formed by the same mask are also shown in FIG. 4B. Furthermore, the p-wells 241 and 242 which are separated from each other provide self-shadowing and isolation in the high-voltage connection region, which is also shown in Fig. 4B. Wherein, the metal portion (b) of the drain 56 may be -τ-shaped ' and the metal portions (a) and (b) may be applied with different voltages. Furthermore, the bungee: the extension (see Figure 4B) can be used as a metal part of the high-voltage internal connection, and other components placed in the element of Figure 4A (not shown, such as LVm〇s bi-carrier junction transistor) (BJT) 'capacitance, resistance, etc.) to complete the electrical connection. <UHV NMOS device of the second embodiment> FIG. 5 is a schematic diagram of a super-internal voltage n-type metal oxide semiconductor (UHVNMOS) device according to a second embodiment of the present disclosure. The element of the second embodiment may include one layer instead of two metal layers. Please also refer to Figure 1 and Figure 5. The elements of Figs. 1 and 5 have the same structure, except that the two metal layers of the element of Fig. 1 are reduced to a layer of metal reed (i.e., the first patterned metal layer 64) of Fig. 5. <UHV NMOS device of the third embodiment 201240085 » vv Fig. 6 is a schematic diagram of an ultrahigh voltage N-type metal oxide semiconductor (UHVNMOS) device according to a third embodiment of the present disclosure. In the third embodiment, the N-type buried layer (NBL) of the component can be removed as needed for different applications. Please refer to both Figure 1 and Figure 6. The elements of Fig. 6 and Fig. 1 are identical in structure except that the first N buried layer 12 at the source terminal in Fig. 1 is removed in the element structure of Fig. 6 and is not shown. <UHV NMOS device of the fourth embodiment> FIG. 7 is a schematic diagram of an ultrahigh voltage N-type metal oxide semiconductor (UHV NMOS) device according to a fourth embodiment of the present disclosure. Please refer to both Figure 1 and Figure 7. The elements of Fig. 7 and Fig. 1 are identical in structure' except that the second N-type buried layer 13 located in the high voltage operation region (HSOR) in Fig. 1 is removed in the element structure of Fig. 7 and is not displayed (when high voltage operation is performed) The second N-type buried layer 13 can be removed when the region is properly insulated). <UHV NMOS device of the fifth embodiment> Fig. 8 is a schematic view showing an ultrahigh voltage N-type metal oxide semiconductor (UHV NMOS) device according to a fifth embodiment of the present disclosure. In the first embodiment, the p-type well space (PWS) has two independent p-type wells 241 and 242' but the disclosure is not limited thereto. In a fifth embodiment, the P-well space of the high pressure interconnect may include N P-wells, and N may be a positive integer. As shown in Figure 8, the P-well space has three separate and spaced P-wells 241, 242, and 243' to provide self-shadowing and isolation. <UHV NMOS element of the sixth embodiment> 15 201240085 ... Milk pressure N is a schematic view of a metal oxide semiconductor (UHV NMOS) element according to a sixth embodiment of the present disclosure. In the second embodiment, the p-crack in the p-type well space of the high-voltage interconnect is also removed according to the & λ town 9 map and as needed. Please refer to both Figure 1 and Figure 9. The components and structures of Figure 1 are the same, except for the P-wells 241 and 242 in the 1st ® in the still-pressed interconnect code, which are removed in the component structure of Figure 9 and are shown in Figure 9 (when P-wells 241 and 242 can be removed when the high pressure internal connection (HVI) region is properly self-shielded. <UΗV NMOS element of the seventh embodiment> FIG. 10 is a schematic diagram of an ultrahigh voltage Ν-type metal oxide semiconductor (UHVNMOS) element according to a seventh embodiment of the present disclosure. In the seventh embodiment, one or more N-type buried layers (NBL) may be added in the element to improve the isolation effect. Please refer to both Figure 1 and Figure 1 at the same time. The component structure of Fig. 10 further includes a third N-type buried layer 14 formed between the p-type wells 241, 242 in the drain 56 and the P-type well space. <UHV NMOS device of the eighth embodiment> Fig. 11 is a schematic diagram of an ultrahigh voltage N-type metal oxide semiconductor (UHV NMOS) device according to an eighth embodiment of the present disclosure. In the first embodiment, a P-type layer 32 and an n-type implant layer 34 are disposed in the first high-pressure N-well region 16 and are constructed as a complete Block, but the disclosure is not limited to this. In the eighth embodiment, the P-type field limiting layer 32 and the N-type doping layer 34 may also be constructed as a plurality of independent blocks as shown in Fig. 11. 201240085 <UHV NM〇s element of the ninth embodiment> Fig. 12 is a schematic view showing an ultrahigh voltage N-type metal oxide semiconductor (UHV NMOS) element according to a ninth embodiment of the present disclosure. In the first embodiment, the element includes the first field oxide 41, the second field oxide 43, the third field oxide 45, the fourth field oxide 47, and the fifth field oxide 'but the disclosure is not limited this. Please refer to both Figure 1 and Figure 12. The third field oxide 45 in FIG. 1 is formed in the first high-voltage N-type well region 16 and on the N-type doped layer 34, and may also be in the ninth embodiment from the element structure of FIG. Removed to provide an implementation of other application aspects. <UHV NMOS device of the tenth embodiment> Fig. 13 is a schematic view showing an ultrahigh voltage N-type metal oxide semiconductor (UHV NMOS) device according to a tenth embodiment of the present disclosure. In the semi-conducting process, the thermally generated oxide is mainly used as an insulating material. There are two main processes that can be used to isolate adjacent MOS transistors, the Local Oxidation of Silicon (LOCOS) process and the Shallow Trench Isolation (STI) process. In the first embodiment, the elements as shown in Fig. 1 are fabricated in a LOCOS process, and the thick oxidized oxide grown for isolation is called field oxide (41, 43, 45, 47 and 49). . Since the entire LOCOS structure is thermally generated, the LOCOS process has the advantage of a simple process and high quality oxides. However, the disadvantage is that it produces a "bird's beak" effect. To avoid the appearance of a "bird's beak" shape, the components of the tenth embodiment are manufactured in an STI process. In the case of space, the STI process can be used to form a smaller range of isolation regions, and can be more suitable for manufacturing components with high density requirements. Therefore, the first, second, third, and third in the first figure The fourth and fifth field oxides 41, 43, 45, 47 and 49 are the first, second, third, fourth and fifth isolated oxides 81, 83, 85 in the tenth embodiment. Replaced by 87 and 89, as shown in Fig. 13. <UHV NMOS device of the eleventh embodiment> Fig. 14 is an ultrahigh voltage N-type metal oxide semiconductor according to the eleventh embodiment of the present disclosure. A schematic diagram of a (UHV NMOS) device. In a tenth embodiment, the device has a first isolation oxide 81, a second isolation oxide 83, a third isolation oxide 85, a fourth isolation oxide 87, and a fifth isolation oxide. 89. However, the disclosure is not limited to this. Please refer to Figure 13 and 14 is a third isolation oxide 85 in FIG. 13 formed in the first high-pressure N-well region 16 and above the N-doped layer 34 (ie, the floating region), and may also be implemented in the eleventh implementation. In the example, the component structure of Fig. 14 is removed to provide an implementation of other application aspects. <UHV NMOS device of the twelfth embodiment> FIG. 15 is a twelfth embodiment according to the present disclosure. A schematic diagram of an ultra high voltage N-type metal oxide semiconductor (UHV NMOS) device. In the tenth embodiment, the device has a first isolation oxide 81, a second isolation oxide 83, a third isolation oxide 85, and a fourth The isolation oxide 87 and the fifth isolation oxide 89, wherein the fourth isolation oxide 87 located in the P-type well space (PWS) is a complete body. However, the disclosure is not limited thereto. Please refer to 201240085 1 vv I ~ Rw\>/it~\ Figures 13 and 15. In a twelfth embodiment, the P-well space may include two separate and spaced apart isolation oxides 871 and 872 to provide a P-type Well shading. <UHV NMOS element of the thirteenth embodiment> Fig. 16 is the thirteenth according to the present disclosure A schematic diagram of an ultrahigh voltage N-type metal oxide semiconductor (UHV NMQS) device of one embodiment. In the first embodiment, the components manufactured by the LOCOS process have first, second, third, fourth, and fifth components. Field oxides 41, 43, 45, 47 and 49. In the tenth embodiment, the elements fabricated in the STI process have first, second, third, fourth and fifth isolation oxides 81, 83, 85 , 87 and 89. However, the disclosure is not limited to this. In some cases, such as manufacturing cost considerations, the fabrication of components may not require the use of a LOCOS process and an STI process, so as shown in Figure 16, the thirteenth embodiment does not have any field oxide or isolation oxide formation. <UHV NMOS device of the fourteenth embodiment> Fig. 17 is a view showing an ultrahigh voltage N-type metal oxide semiconductor (UHV NMOS) device according to a fourteenth embodiment of the present disclosure. Please refer to Figures 1 and 17 at the same time. In a first embodiment, a portion of the first patterned metal layer 64 and the second patterned metal layer 74 respectively span the P-well space (PWS) for high voltage internal connections. However, this disclosure is not limited to this. In the fourteenth embodiment, only a portion of the second patterned metal layer 74 may span the P-type well space (PWS) for high voltage internal connection, and the first patterned metal layer 64 may be corresponding to the P-type well space. Two points are formed on both sides. 19 201240085 IVV f The separations 64a and 64b do not span the P-type well space, as shown in Figure 17. <UHV NMOS device of the fifteenth embodiment> FIG. 18 is a schematic diagram of an ultrahigh voltage N-type metal oxide semiconductor (UHV NMOS) device according to a fifteenth embodiment of the present disclosure. Please refer to Figures 1 and 18 at the same time. In a first embodiment, a portion of the first patterned metal layer 64 and the second patterned metal layer 74 respectively span the P-well space (PWS) for high voltage internal connections. However, this disclosure is not limited to this. In the fifteenth embodiment, only a portion of the first patterned metal layer 64 may span the P-type well space (PWS) for high-voltage internal connection, and the second patterned metal layer 74 may correspond to the P-type well space. Two separate portions 74a and 74b are formed on both sides without crossing the P-type well space, as shown in Fig. 18. <UHV NMOS device of the sixteenth embodiment> Fig. 19 is a view showing an ultrahigh voltage N-type metal oxide semiconductor (UHV NMOS) device according to a sixteenth embodiment of the present disclosure. Please refer to Figures 1 and 19 at the same time. In the first embodiment, the first high pressure N-well region 16 is located between the base and source P-well 22 and the P-well 241. However, the disclosure is not limited to this. In a sixteenth embodiment, the first high pressure N-well region 16' may also extend to the base and source P-well 22 to provide other embodiments of the application. <UHV NMOS device of the seventeenth embodiment> FIG. 20 is a manufacturing method of another ultrahigh voltage N-type metal oxide semiconductor (UHV NMOS) device according to the seventeenth embodiment of the present disclosure. 201240085 • « «(r~\ schematic diagram. Please refer to the 3C, 3D, and 20th drawings at the same time. In the manufacturing method of the first embodiment, the P-type field limiting layer 32 and the N-type doping layer 34 are formed in the field oxide (FOX) has been formed before, as shown in Figures 3C and 3D. However, the disclosure is not limited thereto. In some cases, the P-type field limiting layer 32 and the N-type doping layer 34 may be implemented as the seventeenth embodiment. As shown in the example, after formation of a field oxide (FOX), ion implantation of the P-type field limiting layer 32 and the N-type doping layer 34 can pass through the third field oxide 45 to oxidize in the third field. The invention is formed under the object 45, as shown in Fig. 20. In summary, although the invention has been disclosed above by way of example, it is not intended to limit the invention. Within the spirit and scope of the present invention, various changes and retouchings can be made. Therefore, the scope of protection of the present invention is BRIEF DESCRIPTION OF THE DRAWINGS The following is a schematic diagram of an ultrahigh voltage N-type metal oxide semiconductor (UHVNMOS) device according to a first embodiment of the present disclosure. 2B shows a 丨/V characteristic diagram of a UHV NMOS device having an N-type doped layer and an N-type doped layer, respectively. FIGS. 3A to 3E are diagrams showing an ultra-high voltage according to the first embodiment of the present disclosure. A schematic diagram of a method of fabricating an N-type metal oxide semiconductor (UHV NMOS) device. Fig. 4A is a top view of one element of an ultrahigh voltage N-type metal oxide semiconductor (UHVNMOS) having one of the disclosed embodiments. It is a partial enlarged view of the element of Figure 4A. 21 201240085 Figure 5 is a schematic diagram of an ultra-high voltage N-type metal oxide semiconductor (UHVNMOS) device according to a second embodiment of the present disclosure. A schematic diagram of an ultra high voltage N-type metal oxide semiconductor (UHVNMOS) device according to a third embodiment is disclosed. FIG. 7 is an ultra high voltage N-type metal oxide semiconductor (UHVNMOS) device according to a fourth embodiment of the present disclosure. Figure 8 is a schematic diagram of an ultra-high voltage N-type metal oxide semiconductor (UHVNMOS) device according to a fifth embodiment of the present disclosure. Figure 9 is an ultra-high voltage N according to a sixth embodiment of the present disclosure. FIG. 10 is a schematic diagram of an ultra high voltage N-type metal oxide semiconductor (UHVNMOS) device according to a seventh embodiment of the present disclosure. FIG. 11 is a schematic view of the present invention. A schematic diagram of an ultrahigh voltage N-type metal oxide semiconductor (UHVNMOS) device of an eighth embodiment. Figure 12 is a schematic diagram of an ultra high voltage N-type metal oxide semiconductor (UHVNMOS) device in accordance with a ninth embodiment of the present disclosure. Figure 13 is a schematic diagram of an ultra high voltage N-type metal oxide semiconductor (UHVNMOS) device in accordance with a tenth embodiment of the present disclosure. Figure 14 is a schematic diagram of an ultrahigh voltage N-type metal oxide semiconductor (UHVNMOS) device in accordance with an eleventh embodiment of the present disclosure. Figure 15 is a schematic diagram of an ultrahigh voltage N-type metal oxide semiconductor (UHVNMOS) device in accordance with a twelfth embodiment of the present disclosure. Figure 16 is a schematic diagram of an ultrahigh voltage N-type metal oxide semiconductor (UHVNMOS) device in accordance with a thirteenth embodiment of the present disclosure. Figure 17 is a schematic diagram of an ultra-high voltage 22 201240085 I » W f -TWWI ft N-type metal oxide semiconductor (UHVNMOS) device in accordance with a fourteenth embodiment of the present disclosure. Figure 18 is a schematic diagram of an ultra high voltage N-type metal oxide semiconductor (UHVNMOS) device in accordance with a fifteenth embodiment of the present disclosure. Figure 19 is a schematic diagram of an ultra high voltage N-type metal oxide semiconductor (UHV NMOS) device in accordance with a sixteenth embodiment of the present disclosure. Fig. 20 is a view showing a method of manufacturing another ultrahigh voltage N-type metal oxide semiconductor (UHV NMOS) device in accordance with a seventeenth embodiment of the present disclosure. [Description of main component symbols] 10: Substrate 12: First N-type buried layer 13: Second N-type buried layer 14: Third N-type buried layer 15: P-type epitaxial layer 16, 16': first high-voltage N-type Well area 18: second high pressure N-type well area 20, 241, 242, 243: P-type well 22: source and base P-type well 27, 29: N-type well 32: P-type field limiting layer (P-Top layer 34: n-type implant layer 41: first field oxide 43: second field oxide 45: third field oxide 201240085 47: fourth field oxide 49: fifth field oxidation 52: gate 53: substrate 54: source 56: drain 61: inner insulating dielectric layer 63: contact hole 64: first patterned metal layer 64a, 64b: two separate portions 68 of the first patterned metal layer Inner metal dielectric layer 69: through hole 74: second patterned metal layer 74a, 74b: two separated portions of the second patterned metal layer 81: first isolation oxide 83: second isolation oxide 85: third Isolation oxide 87: fourth isolation oxide 89: fifth isolation oxide NMOS: N-type metal oxide semiconductor HSOR: high-voltage side operation region HVI: high-voltage internal connection PWS: P-type well space 24