CN104810383B - Semiconductor element and its manufacture method - Google Patents
Semiconductor element and its manufacture method Download PDFInfo
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- CN104810383B CN104810383B CN201410041840.2A CN201410041840A CN104810383B CN 104810383 B CN104810383 B CN 104810383B CN 201410041840 A CN201410041840 A CN 201410041840A CN 104810383 B CN104810383 B CN 104810383B
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 59
- 238000000034 method Methods 0.000 title claims abstract description 37
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 16
- 239000004020 conductor Substances 0.000 claims abstract description 87
- 238000002955 isolation Methods 0.000 claims abstract description 79
- 239000000758 substrate Substances 0.000 claims abstract description 65
- 229910052751 metal Inorganic materials 0.000 claims description 34
- 239000002184 metal Substances 0.000 claims description 34
- 230000005611 electricity Effects 0.000 claims description 3
- 239000010410 layer Substances 0.000 description 146
- 239000000463 material Substances 0.000 description 25
- 238000000059 patterning Methods 0.000 description 15
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 14
- 238000005516 engineering process Methods 0.000 description 13
- 238000005468 ion implantation Methods 0.000 description 12
- 239000011229 interlayer Substances 0.000 description 10
- 230000015556 catabolic process Effects 0.000 description 9
- 230000015572 biosynthetic process Effects 0.000 description 7
- 239000000377 silicon dioxide Substances 0.000 description 7
- 229910052581 Si3N4 Inorganic materials 0.000 description 6
- 230000005684 electric field Effects 0.000 description 6
- 238000002347 injection Methods 0.000 description 6
- 239000007924 injection Substances 0.000 description 6
- 239000003989 dielectric material Substances 0.000 description 5
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 5
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 4
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 4
- 229910052785 arsenic Inorganic materials 0.000 description 4
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 4
- 229910052796 boron Inorganic materials 0.000 description 4
- 229910052698 phosphorus Inorganic materials 0.000 description 4
- 239000011574 phosphorus Substances 0.000 description 4
- 230000001012 protector Effects 0.000 description 4
- 229910052710 silicon Inorganic materials 0.000 description 4
- 230000003068 static effect Effects 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 238000005229 chemical vapour deposition Methods 0.000 description 3
- 229920002120 photoresistant polymer Polymers 0.000 description 3
- 239000011241 protective layer Substances 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- 229910045601 alloy Inorganic materials 0.000 description 2
- 239000000956 alloy Substances 0.000 description 2
- 239000004411 aluminium Substances 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 239000011368 organic material Substances 0.000 description 2
- 238000005240 physical vapour deposition Methods 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 2
- 229910052721 tungsten Inorganic materials 0.000 description 2
- 239000010937 tungsten Substances 0.000 description 2
- 229910005540 GaP Inorganic materials 0.000 description 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- 229910003855 HfAlO Inorganic materials 0.000 description 1
- 229910000673 Indium arsenide Inorganic materials 0.000 description 1
- 229910003811 SiGeC Inorganic materials 0.000 description 1
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 1
- 239000002253 acid Substances 0.000 description 1
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 1
- 229910052593 corundum Inorganic materials 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000005137 deposition process Methods 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000001595 flow curve Methods 0.000 description 1
- 229910052732 germanium Inorganic materials 0.000 description 1
- CJNBYAVZURUTKZ-UHFFFAOYSA-N hafnium(IV) oxide Inorganic materials O=[Hf]=O CJNBYAVZURUTKZ-UHFFFAOYSA-N 0.000 description 1
- 150000003949 imides Chemical class 0.000 description 1
- RPQDHPTXJYYUPQ-UHFFFAOYSA-N indium arsenide Chemical compound [In]#[As] RPQDHPTXJYYUPQ-UHFFFAOYSA-N 0.000 description 1
- 229910010272 inorganic material Inorganic materials 0.000 description 1
- 239000011147 inorganic material Substances 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 238000003701 mechanical milling Methods 0.000 description 1
- 229910001092 metal group alloy Inorganic materials 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 238000002156 mixing Methods 0.000 description 1
- 229910003465 moissanite Inorganic materials 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 230000002265 prevention Effects 0.000 description 1
- 238000004062 sedimentation Methods 0.000 description 1
- 229910021332 silicide Inorganic materials 0.000 description 1
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 1
- 229910010271 silicon carbide Inorganic materials 0.000 description 1
- 125000006850 spacer group Chemical group 0.000 description 1
- 238000004528 spin coating Methods 0.000 description 1
- 229910001845 yogo sapphire Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
- H01L29/7835—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's with asymmetrical source and drain regions, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
- H01L29/063—Reduced surface field [RESURF] pn-junction structures
- H01L29/0634—Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42364—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity
- H01L29/42368—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity the thickness being non-uniform
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Chemical & Material Sciences (AREA)
- Composite Materials (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Manufacturing & Machinery (AREA)
Abstract
The invention discloses a kind of semiconductor element and its manufacture method.Semiconductor element includes：Substrate, isolation structure, grid structure, source area and drain region and conductor layer；Source area is located in substrate with drain region；Isolation structure is located between source area and drain region；Grid structure is located in the substrate between source area and isolation structure；Conductor layer is located above substrate, is at least extended to from above source area above isolation structure, and is electrically connected with source area；Substrate includes the firstth area and the secondth area, it is more than the curvature in the profile of the source area in the firstth area in the curvature of the profile of the source area in the secondth area, and the width of the part of the conductor layer of the covering isolation structure of side is more than the width of the part of the conductor layer of the covering isolation structure above the firstth area on the second region.
Description
Technical field
The invention relates to a kind of semiconductor element and its manufacture method.
Background technology
Super-pressure element must have high breakdown voltage (breakdown voltage) and low unlatching electricity in operation
Hinder (on-state resistance, Ron), to reduce power attenuation.In current super-pressure element, it is frequently found in source
It is extreme to have very big current gathering effect, thus as collapse point, cause the breakdown voltage of element to decline, and leakage current
Situation it is very serious.
The content of the invention
The embodiment of the present invention provides a kind of semiconductor element and its manufacture method, providing with high breakdown voltage and
The semiconductor element of low-leakage current.
The present invention proposes a kind of semiconductor element, it include substrate, isolation structure, grid structure, with the first conductivity type
Source area and drain region and conductor layer.Source area is located in substrate with drain region.Isolation structure is located at source area and drain electrode
Between area.Grid structure is located in the substrate between source area and isolation structure.Conductor layer is located above substrate, at least from source electrode
Extended to above area above isolation structure, and be electrically connected with source area.Substrate includes the firstth area and the secondth area, the source in the secondth area
The curvature of the profile of polar region is more than the curvature in the profile of the source area in the firstth area, and covering isolation structure square on the second region
Conductor layer part width be more than above the firstth area covering isolation structure conductor layer part width.
According to one embodiment of the invention, the conductor layer is topmost metal layer.
According to one embodiment of the invention, the semiconductor element includes multiple linearity regions and multiple Turning regions, directly
It is located at the firstth area one of in line region；It is located at the secondth area one of in Turning regions.
According to one embodiment of the invention, the semiconductor element is further included：Top layer with the second conductivity type, positioned at isolation
In substrate below structure；And the terraced layer with the first conductivity type, between top layer and isolation structure.
According to one embodiment of the invention, the semiconductor element further includes the first well region with the second conductivity type, is located at
In substrate, wherein source area is located in the first well region, and the well region of grid structure covering part first；With mixing for the second conductivity type
Miscellaneous area be located at the first well region in, it is adjacent with source area, and with the common connecting conductor layer of source area；And with the first conductivity type
Second well region, in substrate, wherein the first well region and drain region are located in the second well region.
The present invention also proposes a kind of manufacture method of semiconductor element, is included in substrate and forms isolation structure.In substrate
Upper formation grid structure.In the substrate of grid structure and the both sides of isolation structure formed with the first conductivity type source area with
Drain region with the first conductivity type.Source area is close to grid structure, and drain region is close to isolation structure.Formed and led above substrate
Body layer.Conductor layer is extended to from above source area above isolation structure, and is electrically connected with source area.Substrate includes the firstth area and the
2nd area, are more than the curvature in the profile of the source area in the firstth area in the curvature of the profile of the source area in the secondth area, and in the secondth area
The width of the part of the conductor layer of the covering isolation structure of top is more than the conductor layer of the covering isolation structure above the firstth area
Partial width.
According to one embodiment of the invention, the conductor layer is topmost metal layer.
According to one embodiment of the invention, the semiconductor element includes multiple linearity regions and multiple Turning regions, directly
It is located at the firstth area one of in line region；It is located at the secondth area one of in Turning regions.
According to one embodiment of the invention, the manufacture method of the semiconductor element is further included：Base below isolation structure
The top layer with the second conductivity type is formed in bottom；And the ladder with the first conductivity type is formed between top layer and isolation structure
Layer.
According to one embodiment of the invention, the manufacture method of the semiconductor element is further included：Being formed in substrate has the
First well region of two conductivity types, wherein source area are located in the first well region, and the well region of grid structure covering part first；In first
The doped region with the second conductivity type is formed in well region, doped region is adjacent with source area, and with the common connecting conductor layer of source area；
And the second well region with the first conductivity type is formed in substrate, wherein the first well region and drain region are located at the second well region
In.
Based on above-mentioned, of the invention semiconductor element system according to the different conductor layers by source terminal of source area contour curvature
(such as topmost metal layer) is designed to different width, to disperse the electric field of curvature larger part or corner, lifting collapse
Voltage, reduces leakage current.
For the features described above and advantage of the present invention can be become apparent, special embodiment below, and coordinate institute's accompanying drawings
It is described in detail below.
Brief description of the drawings
Fig. 1 is a kind of top view of semiconductor element according to the embodiment of the present invention.
Fig. 2A to Fig. 2 G is a kind of diagrammatic cross-section of the manufacture method of semiconductor element according to the embodiment of the present invention, its
Middle Fig. 2 G are Fig. 1 tangent line I-I and II-II profile.
Fig. 3 is electric leakage flow curve of three kinds of semiconductor elements in the test for carrying out electric static discharge protector 2kV, described half
The width of the part of the conductor layer of covering isolation structure of the conductor element at respective source terminal is different.
Fig. 4 is breakdown voltage curve of three kinds of semiconductor elements in the test for carrying out electric static discharge protector 2kV, described
The width of the part of the conductor layer of covering isolation structure of the semiconductor element at respective source terminal is different.
【Symbol description】
10：Substrate
12、14、16、18、32：Well region
20：Top layer
22：Terraced layer
24a~24d：Isolation structure
26：Gate dielectric layer
28：Gate conductor layer
30：Grid structure
32：Clearance wall
34：Source area
36：Drain region
38、40：Doped region
42、48：Dielectric layer
44a~44e：Contact hole
46a~46d, 50a~50b：Conductor layer
52a~52b：Interlayer hole
60：It is online in metal
99：Semiconductor element
100：Firstth area
102：Secondth area
104、106：Mask
W1、W2、W3、W4：Width
OP1、OP2：End points
Embodiment
Idea of the invention can be used for the semiconductor element that source area has Turning regions, and e.g. source area is runway
Type or U-shaped semiconductor element, but be not limited.The semiconductor element of the present invention is will according to source area contour curvature difference
The conductor layer (such as topmost metal layer) of source terminal is designed to different width, with scattered curvature larger part or corner
Electric field, lifted breakdown voltage, reduce leakage current.Illustrate the following is with the semiconductor element with U-shaped source area, however,
The present invention is not limited thereto.
Fig. 1 is a kind of top view of semiconductor element according to the embodiment of the present invention.Fig. 2 G for Fig. 1 tangent line I-I and
II-II profile.
Below in an example, the first conductivity type is N-type, and the second conductivity type is p-type.P-type doping e.g. boron；N
Type doping e.g. phosphorus or arsenic.However, the present invention is not limited thereto.In other embodiments, the first conductivity type can be P
Type, and the second conductivity type can be N-type.
Fig. 1 and Fig. 2 G are refer to, semiconductor element 99 of the invention can be a kind of high voltage device, super-pressure element (behaviour
Make voltage 300V to 1000V), power component, sideways diffusion metal-oxide semiconductor (MOS) (LDMOS) or insulated gate bipolar transistor
Manage (IGBT).Semiconductor element 99 includes substrate 10, isolation structure 24a~24d, grid structure 30, source area 34, drain region 36
And online 60 (including conductor layers 50a, 50b etc.) in metal.The present invention semiconductor element 99 can also further include well region 12,
16th, 18, top layer 20, terraced layer 22 and doped region 38,40.
Substrate 10 is, for example, the semiconductor base with the second conductivity type, such as P-type substrate.The material example of semiconductor base
It is selected from this way by least one of Si, Ge, SiGe, GaP, GaAs, SiC, SiGeC, InAs and InP group constituted material
Material.Substrate 10 can also cover silicon insulation (SOI) substrate.Substrate 10 can be the epitaxial wafer with the second conductivity type, such as P
Type extension (P-epi) chip.
In one embodiment, semiconductor element 99 include multiple linearity regions and multiple Turning regions, but not as
Limit.In the present embodiment, the first area 100 of substrate 10 can be that (curvature of the wherein profile of source area 34 is small or is for linearity region
Zero)；Can be Turning regions in the second area 200 of substrate 10 (curvature of the wherein profile of source area 34 is big).
Well region 12 has the first conductivity type, and it is located in substrate 10.Well region 12 is, for example, N traps, or is high pressure N traps
(HVNW).Well region 16 and 18 has the second conductivity type, e.g. p-well.Well region 16 is located at adjacent with well region 12 in substrate 10.Trap
Area 18 is located among well region 12.
Isolation structure 24a~24d is located in substrate 10.In more detail, the well region 16 of isolation structure 24a covering parts.
Isolation structure 24b covers the well region 16 of another part, and extends over part well region 12 and well region 18.Isolation structure 24c with
24d is located on the part well region 12 of the side of well region 18.Isolation structure 24c is located between well region 18 and isolation structure 24d.Isolation junction
Structure 24a, 24b, 24c, 24d be insulating materials, be, for example, undoped with silica, silicon nitride or its combination.
Grid structure 30 include gate dielectric layer 26 with gate conductor layer 28.Grid structure 30 is located in substrate 12, covering
Partial well region 18, well region 12, grid structure 30 can be on isolation structure 24c be extended over.On the side wall of grid structure 30
Also clearance wall 32.The material of clearance wall 32 is, for example, silica, silicon nitride or its combination.
Source area 34 has the first conductivity type, e.g. N-type source region and N-type drain electrode (N+) with drain region 36.Source electrode
Area 34 is located at isolation structure 24c respectively with drain region 36 and in the substrate 10 of the both sides of grid structure 30, wherein source area 34 connects
Nearly grid structure 30, drain region 36 is close to isolation structure 24c.More specifically, source area 34 is located at the side of grid structure 30
Among well region 18.Drain region 36 is located among the well region 12 between isolation structure 24c and isolation structure 24d.Source area 34 and leakage
The doping concentration of polar region 36 is, for example, 1 × 1014/cm2To 9 × 1016/cm2。
Doped region 38,40 has the second conductivity type, the e.g. dense doped region of p-type (P+).Doped region 38 is located at isolation structure
In well region 18 between 24b and source area 34.Doped region 40 is located among well region 16.The doping concentration of doped region 38,40 is for example
It is 1 × 1014/cm2To 9 × 1016/cm2。
Top layer 20 has the second conductivity type, e.g. p-type top layer (P-Top).Top layer 20 is located at below isolation structure 24c
In well region 12, to lift breakdown voltage.Terraced layer 22 has the first conductivity type, the e.g. terraced layer (N-grade) of N-type.Terraced layer 22
Between top layer 20 and isolation structure 24c, to reduce conducting resistance.The doping concentration of terraced layer 22 is mixed not less than well region 12
Miscellaneous concentration.The doping concentration of top layer 20 is, for example, 1 × 1011/cm2To 9 × 1013/cm2.The doping concentration of terraced layer 22 is, for example, 1 ×
1011/cm2To 9 × 1013/cm2。
In one embodiment, online 60 dielectric layer 42, contact hole 44a~44e, conductor layer (or first are included in metal
Metal level) 46a~46d, dielectric layer 48, interlayer hole 52a~52b and conductor layer (or top metal level) 50a~50b, but not
As limit.In other embodiments, in metal online 60 can further include conductor layer 46a~46d and conductor layer 50a~50b it
Between multilayer conductor layer (or metal level) and multiple interlayer holes.Conductor layer 46a is electrical by contact hole 44a and doped region 40
Connection.Conductor layer 46b is electrically connected with doped region 38 and source area 34 respectively by contact hole 44b, 44c.Conductor layer 46c
It is electrically connected with by contact hole 44d with gate conductor layer 28.Conductor layer 46d is electrically connected with by contact hole 44e with drain region 36.
Conductor layer 50a, 50b can be in metal online 60 topmost metal layer, pass through interlayer hole 52a~52b and conductor
Layer 46a~46d is electrically connected with.Conductor layer 50a can be described as source metal, at least from source area 34 (or self-isolation structure 24b)
Top is extended to above isolation structure 24c, and by interlayer hole 52a, conductor layer 46b and contact hole 44c to be electrically connected with source electrode
Area 34.Conductor layer 50b can be described as extending to above drain metal layer, at least self-isolation structure 24c above isolation structure 24d, and
By interlayer hole 52b, conductor layer 46d and contact hole 44e to be electrically connected with drain region 36.
It refer to the width of the conductor layer 50a of covering isolation structure 24c in Fig. 1 and Fig. 2 G, the first area 100 part
W1, be the first area 100 conductor layer 50a correspondences isolation structure 24c end points OP1 in place of to conductor layer 50a (proximity conductor floor
The distance at edge 50b).The width W2 of the conductor layer 50a of covering isolation structure 24c in second area 200 part, is second
To conductor layer 50a (proximity conductor floor 50b) edge in place of the conductor layer 50a correspondence isolation structures 24c in area 200 end points OP2
Distance.In the present embodiment, the width W2 of the conductor layer 50a of the covering isolation structure 24c in the second area 200 part is more than
The width W1, i.e. W2 of the conductor layer 50a of covering isolation structure 24c in first area 100 part>W1.Width W2 such as width
1.5 times to 5 times of W1.
From the point of view of Fig. 1 top view, from region 100 to region 200, the curvature of the profile of source area 34 is incremented by.In this reality
Apply in example, the width of covering isolation structure 24c conductor layer 50a part is also gradually smoothly passed from region 100 to region 200
Increase, make conductor layer 50a that there is smooth profile (as shown in Figure 1).(do not illustrate) in another embodiment, cover isolation structure
The width of 24c conductor layer 50a part can also from region 100 to region 200 gradually ladder it is incremental, make conductor layer 50a
With scalariform profile.
In the embodiment above, in the first area 100 of substrate 10 be semiconductor element 99 linearity region；In substrate
In 10 the second area 200 is the Turning regions of semiconductor element 99.However, the present invention is not limited thereto, as long as second
The curvature of the profile of the source area 34 of the part of semiconductor element 99 in area 200 is more than the semiconductor element in the first area 100
The curvature of the profile of the source area 34 of the part of part 99 is the scope that the present invention covers.
Fig. 2A to 2G is a kind of diagrammatic cross-section of the manufacture method of semiconductor element according to the embodiment of the present invention.
Fig. 2A be refer to there is provided substrate 10, substrate 10 includes the first area 100 and the second area 200.Then, in substrate 10
Form the mask layer 102 of patterning.The material of the mask layer 102 of patterning is, for example, photoresist or dielectric material.Afterwards, with
The mask layer 102 of patterning is injecting mask, carries out ion implantation technology, to be formed in substrate 10 with the first conductivity type
Well region 12.Well region 12 is, for example, N traps.The doping that ion implantation technology is injected is, for example, phosphorus or arsenic, and the dosage of doping is for example
It is 1 × 1011/cm2To 9 × 1013/cm2, the energy of injection is, for example, 50KeV to 200KeV.
Afterwards, Fig. 2 B are refer to, the mask layer 102 of patterning is removed.Afterwards, the mask of patterning is formed on the substrate 10
Layer 104.The material of the mask layer 104 of patterning is, for example, photoresist or dielectric material.Afterwards, with the mask layer of patterning
104 be injecting mask, carries out ion implantation technology, to form the well region 16 and 18 with the second conductivity type in substrate 10.
Well region 16,18 is, for example, p-well.The doping that ion implantation technology is injected e.g. boron, the dosage of doping is, for example, 1 × 1011/
cm2To 9 × 1013/cm2, the energy of injection is, for example, 50KeV to 200KeV.
Thereafter, Fig. 2 C are refer to, the mask layer 104 of patterning is removed.Then, the mask of patterning is formed on the substrate 10
Layer 106.The material of the mask layer 106 of patterning is, for example, photoresist or dielectric material.Afterwards, with the mask layer of patterning
106 be injecting mask, carries out ion implantation technology, to form the top layer 20 with the second conductivity type in substrate 10.Top layer 20
E.g. p-type top layer.The doping that ion implantation technology is injected e.g. boron, the dosage of doping is, for example, 1 × 1011/cm2To 9
×1013/cm2, the energy of injection is, for example, 50KeV to 200KeV.
Then, Fig. 2 C are continued referring to, are injecting mask with the mask layer 106 of patterning, ion implantation technology is carried out, with
The terraced layer 22 with the first conductivity type is formed in substrate 10.Terraced layer 22 is, for example, the terraced layer of N-type.What ion implantation technology was injected
Doping e.g. phosphorus or arsenic, the dosage of doping is, for example, 1 × 1011/cm2To 9 × 1013/cm2, the energy of injection is, for example,
50KeV to 200KeV.
Thereafter, Fig. 2 D are refer to, the mask layer 106 of patterning is removed.Then, formed isolation structure 24a, 24b, 24c,
24d, to define active area.Isolation structure 24a, 24b, 24c, 24d material be, for example, undoped with silica, its formed
Method can aoxidize isolation method or shallow trench isolation method using field.Isolation structure 24a, 24b, 24c, 24d thickness is, for example,
100nm to 800nm.
Thereafter, Fig. 2 E are refer to, grid structure 30 is formed in neighbouring isolation structure 24c substrate 10.In an embodiment
In, grid structure 30 also extends over portions of isolation structure 24c.Grid structure 30 include gate dielectric layer 26 with gate conductor layer
28.The material of gate dielectric layer 26 may, for example, be advanced low-k materials or high dielectric constant material.Advanced low-k materials
Refer to the dielectric material that dielectric constant is less than 4, e.g. silica or silicon oxynitride.High dielectric constant material refers to dielectric constant
Dielectric material higher than 4, e.g. HfAlO, HfO2、Al2O3Or Si3N4.Forming method is, for example, thermal oxidation method or chemical gas
Phase sedimentation.Gate conductor layer 28 includes polysilicon, metal, metal silicide or its combination, and the method for formation is, for example, chemistry
Vapour deposition process.
Afterwards, in the side wall formation clearance wall 32 of grid structure 30.The material of clearance wall 32 is, for example, silica, silicon nitride
Or its combination.The method of formation can be initially formed spacer material layer, afterwards, then carry out anisotropic etching.
Thereafter, the source area 34 with the first conductivity type is formed in the well region 18 of the side of grid structure 30, and in grid
The drain region 36 with the first conductivity type is formed in the well region 12 of structure 30 (or isolation structure 24c) opposite side.Source area 34 with
The forming method of drain region 36 can form the mask layer (not illustrating) of patterning, then carry out ion implantation technology to be formed.Source
Polar region 34 is, for example, N-type heavily doped region with drain region 36.The doping that ion implantation technology is injected is, for example, phosphorus or arsenic, doping
Dosage be, for example, 1 × 1014/cm2To 9 × 1016/cm2, the energy of injection is, for example, 50KeV to 200KeV.
Thereafter, Fig. 2 F are refer to, the doped region 38 with the second conductivity type, and the shape in well region 16 are formed in well region 18
Into the doped region 40 with the second conductivity type.The mask layer that the forming method of doped region 38,40 can form patterning (is not painted
Show), then carry out ion implantation technology to be formed.Doped region 38,40 is, for example, p-type doped region.What ion implantation technology was injected
Doping e.g. boron, the dosage of doping is, for example, 1 × 1014/cm2To 9 × 1016/cm2, the energy of injection be, for example, 50K eV extremely
200KeV。
Followed by, Fig. 2 G are refer to, are formed on the substrate 10 online 60 in metal.In the present embodiment, online 60 in metal
Including dielectric layer 42, contact hole 44a~44e, conductor layer (or the first metal layer) 46a~46d, dielectric layer 48, interlayer hole 52a
~52b and conductor layer (or top metal level) 50a~50b, but be not limited.In one embodiment, online 60 in metal
Forming method comprise the following steps.Can be prior to forming dielectric layer 42 in substrate 10.Then, contact hole is formed in dielectric layer 42
44a~44e.Afterwards, conductor layer 46a~46d is formed on dielectric layer 42.Thereafter, on the substrate 10 formed dielectric layer 48, and in
Interlayer hole 52a~52b is formed in dielectric layer 48.Afterwards, formed on dielectric layer 48 conductor layer (or top metal level) 50a~
50b.The material of dielectric layer 42 and dielectric layer 48 is, for example, low Jie that silica, silicon nitride, silicon oxynitride or dielectric constant are less than 4
Permittivity material, the method for formation is, for example, chemical vapour deposition technique or spin-coating method.Contact hole 44a~44e and interlayer hole 52a~
52b material is, for example, aluminium, tungsten or its alloy, and the method for formation is, for example, chemical vapour deposition technique or physical vapour deposition (PVD)
Method.Contact hole 44a~44e forming method is, for example, that contact window, redeposited conductor material are first formed in dielectric layer 42
Then layer is etched back or chemical mechanical milling tech, is opened with removing the contact hole on dielectric layer 42 in contact window
Part conductor material layer outside mouthful.Interlayer hole 52a~52b forming method is similar to contact hole 44a~44e forming method,
Repeated no more in this.The method of conductor layer 46a~46d and conductor layer 50a~50b formation e.g. forms conductor material respectively
Layer, is then patterned with photoetching and etching technics again.Conductor material layer can be metal or metal alloy, e.g. aluminium, tungsten or
Its alloy.The forming method of conductor material layer is, for example, chemical vapour deposition technique or physical vaporous deposition.It is online in metal
60 forming method not limited to this.In another embodiment, online 60 can also be using the mode of damascene come shape in metal
Into.
After being formed online 60 in metal, it can further include and form protective layer (not illustrating) on the substrate 10, to cover
Conductor layer 50a~50b and dielectric layer 48.Protective layer can be individual layer or double-decker.The material of protective layer can be nothing
Machine material, organic material or its combination.Inorganic material is, for example, silica, silicon nitride or its combination.Organic material is, for example, poly-
Acid imide (PI).
Fig. 3 and Fig. 4 illustrates leakage current of three kinds of semiconductor elements in the test for carrying out electric static discharge protector 2kV respectively
Curve and breakdown voltage curve, the semiconductor element in respective turning area (such as Fig. 2 G the second area 200) place covering every
The width W2 of the part of conductor layer 50a from structure 24c is different.The width W2 of the semiconductor element can be respectively a, b,
C (wherein a<b<c).
Shown through experimental result：The width of the part of the conductor layer of covering isolation structure at source terminal more then leaks electricity
Stream is smaller, and breakdown voltage is bigger.In other words, as long as by the conductor layer for covering isolation structure at appropriate adjustment source terminal
Partial width, 700V of the invention semiconductor element can be by electric static discharge protector 2kV test.Actually should
Use, structure of the invention can apply to the super-pressure semiconductor element that operating voltage is 300V to 1000.
In summary it is described, in the present invention, according to the different zones in semiconductor element, leading for isolation structure will be covered
The width adjustment of the part of body layer is different in width.For example, by the curvature of source area is larger or conductor layer of corner (such as
Topmost metal layer) width increase, be larger than that the curvature of source area is smaller or straight line at conductor layer (such as the superiors' metal
Layer) width.In other words, increase source area curvature is larger or area of conductor layer (such as topmost metal layer) of corner can be with
Effectively dispersed high electric field at this.In this way, it is possible to provide height collapse electric field, low-leakage current and high electrostatic discharge protection
Ability semiconductor element.
Furthermore, the manufacture method of semiconductor element of the invention can define conductor layer (such as the superiors' metal through changing
Layer) pattern mask, you can to increase, curvature is larger or width of conductor layer (such as topmost metal layer) of corner
(or area), with effectively dispersed high electric field at this, reduction collapse electric field, and reduces leakage current, therefore can lift electrostatic
The ability of discharge prevention.
Although the present invention is disclosed above with embodiment, so it is not limited to the present invention, any art
Middle tool usually intellectual, without departing from the spirit and scope of the present invention, when a little change and retouching can be made, thus it is of the invention
Protection domain when depending on being defined that appended claims scope is defined.
Claims (10)
1. a kind of semiconductor element, including：
One has the source region of the first conductivity type and the drain region with first conductivity type, in a substrate；
One isolation structure, between the source area and the drain region；
In one grid structure, the substrate between the source area and the isolation structure；
One conductor layer, above the substrate, is at least extended to above the isolation structure, and be electrically connected with from above the source area
The source area,
Wherein, the substrate includes one first area and one second area, is more than in the curvature of the profile of the source area in secondth area
The curvature of the profile of the source area in firstth area, and the width of the part of the conductor layer for covering the isolation structure in secondth area
Width of the degree more than the part of the conductor layer for covering the isolation structure in firstth area.
2. semiconductor element according to claim 1, the wherein conductor layer are a topmost metal layer.
3. semiconductor element according to claim 1, the wherein semiconductor element include multiple linearity regions and multiple
It is located at firstth area one of in Turning regions, these linearity regions；Being located at one of in these Turning regions should
Secondth area.
4. semiconductor element according to claim 1, is further included：
A top layer with one second conductivity type, in the substrate below the isolation structure；And
A terraced layer with first conductivity type, between the top layer and the isolation structure.
5. semiconductor element according to claim 1, is further included：
One first well region with one second conductivity type, in the substrate, wherein the source area is located in first well region, and
The grid structure covering part first well region；
Doped region with second conductivity type is adjacent with the source area in first well region and common with the source area
Connect the conductor layer；And
One second well region with first conductivity type, in the substrate, wherein first well region and the drain region are located at
In second well region.
6. a kind of manufacture method of semiconductor element, including：
In forming an isolation structure in a substrate；
In forming a grid structure in the substrate；
In the substrate of the grid structure Yu the both sides of the isolation structure formed with one first conductivity type source region with
A drain region with first conductivity type, the wherein source area are close to the grid structure, and the drain region is close to the isolation structure；
A conductor layer is formed above the substrate, the conductor layer is extended to from above the source area above the isolation structure, and electricity
Property connects the source area,
Wherein the substrate includes one first area and one second area, is more than in the curvature of the profile of the source area in secondth area at this
The curvature of the profile of the source area in the firstth area, the width in the part of the conductor layer for covering the isolation structure in secondth area
More than the part of the conductor layer for covering the isolation structure in firstth area.
7. the manufacture method of semiconductor element according to claim 6, the wherein conductor layer are a topmost metal layer.
8. the manufacture method of semiconductor element according to claim 6, the wherein semiconductor element include multiple linearity sectors
It is located at firstth area one of in domain and multiple Turning regions, these linearity regions；In these Turning regions wherein
One of be located at secondth area.
9. the manufacture method of semiconductor element according to claim 6, is further included：
The top layer with one second conductivity type is formed in the substrate below the isolation structure；And
The terraced layer with first conductivity type is formed between the top layer and the isolation structure.
10. the manufacture method of semiconductor element according to claim 6, is further included：
One first well region with one second conductivity type is formed in the substrate, the wherein source area is located in first well region,
And the grid structure covering part first well region；
The doped region with second conductivity type is formed in first well region, the doped region is adjacent with the source area, and with
The source area connects the conductor layer jointly；And
One second well region with first conductivity type is formed in the substrate, wherein first well region and drain region is located at
In second well region.
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| US5981983A (en) * | 1996-09-18 | 1999-11-09 | Kabushiki Kaisha Toshiba | High voltage semiconductor device |
| TW201240085A (en) * | 2011-03-24 | 2012-10-01 | Macronix Int Co Ltd | Ultra-high voltage n-type-metal-oxide-semiconductor (UHV NMOS) device and methods of manufacturing the same |
| CN102867853A (en) * | 2011-07-08 | 2013-01-09 | 新唐科技股份有限公司 | Metal Oxide Half Field Effect Transistor |
| US8592901B1 (en) * | 2012-08-31 | 2013-11-26 | Nuvoton Technology Corporation | Metal oxide semiconductor field transistor and method of fabricating the same |
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| US5981983A (en) * | 1996-09-18 | 1999-11-09 | Kabushiki Kaisha Toshiba | High voltage semiconductor device |
| TW201240085A (en) * | 2011-03-24 | 2012-10-01 | Macronix Int Co Ltd | Ultra-high voltage n-type-metal-oxide-semiconductor (UHV NMOS) device and methods of manufacturing the same |
| CN102867853A (en) * | 2011-07-08 | 2013-01-09 | 新唐科技股份有限公司 | Metal Oxide Half Field Effect Transistor |
| US8592901B1 (en) * | 2012-08-31 | 2013-11-26 | Nuvoton Technology Corporation | Metal oxide semiconductor field transistor and method of fabricating the same |
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