CN108735796A - Semiconductor element - Google Patents
Semiconductor element Download PDFInfo
- Publication number
- CN108735796A CN108735796A CN201710276690.7A CN201710276690A CN108735796A CN 108735796 A CN108735796 A CN 108735796A CN 201710276690 A CN201710276690 A CN 201710276690A CN 108735796 A CN108735796 A CN 108735796A
- Authority
- CN
- China
- Prior art keywords
- region
- area
- doped region
- helical regions
- semiconductor element
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 39
- 238000002955 isolation Methods 0.000 claims abstract description 53
- 239000000758 substrate Substances 0.000 claims abstract description 47
- 230000002093 peripheral effect Effects 0.000 claims abstract description 10
- 239000004020 conductor Substances 0.000 claims description 49
- 238000005452 bending Methods 0.000 claims description 36
- 230000000977 initiatory effect Effects 0.000 claims description 9
- 239000010410 layer Substances 0.000 description 90
- 230000015556 catabolic process Effects 0.000 description 11
- 239000000463 material Substances 0.000 description 11
- 239000011229 interlayer Substances 0.000 description 7
- 229910052751 metal Inorganic materials 0.000 description 7
- 239000002184 metal Substances 0.000 description 7
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 6
- 230000005684 electric field Effects 0.000 description 4
- 238000005516 engineering process Methods 0.000 description 4
- 229910052581 Si3N4 Inorganic materials 0.000 description 3
- 238000005468 ion implantation Methods 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000000377 silicon dioxide Substances 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 239000003989 dielectric material Substances 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 230000005611 electricity Effects 0.000 description 2
- 239000011810 insulating material Substances 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 239000012071 phase Substances 0.000 description 2
- 230000009467 reduction Effects 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- 229910005540 GaP Inorganic materials 0.000 description 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- 229910003855 HfAlO Inorganic materials 0.000 description 1
- 229910000673 Indium arsenide Inorganic materials 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 229910003811 SiGeC Inorganic materials 0.000 description 1
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 1
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 229910052593 corundum Inorganic materials 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 239000007792 gaseous phase Substances 0.000 description 1
- 229910052732 germanium Inorganic materials 0.000 description 1
- CJNBYAVZURUTKZ-UHFFFAOYSA-N hafnium(IV) oxide Inorganic materials O=[Hf]=O CJNBYAVZURUTKZ-UHFFFAOYSA-N 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- RPQDHPTXJYYUPQ-UHFFFAOYSA-N indium arsenide Chemical compound [In]#[As] RPQDHPTXJYYUPQ-UHFFFAOYSA-N 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 229910003465 moissanite Inorganic materials 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 238000004062 sedimentation Methods 0.000 description 1
- 229910021332 silicide Inorganic materials 0.000 description 1
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 1
- 229910010271 silicon carbide Inorganic materials 0.000 description 1
- 125000006850 spacer group Chemical group 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- 229910001845 yogo sapphire Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
- H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/0843—Source or drain regions of field-effect devices
- H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
- H01L29/0852—Source or drain regions of field-effect devices of field-effect transistors with insulated gate of DMOS transistors
- H01L29/0856—Source regions
- H01L29/0865—Disposition
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/0843—Source or drain regions of field-effect devices
- H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
- H01L29/0852—Source or drain regions of field-effect devices of field-effect transistors with insulated gate of DMOS transistors
- H01L29/0856—Source regions
- H01L29/0869—Shape
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors
Abstract
A kind of semiconductor element comprising substrate, the first doped region, the second doped region, isolation structure and gate structure.Substrate includes the firstth area and the secondth area for being connected with the firstth area.First doped region has the first conductive type, in substrate and includes the first helical regions and boxed area.Second doped region has the first conductive type, in substrate and includes the second helical regions and peripheral region.Isolation structure is set between the first doped region and the second doped region.Gate structure is set between the first doped region and the second doped region and the substrate of covering part and partial isolation structure.
Description
Technical field
The present invention relates to a kind of semiconductor elements.
Background technology
Super-pressure element must have high breakdown voltage (breakdown voltage) and low unlatching electricity in operation
It hinders (on-state resistance), to reduce power attenuation.With the super-pressure of high breakdown voltage and low opening resistor member
Part can have lower power attenuation in application, and lower opening resistor then can make transistor have in saturation state
There is service speed of the higher drain current so as to increase super-pressure element.In current super-pressure element, it is frequently found
Source terminal has very big current gathering effect, thus becomes collapse point, causes the breakdown voltage of element to decline, and leak electricity
The case where stream, is very serious.
Based on this, pole needs a kind of super-pressure element with high breakdown voltage and/or low opening resistor at present, super to be promoted
The application of high voltage device.
Invention content
The embodiment of the present invention provides a kind of semiconductor element with high breakdown voltage and low opening resistor.
The present invention provides a kind of semiconductor element comprising substrate, the first doped region (D), the second doped region (S), isolation
Structure and gate structure.Substrate includes the firstth area and the secondth area for being connected with the firstth area.First doped region has the first conductive type,
In substrate and include the first helical regions and boxed area.First helical regions are in the firstth area.Boxed area exists
It is connect in secondth area and with the first helical regions.Second doped region has the first conductive type, in substrate and includes second
Helical regions and peripheral region.Second helical regions are in the firstth area and are sandwiched among the first helical regions.External zones
Domain at the edge in the firstth area and the secondth area and around the first helical regions and boxed area, and with the second helical regions
Connection.Isolation structure is set between the first doped region and the second doped region.Gate structure is set to the first doped region and second
Between doped region and the substrate of covering part and partial isolation structure.
In some embodiments of the invention, the shape of the first above-mentioned helical regions and the second helical regions is each
From for square spiral shape region, round spiral region or elliptical spiral shape region.
In some embodiments of the invention, the first above-mentioned helical regions include the multiple first straight lines being connected with each other
Region and multiple first bendings region, and the second helical regions include the multiple second straight line regions being connected with each other and multiple the
Two bending regions.First straight line region is arranged alternately with second straight line region, and the first bending region is handed over the second bending region
For setting.
In some embodiments of the invention, closest to the first straight of the first area edge in the first above-mentioned helical regions
Line region is connect with boxed area, and closest to the second straight line area in the firstth area and second area's interface in the second helical regions
Domain is connect with peripheral region.
In some embodiments of the invention, the first initial part of the first above-mentioned helical regions and the second helical form area
Second initial part in domain interlocks each other.
In some embodiments of the invention, the first initial part of the first above-mentioned helical regions it is U-shaped with inverted U its
One of, and the second initial part of the second helical regions is U-shaped wherein another with inverted U.
In some embodiments of the invention, the isolation structure in the firstth area includes center, double helix area and connection
Area, and isolation structure in the second region includes around area.Center is S-type and is located at the first of the first helical regions the starting
Between portion and the second initial part of the second helical regions.Double helix area is looped around the periphery of center.Bonding pad is L-shaped and connects
Connect center and double helix area.The first end of the first end connection center of bonding pad.The second end of bonding pad connects double helix
Second initiating terminal in area.The second end of the first initiating terminal connection center in double helix area.Around area around boxed area.It surround
The first end in the first end connection double helix area in area, and around the second end in the second end in area connection double helix area.
In some embodiments of the invention, above-mentioned semiconductor element further includes conductor layer.Conductor layer is set to grid
The top of structure and with the second doped region be electrically connected.Conductor layer at least extends to part isolation junction from above the second doped region
The top of structure.The width for the conductor layer being set on the second bending region of the second doped region, which is more than, is set to the second doped region
The width of conductor layer on second straight line region.
In some embodiments of the invention, above-mentioned semiconductor element further includes the first well region, the second well region, third trap
Area, third doped region and the 4th doped region.First well region has the second conductive type and is set in substrate, wherein the second doped region
It is set in the first well region and the first well region of gate structure covering part.Second well region has the first conductive type and is set to base
In bottom, wherein the first well region and the first doped region are set in the second well region.Third well region has the first conductive type and is set to
In substrate.Third well region is adjacent with the second well region.Third doped region has the second conductive type and is set in the first well region.Third
Doped region is adjacent with the second doped region.4th doped region has the second conductive type and is set in third well region.
In some embodiments of the invention, above-mentioned semiconductor element further includes top layer and terraced layer.Top layer has second
It conductivity type and is set in the substrate below isolation structure.Terraced layer there is the first conductive type and be set to isolation structure and top layer it
Between.
Based on above-mentioned, the present invention is laid out in by the second doped region that will be set in the firstth area of substrate by multiple second
Linearity region and the helical regions that are constituted of multiple second bendings region, thus can be promoted semiconductor element breakdown voltage and
Its opening resistor is reduced, to promote the electric current of semiconductor element under the size of limited semiconductor element.
To make the foregoing features and advantages of the present invention clearer and more comprehensible, following spy enumerates embodiment, and coordinates appended attached
Figure is described in detail below.
Description of the drawings
Fig. 1 is a kind of vertical view of semiconductor element of embodiment according to the present invention.
Fig. 2A and Fig. 2 B are the sectional view of the tangent line I-I ' and II-II ' of Fig. 1.
【Reference sign】
100：Semiconductor element
10：Substrate
10a：Firstth area
10b：Secondth area
12：First doped region
12a：First helical regions
12a_1：First initial part
12a_2：First middle part
12a_3：First end portion
12b：Boxed area
14：Second doped region
14a：Second helical regions
14a_1：First initial part
14a_2：First middle part
14a_3：First end portion
14b：Peripheral region
16a,16b,16c,16d：Isolation structure
16c1：Center
16c1_1：First end
16c1_2：Second end
16c2：Bonding pad
16c2_1：First end
16c2_2：Second end
16c3：Double helix area
16c3_s1：First initiating terminal
16c3_s2：Second initiating terminal
16c3_t1：First end
16c3_t2：Second end
16c4：Around area
16c4_1：First end
16c4_2：Second end
18：Gate structure
18a：Gate dielectric layer
18b：Gate conductor layer
20：Clearance wall
22,28：Dielectric layer
24a,24b,24c,24d,24e：Contact hole
26a,26b,26c,26d,30a,30b：Conductor layer
32a,32b：Interlayer hole
40：Metal interconnecting
42：First well region
44：Second well region
46：Third well region
48：Third doped region
50：4th doped region
52：Top layer
54：Terraced layer
L：Linearity region
L1：First straight line region
L2：Second straight line region
L3：Third linearity region
C：It is bent region
C1：First bending region
C2：Second bending region
C3：Third is bent region
D1：First direction
D2：Second direction
WC1,WC2,WD1,WD2：Width
OP1,OP2：Endpoint
I-I',II-II'：Line
Specific implementation mode
Fig. 1 is a kind of vertical view of semiconductor element of embodiment according to the present invention.Fig. 2A and Fig. 2 B are the tangent line I- of Fig. 1
The sectional view of I ' and II-II '.
Hereinafter, will be that p-type illustrates as an example, but the present invention is simultaneously by N-type and the second conductive type of the first conductive type
It is not limited.It will be understood by a person skilled in the art that can also p-type be replaced as the first conductive type, the second conductive type is replaced
At N-type.In some embodiments, p-type admixture is, for example, boron；N-type doping is, for example, phosphorus or arsenic.
Please refer to Fig. 1, Fig. 2A and Fig. 2 B, semiconductor element 100 of the invention can be a kind of high voltage device, super-pressure member
Part (operation voltage 300V to 1000V), power component, lateral diffusion metal oxide semiconductor (LDMOS) or insulated gate bipolar
Transistor npn npn (IGBT).In the present embodiment, semiconductor element 100 includes substrate 10, the first doped region 12, the second doped region
14, isolation structure 16a~16d with gate structure 18.
Substrate 10 is, for example, the semiconductor base with the second conductive type.For example, substrate 10 is P-type substrate.Partly lead
The material of body substrate is, for example, selected from the group being made of Si, Ge, SiGe, GaP, GaAs, SiC, SiGeC, InAs and InP
At least one of material.Substrate 10, which also can be for example, covers silicon insulation (SOI) substrate.Substrate 10 can be with the second conductive type
Epitaxial wafer, such as p-type extension (P-epi) wafer.In some embodiments, substrate 10 includes the first area 10a and second
Area 10b, and the second area 10b is connected with the first area 10a.In some embodiments, the first area 10a of substrate 10 be more than substrate 10
The second area 10b.The shape of the first area 10a and the second area 10b of substrate 10 are, for example, rectangle, circle, ellipse or combinations thereof.
In the present embodiment, the shape of the first area 10a and the second area 10b of substrate 10 are rectangle.One side of first area 10a and the secondth area
10b's trims on one side so that the first area 10a and the second area 10b are stepped.
First doped region 12 has the first conductive type and in substrate 10.First doped region 12 is, for example, N-type drain electrode
(N+).The doping concentration of first doped region 12 is, for example, 1 × 1014/cm2To 9 × 1016/cm2.First doped region 12 is, for example, first
It is formed by carrying out ion implantation technology again after forming patterned mask layer (not being painted) in substrate 10.In some implementations
In example, the first doped region 12 includes the first helical regions 12a and boxed area 12b.
First helical regions 12a is in the first area 10a.In the present embodiment, the first helical form in the first area 10a
Region 12a be from inside to outside around helical regions.In the present embodiment, the first helical regions 12a in the first area 10a
For the helical regions rotated in a clockwise direction, but invention is not limited thereto.For example, in the first area 10a
One helical regions 12a can also be the helical regions rotated in a counter-clockwise direction.First helical regions 12a can be for example
Square spiral shape region, round spiral region or elliptical spiral shape region etc..In the present embodiment, the first helical regions
12a is square spiral shape region.
In one embodiment, the first helical regions 12a may include the first initial part 12a_1, the first middle part 12a_2
With first end portion 12a_3.First initial part 12a_1 is for example at the center of the first area 10a.First initial part 12a_1 is for example
It is U-shaped or inverted U.First middle part 12a_2 connections the first initial part 12a_1 and first end portion 12a_3.Among first
Portion 12a_2 is, for example, the shape in hook, the Arabic numerals 7 fallen or Arabic numerals 7.First end portion 12a_3 be located at
Boxed area 12b connections in second area 10b.In one embodiment, first end portion 12a_3 is in the L-type or L-type fallen.At this
In Fig. 1 of embodiment, the first initial part 12a_1 is inverted u-shaped；First middle part 12a_2 is in the shape of the Arabic numerals 7 fallen；
First end portion 12a_3 is in the L-type fallen.
Boxed area 12b is connect in the second area 10b, and with the first helical regions 12a.Boxed area 12b can be in
Rectangle, circle, ellipse or combinations thereof.In addition, contact hole can be formed on the boxed area 12b being set in the second area 10b, with
High voltage is connected, therefore, in the present embodiment, the width WD2 for the boxed area 12b being set in the second area 10b, which can be more than, to be set
It is placed in the width WD1 of the first helical regions 12a in the first area 10a.
There is admixture, the conductivity type phase of the conductivity type of admixture and admixture in the first doped region 12 in second doped region 14
Together.In some embodiments, the second doped region 14 has the first conductive type and in substrate 10, wherein the second doped region 14
N-type source region (N+) in this way.The doping concentration of second doped region 14 is, for example, 1 × 1014/cm2To 9 × 1016/cm2.Second doping
Area 14 is, for example, to first pass through to carry out ion implantation technology again after forming patterned mask layer (not being painted) in substrate 10 and carry out shape
At.In some embodiments, the second doped region 14 includes the second helical regions 14a and peripheral region 14b.
Second helical regions 14a of the second doped region 14 is in the first area 10a and among being sandwiched in the first helical regions
12a.In the present embodiment, the second helical regions 14a in the first area 10a be from inside to outside around helical regions.?
In the present embodiment, the second helical regions 14a in the first area 10a is the helical regions rotated in a clockwise direction, but
Invention is not limited thereto.The second helical regions 14a in the first area 10a can also be the spiral shell rotated in a counter-clockwise direction
Revolve shape region.The direction of rotation of the second helical regions 14a in the first area 10a and the first spiral in the first area 10a
The direction of rotation of shape region 12a is identical.Second helical regions 14a can be for example square spiral shape region, round spiral area
Domain or elliptical spiral shape region etc..In the present embodiment, the second helical regions 14a is square spiral shape region.
In one embodiment, the second helical regions 14a may include the second initial part 14a_1, the second middle part 14a_2
With second end portion 14a_3.Second initial part 14a_1 is for example at the center of the first area 10a.Second initial part 14a_1 is for example
It is inverted u-shaped or U-shaped.In some embodiments, the first initial part 12a_1 of the first doped region 12 and the second doped region 14
Second initial part 14a_1 e.g. interlocks each other.In other words, in some embodiments, the first initial part 12a_1 is, for example, in U
Type；Second initial part 14a_1 is, for example, to be in and the U-shaped inverted U to interlock.In further embodiments, the first initial part 12a_1
Inverted U in this way；Second initial part 14a_1 is, for example, U-shaped in interlocking with inverted U.It is originated in the first initial part 12a_1 and second
The end of first initial part 12a_1 of the phase buckle of portion 14a_1 and the end of the second initial part 14a_1 are e.g. in rounded shape.
Second middle part 14a_2 connections the second initial part 14a_1 and second end portion 14a_3.Second middle part 14a_2 is, for example, in hook
The shape of shape, number 7 or the Arabic numerals 7 fallen.Second end portion 14a_3 is connect with peripheral region 14b.In an embodiment
In, second end portion 14a_3 has the shape of " one " word.In Fig. 1 of the present embodiment, the second initial part 14a_1 is inverted u-shaped；
Second middle part 14a_2 is in the shape of Arabic numerals 7；Second end portion 14a_3 is in " one " shape.
The peripheral region 14b of second doped region 14 is at the edge of the first area 10a and the second area 10b and around the first spiral
Shape region 12a and boxed area 12b, and connect with the first end portion 14a_3 of the second helical regions 14a.
On the other hand, in some embodiments, the first helical regions 12a includes multiple first to be connected with each other
Linearity region L1 and multiple first bending region C1, and the second helical regions 14a includes the multiple second straight lines being connected with each other
Region L2 and multiple second bending region C2.In the present embodiment, closest to the first area sides 10a in the first helical regions 12a
The first straight line region L1 that the D1 along a first direction of edge extends is connect with boxed area 12b, and in the second helical regions 14a
Closest to (the i.e. first ends second straight line region L2 of the first area 10a and second area's 10b interfaces extended along second direction D2
End 14a_3) it is connect with peripheral region 14b.In some embodiments, first direction D1 is orthogonal with second direction D2.First is straight
Line region L1 be, for example, be arranged alternately with second straight line region L2 and first bending region C1 be, for example, and second bending region C2
It is arranged alternately.In detail, first straight line region L1 is located between two linearity region L2 that (or second straight line region L2 is located at
Between two first straight line region L1)；Or first bending region C1 be located at (or second between two second bending region C2
It is bent region C2 to be located between two first bending region C1).In some embodiments, the area of multiple first straight line region L1
Summation be more than the summation of the area that multiple first are bent region C1, and the summation of the area of multiple second straight line region L2 is more than
The summation of the area of multiple second bending region C2.In detail, multiple first straight line region L1 are in the first helical regions 12a
In shared ratio be more than multiple first and be bent region C1 ratios shared in the first helical regions 12a, and multiple second
Ratio shared in the second helical regions 14a linearity region L2 is more than multiple second and is bent region C2 in the second helical form area
Shared ratio in the 14a of domain.Compared with the layout type in known semiconductor element, the present invention passes through above-mentioned layout type
Second of second doped region 14 with high electric field can be made to be bent the ratio reduction that region C2 accounts for entire second doped region 14, to carry
It rises 100 breakdown voltage of semiconductor element and reduces its opening resistor, to be promoted under the size of limited semiconductor element 100
The electric current of semiconductor element 100.
Isolation structure 16c is set between the first doped region 12 and the second doped region 14.In some embodiments, isolation junction
Structure 16c includes field oxide structure or isolation structure of shallow trench.Isolation structure 16c includes insulating materials.Insulating materials is, for example,
Undoped silica, silicon nitride or combinations thereof.Isolation structure 16c is, for example, to utilize field oxidation isolation method or shallow trench isolation method
And it is formed.In one embodiment, the isolation structure 16c in the first area 10a includes center 16c1, bonding pad from inside to outside
16c2 and double helix area 16c3.Isolation structure 16c in the second area 10b includes around area 16c4.
In the first area 10a, the center 16c1 of isolation structure 16c is located at the first starting of the first helical regions 12a
Between portion 12a_1 and the second initial part 14a_1 of the second helical regions 14a.In other words, in the first of the first doped region 12
In the embodiment for the U-shaped and inverted U that second initial part 14a_1 of beginning portion 12a_1 and the second doped region 14 e.g. interlocks each other,
Center 16c1 is for example S-type, is sandwiched in U-shaped between inverted U.Center 16c1 is for example including first end 16c1_1 and second
Hold 16c1_2.
In the bonding pad 16c2 connections center 16c1 and double helix area 16c3 of the first doped region 12.More specifically, even
Meet the first end 16c1_1 of the first end 16c2_1 connections center 16c1 of area 16c2；The second end 16c2_2 of bonding pad 16c2 connects
Meet double helix area 16c3.Bonding pad 16c2 is e.g. L-shaped.Double helix area 16c3 is looped around the periphery of center 16c1.?
The double helix area 16c3 of one doped region 12 for example mutually separated including two and concentric ring around spiral, by the of the first doped region 12
A part of one helical regions 12a is folded in wherein.Double helix area 16c3 has the first initiating terminal 16c3_s1, the second starting
Hold 16c3_s2, first end 16c3_t1 and second end 16c3_t2.The first initiating terminal 16c3_s1 of double helix area 16c3 connects
Meet the second end 16c1_2 of center 16c1；And the second initiating terminal 16c3_s2 connections bonding pad 16c2 of double helix area 16c3
Second end 16c2_2.In the first end 16c3_t1 and second end 16c3_t2 and the second area 10b of double helix area 16c3 every
From structure 16c connections.More specifically, the first end 16c3_t1 and second end 16c3_t2 and second of double helix area 16c3
The circular area 16c4 connections of area 10b.
In one embodiment, the isolation structure 16c in the second area 10b includes around area 16c4.It is surround around area 16c4
Boxed area 12b.Around the first end 16c3_t1 of the first end 16c4_1 connection double helixs area 16c3 of area 16c4, and it surround
The second end 16c3_t2 of the second end 16c4_2 connection double helixs area 16c3 of area 16c4.
On the other hand, in some embodiments, isolation structure 16c includes the multiple third linearity sectors being connected with each other
Domain L3 and multiple thirds are bent region C3.Third linearity region L3 is for example disposed on first straight line region L1 and second straight line area
Between the L2 of domain, and third bending region C3 is for example disposed between the bendings of the first bending region C1 and second region C2.One
In a little embodiments, the summation of the area of multiple third linearity region L3 is more than the summation of the area of multiple thirds bending region C3.
Generally speaking, semiconductor element 100 can be for example is made of multiple linearity region L and multiple bending region C.Directly
Line region L includes multiple first straight line region L1, multiple second straight line region L2 and multiple third linearity region L3, and buckled zone
Domain L includes multiple first bending region C1, multiple second bending region C2 and multiple thirds bending region C3.
Gate structure 18 is set between the first doped region 12 and the second doped region 14 and the substrate 10 of covering part and portion
The isolation structure 16c divided.In some embodiments, gate structure 18 include gate dielectric layer 18a with gate conductor layer 18b.Grid
Dielectric layer 18a is located in substrate 10, and material is, for example, advanced low-k materials or high dielectric constant material.Low-k
Material refers to the dielectric material that dielectric constant is less than 4, is, for example, silica or silicon oxynitride.High dielectric constant material refers to being situated between
Electric constant is higher than 4 dielectric material, is, for example, HfAlO, HfO2、Al2O3Or Si3N4.Gate dielectric layer 18a is, for example, to pass through hot oxygen
Change method or chemical vapour deposition technique are formed.Gate conductor layer 18b is located on gate dielectric layer 18a and partial isolation structure 16c,
Its material is, for example, polysilicon, metal, metal silicide or combinations thereof etc..Gate conductor layer 18b is, for example, to pass through chemical gaseous phase
Sedimentation is formed.In some embodiments, it is provided with clearance wall 20 on the side wall of gate structure 18.The material of clearance wall 20 is for example
It is silica, silicon nitride or combinations thereof.Clearance wall 20 be, for example, by being initially formed spacer material layer after, then by clearance wall
Material layer carries out anisotropic etching to be formed.
Please continue to refer to Fig. 1, Fig. 2A and Fig. 2 B, semiconductor element 100 of the invention can also further include the first well region 42,
Two well regions 44, third well region 46, third doped region 48, the 4th doped region 50, top layer 52, terraced layer 54 and conductor layer 30a.
First well region 42 is for example with the second conductive type and in substrate 10.In some embodiments, the second doped region
14 are set in the first well region 42, and the first well region 42 of 18 covering part of gate structure.Second well region 44 is for example with first
Conductivity type and in the substrate 10.Second well region 44 is, for example, N traps.In some embodiments, the second well region 44 is high pressure N traps
(HVNW).In some embodiments, the first well region 42 and the first doped region 12 are set in the second well region 44.Third well region 46
Such as there is the second conductive type.In some embodiments, third well region 46 is located at adjacent with the second well region 44 in substrate 10.Third trap
Area 46 is, for example, p-well.
Third doped region 48 and the 4th doped region 50 have the second conductive type, third doped region 48 and the 4th doped region 50
The dense doped region of p-type (P+) in this way.Third doped region 48 is located at the first well region 42 between isolation structure 16b and the second doped region 14
In.4th doped region 50 is located among third well region 46.The doping concentration of third doped region 48 and the 4th doped region 50 is, for example, 1
×1014/cm2To 9 × 1016/cm2.In addition, the third well region 46 of isolation structure 16a covering parts.Isolation structure 16b coverings are another
The third well region 46 of a part, and extend over part the first well region 42 and the second well region 44.Isolation structure 16c and isolation junction
Structure 16d is located on the first well region of part 42 of 44 side of the second well region.Isolation structure 16c is located at the second well region 44 and isolation structure
Between 16d.
It is, for example, p-type top layer (P-Top) that top layer 52, which has the second conductive type, top layer 52,.Top layer 52 is located at isolation structure 16c
In second well region 44 of lower section, to promote breakdown voltage.It is, for example, N-type ladder layer that terraced layer 54, which has the first conductive type, terraced layer 54,
(N-grade).Terraced layer 54 is between top layer 52 and isolation structure 16c, to reduce conducting resistance.In some embodiments,
The doping concentration of terraced layer 54 is not less than the doping concentration of well region 42.The doping concentration of top layer 52 is, for example, 1 × 1011/cm2To 9 ×
1013/cm2.The doping concentration of terraced layer 54 is, for example, 1 × 1011/cm2To 9 × 1013/cm2.Top layer 52 and terraced layer 54 are, for example, to pass through
Ion implantation technology is formed.
Conductor layer 30a is set to the top of gate structure 18 and is electrically connected with the second doped region 14.In some embodiments
In, component that conductor layer 30a includes by metal interconnecting 40.In detail, metal interconnecting 40 includes dielectric layer 22, contact
Window 24a~24e, conductor layer 26a~26d, dielectric layer 28, interlayer hole 32a, 32b and conductor layer 30a, 30b, but not as
Limit.Dielectric layer 22 is set in substrate 10.Contact hole 24a~24e is set in dielectric layer 22.Conductor layer 26a~26d is set to
On dielectric layer 22.Conductor layer 26a is electrically connected by contact hole 24a with the 4th doped region 50.Conductor layer 26b passes through contact hole
24b and be electrically connected with third doped region 48, and conductor layer 26b is electrically connected by contact hole 24c with the second doped region 14
It connects.Conductor layer 26c is electrically connected by contact hole 24d and gate conductor layer 18b.Conductor layer 26d passes through contact hole 24e and first
Doped region 12 is electrically connected.Dielectric layer 28 is set on dielectric layer 22.Interlayer hole 32a, 32b are set in dielectric layer 28.
Conductor layer 30a, 30b is set on dielectric layer 28.In other words, conductor layer 30a, 30b can be metal interconnecting 40
Topmost metal layer.Conductor layer 30a and conductor layer 30b each by interlayer hole 32a and interlayer hole 32b and with conductor layer 26b
And conductor layer 26d is electrically connected.The width of conductor layer 30a at least prolongs from above the second doped region 14 (or self-isolation structure 16b)
It extends to above portions of isolation structure 16c, and is mixed by interlayer hole 32a, conductor layer 26b and contact hole 24c with being electrically connected second
Miscellaneous area 14.Conductor layer 30b is at least extended to above portions of isolation structure 16d from above portions of isolation structure 16c, and passes through interlayer
Window 32b, conductor layer 26d and contact hole 24e are to be electrically connected the first doped region 12.
Referring to Fig. 1, Fig. 2A and Fig. 2 B, the width of the conductor layer 30a on different location can be identical or not
Together.For example, Fig. 1 and 2A are please referred to, the covering isolation structure being set on the second straight line region L2 of the second doped region 14
The width WC1 of the conductor layer 30a of the part of 16c is that conductor layer 30a corresponds to the endpoint OP1 place of isolation structure 16c to conductor layer
The distance at the edge (proximity conductor layer 30b) of 30a.The covering isolation being set on the second bending region C2 of the second doped region 14
The width WC2 of the part of the conductor layer 30a of structure 16c is that conductor layer 30a corresponds to the endpoint OP2 place of isolation structure 16c to leading
The distance at the edge (proximity conductor layer 50b) of body layer 30a.The end that above-mentioned endpoint OP1, OP2 is isolation structure 16c contacts grid
The point of pole dielectric layer 18a.In the present embodiment, it is set to the part of the covering isolation structure 16c on the second bending region C2
The width WC2 of conductor layer 30b is more than the conductor layer of the part for the covering isolation structure 16c being set on the L2 of second straight line region
The width WC1 (i.e. WC2 > WC1) of 30a.In some embodiments, width WC2 is 1 times to 5 times of width WC1.
In detail, from the point of view of the vertical view of Fig. 1, the curvature of the profile of the second doped region 14 from second straight line region L2 extremely
Second bending region C2 is incremented by, and therefore, covers the width of the conductor layer 30a of the second doped region 14 from second straight line region L2 to the
Two bending region C2 are also gradually smoothly incremented by, and conductor layer 30a is made to have smooth profile whereby, so as to effectively uniform point
Dissipate the high electric field in the second bending region C1 of the second doped region 14.
In conclusion the present invention by the second doped region (source area) that will be set in the firstth area of substrate be laid out in by
Multiple second straight line regions and the helical regions that are constituted of multiple second bendings region, thus can reduce with high electric field the
Second bending region of two doped regions accounts for the ratio of entire second doped region, to promote breakdown voltage and the reduction of semiconductor element
Its opening resistor, to promote the electric current of semiconductor element under the size of limited semiconductor element.Furthermore by making conductor
The width of layer can effectively be dispersed in second and mix as the curvature in the second bending region of the second doped region increases and increases
High electric field in the second bending region in miscellaneous area, can make semiconductor element have high breakdown voltage, low-leakage current and height whereby
The characteristic of electrostatic discharge (ESD) protection.
Particular embodiments described above has carried out further in detail the purpose of the present invention, technical solution and advantageous effect
Describe in detail bright, it should be understood that the above is only a specific embodiment of the present invention, is not intended to restrict the invention, it is all
Within the spirit and principles in the present invention, any modification, equivalent substitution, improvement and etc. done should be included in the protection of the present invention
Within the scope of.
Claims (10)
1. a kind of semiconductor element, including：
Substrate, including the firstth area and the secondth area for being connected with firstth area；
First doped region (D) has the first conductive type, is located in the substrate, including：
First helical regions, in firstth area；
Boxed area is connect in secondth area with first helical regions；
Second doped region (S) has the first conductive type, is located in the substrate, including：
Second helical regions are sandwiched in firstth area among first helical regions；
Peripheral region, the edge in firstth area and secondth area, around first helical regions and described piece
Shape region, and connect with second helical regions；
Isolation structure is set between first doped region and second doped region；And
Gate structure, is set between first doped region and second doped region and the substrate of covering part and portion
The isolation structure divided.
2. semiconductor element as described in claim 1, wherein first helical regions and second helical form area
The shape in domain is respectively square spiral shape region, round spiral region or elliptical spiral shape region.
3. semiconductor element as described in claim 1, wherein：
First helical regions include the multiple first straight line regions being connected with each other and multiple first bendings region；And
Second helical regions include that the multiple second straight line regions being connected with each other and multiple second are bent region,
Wherein the multiple first straight line region is arranged alternately with the multiple second straight line region；The multiple first buckled zone
Domain is arranged alternately with the multiple second bending region.
4. semiconductor element as claimed in claim 3, wherein：
Closest to the first straight line region of first area edge and the boxed area in first helical regions
Connection；And
Closest to the second straight line region in firstth area and secondth area interface in second helical regions
It is connect with the peripheral region.
5. semiconductor element as claimed in claim 3, wherein the first initial part of first helical regions and described the
Second initial part of two helical regions interlocks each other.
6. semiconductor element as claimed in claim 5, wherein first initial part of first helical regions is U-shaped
One of with inverted U；Second initial part of second helical regions is U-shaped wherein another with inverted U.
7. semiconductor element as claimed in claim 5, wherein：
The isolation structure in firstth area includes：
Center, it is S-type, it is located at first initial part of first helical regions and second helical regions
Between second initial part；
Double helix area is looped around the periphery of the center；And
Bonding pad, it is L-shaped, the center and the double helix area are connected,
The first end of the wherein described bonding pad connects the first end of the center, and the second end connection of the bonding pad is described double
First initiating terminal of the second initiating terminal of helical region, the double helix area connects the second end of the center；And
The isolation structure in secondth area includes：
Around area, around the boxed area, the first end around area connects the first end in double helix area, described
Second end around area connects the second end in the double helix area.
8. semiconductor element as claimed in claim 3 further includes conductor layer, be set to the top of the gate structure and with institute
State the electric connection of the second doped region, wherein the conductor layer at least extended to from above second doped region part it is described every
Top from structure, be provided in second doped region it is described second bending region on the conductor layer width it is big
In the width for the conductor layer being set on the second straight line region of second doped region.
9. semiconductor element as described in claim 1, further includes：
First well region has the second conductive type, is set in the substrate, wherein second doped region is set to described first
In well region, and first well region of the gate structure covering part；
Second well region has the first conductive type, is set in the substrate, wherein first well region is mixed with described first
Miscellaneous area is set in second well region；
Third well region has the first conductive type, is set in the substrate and adjacent with second well region；
Third doped region has the second conductive type, is set in first well region and adjacent with second doped region；
And
4th doped region has the second conductive type, is set in the third well region.
10. semiconductor element as described in claim 1, further includes：
Top layer has the second conductive type, is set in the substrate below the isolation structure；And
Terraced layer has the first conductive type, is set between the isolation structure and the top layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710276690.7A CN108735796A (en) | 2017-04-25 | 2017-04-25 | Semiconductor element |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710276690.7A CN108735796A (en) | 2017-04-25 | 2017-04-25 | Semiconductor element |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN108735796A true CN108735796A (en) | 2018-11-02 |
Family
ID=63934450
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201710276690.7A Pending CN108735796A (en) | 2017-04-25 | 2017-04-25 | Semiconductor element |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN108735796A (en) |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20080079072A1 (en) * | 2006-09-29 | 2008-04-03 | Leadtrend Technology Corp. | High-voltage semiconductor device structure |
| CN102867853A (en) * | 2011-07-08 | 2013-01-09 | 新唐科技股份有限公司 | Metal Oxide Half Field Effect Transistor |
| CN104810383A (en) * | 2014-01-28 | 2015-07-29 | 旺宏电子股份有限公司 | Semiconductor element and manufacturing method thereof |
-
2017
- 2017-04-25 CN CN201710276690.7A patent/CN108735796A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20080079072A1 (en) * | 2006-09-29 | 2008-04-03 | Leadtrend Technology Corp. | High-voltage semiconductor device structure |
| CN102867853A (en) * | 2011-07-08 | 2013-01-09 | 新唐科技股份有限公司 | Metal Oxide Half Field Effect Transistor |
| CN104810383A (en) * | 2014-01-28 | 2015-07-29 | 旺宏电子股份有限公司 | Semiconductor element and manufacturing method thereof |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US11791409B2 (en) | High voltage semiconductor device and manufacturing method of high voltage semiconductor device | |
| TWI274419B (en) | High-voltage MOS device | |
| US9076837B2 (en) | Lateral insulated gate bipolar transistor structure with low parasitic BJT gain and stable threshold voltage | |
| US11764216B2 (en) | Semiconductor device with controllable channel length and manufacturing method thereof | |
| US7521741B2 (en) | Shielding structures for preventing leakages in high voltage MOS devices | |
| TW202006952A (en) | Laterally diffused metal oxide semiconductor device and manufacturing method thereof | |
| TW201347180A (en) | Trench power MOSFET and fabrication method thereof | |
| US11855201B2 (en) | Semiconductor structure | |
| US10930776B2 (en) | High voltage LDMOS transistor and methods for manufacturing the same | |
| CN107275401B (en) | Semiconductor device and method for manufacturing semiconductor device | |
| CN107799580B (en) | Semiconductor device with a plurality of transistors | |
| CN115083914A (en) | LDMOS having improved breakdown performance | |
| CN108735796A (en) | Semiconductor element | |
| US9954118B2 (en) | Method of producing a high-voltage semiconductor drift device | |
| US9035386B2 (en) | Semiconductor structure and method for manufacturing the same | |
| JP6549972B2 (en) | Semiconductor device and method of manufacturing the same | |
| CN105374854B (en) | Semiconductor device and method for manufacturing semiconductor device | |
| TWI683438B (en) | Semiconductor device | |
| CN104810383B (en) | Semiconductor element and its manufacture method | |
| USRE44430E1 (en) | PMOS depletable drain extension made from NMOS dual depletable drain extensions | |
| TWI436483B (en) | Semiconductor device | |
| CN111463258A (en) | Transistor element | |
| US9070766B1 (en) | Semiconductor device and method of forming the same | |
| US20190355809A1 (en) | Semiconductor device | |
| CN117410317A (en) | High voltage device with multiple field plates and method of manufacturing the same |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| WD01 | Invention patent application deemed withdrawn after publication | ||
| WD01 | Invention patent application deemed withdrawn after publication |
Application publication date: 20181102 |