JP6549972B2 - Semiconductor device and method of manufacturing the same - Google Patents

Description

  The present invention relates to a semiconductor device and a method of manufacturing the same.

  As background art of this technical field, JP-A-2006-303324 (patent document 1), JP-A-10-242458 (patent document 2), JP-A 2014-063949 (patent document 3) and JP-A 2008 No. 004872 gazette (patent documents 4).

  Japanese Patent Laid-Open No. 2006-303324 (Patent Document 1) describes a semiconductor device in which a first n-type impurity diffusion layer is formed in a region between adjacent p-type wells.

  In Japanese Patent Laid-Open No. 10-242458 (Patent Document 2), the side surface of the base region has an impurity region of the first conductivity type doped with a higher concentration than the drift region, and in the drift region below the gate electrode. The document describes a semiconductor device in which a first conductivity type region having an impurity concentration lower than that of the impurity region is formed.

  In JP-A-2014-063949 (Patent Document 3), a second portion in which a JFET region is arranged from a first depth position to a second depth position shallower than the first depth position , And a third portion arranged from the second depth position to the main surface, and the third impurity concentration of the third portion is less than the second impurity concentration of the second portion A silicon carbide semiconductor device is described.

  JP 2008-004872 A (patent document 4) relates to a first semiconductor region of a first conductivity type having a first portion and a second portion protruding from the first portion, wherein the second portion is a second semiconductor portion. The width of the lower surface is smaller than the width of the upper surface, and the first semiconductor region provided with the recess on the upper surface of the second portion and the recess are provided, and the width is smaller than the width of the upper surface of the second portion A semiconductor device is described which comprises a second semiconductor region of a second conductivity type.

JP, 2006-303324, A JP 10-242458 A JP, 2014-063949, A JP, 2008-004872, A

  For energy saving of the power semiconductor device, reduction of the loss of the switching element is desired. Since the loss of the switching element is mainly determined by the characteristic on resistance, it is necessary to maintain the breakdown voltage and to lower the characteristic on resistance. Therefore, in recent years, a MOSFET (Metal Oxide Semiconductor Field Effect Transistor) using a wide gap semiconductor material such as silicon carbide (SiC) has attracted attention as a switching element capable of reducing the characteristic on-resistance.

  In the on state, the channel region becomes conductive by applying the on voltage to the gate electrode, and electrons flow from the JFET (Junction Field Effect Transistor) region sandwiched between the adjacent p-type well regions into the n-type drift layer. As a result, the reduction of the characteristic on-resistance is realized. Further, in the off state, a depletion layer spreads from the p-type well region to the n-type drift layer, and a high breakdown voltage is realized by supporting the voltage by this depletion layer.

  By the way, in order to reduce the characteristic on-resistance, it is effective to reduce the resistance of the JFET region (hereinafter referred to as the JFET resistance). Since the JFET resistance depends on the resistance of the bottleneck portion sandwiched by the depletion layer formed in the JFET region, the JFET resistance decreases as the width of the JFET region (hereinafter referred to as the JFET width) becomes wider.

  However, in the off state, the magnitude of the electric field applied to the gate insulating film under the gate electrode has a maximum value at the central portion of the JFET region, and the value increases as the JFET width becomes wider. Therefore, there is a trade-off between the characteristic on resistance and the gate insulating film electric field.

  In order to solve the above problems, a semiconductor device according to the present invention has a first width from an end side surface of a p-type well region in a JFET region sandwiched between adjacent p-type well regions, and an n-type epitaxial A first depth from the surface of the layer to form a first n-type impurity region, having a second width from an end side surface of the p-type well region, and a second depth from a bottom surface of the first n-type impurity region The second n-type impurity region is formed. Furthermore, the third n-type impurity region is formed across the space between the adjacent p-type well regions having a third depth from the lower surface of the second n-type impurity region. The first width and the second width are smaller than 1/2 of the width of the JFET region, and the impurity concentration of the central portion in the surface layer portion of the JFET region is that of the first, second and third n-type impurity regions. Lower than impurity concentration.

  According to the present invention, it is possible to provide a semiconductor device capable of suppressing the increase in the characteristic on-resistance and reducing the electric field of the gate insulating film.

  Problems, configurations, and effects other than those described above will be apparent from the description of the embodiments below.

It is principal part sectional drawing which shows the silicon carbide semiconductor device by a present Example. It is principal part sectional drawing which shows the silicon carbide semiconductor device by the comparative example which this inventor examined. It is a graph which shows an example of the calculation result of the n-type impurity concentration profile of the depth direction from the surface of the epitaxial layer in the center part of JFET area | region. It is a graph which shows an example of the calculation result of the gate insulating film electric field along the interface of a gate insulating film and an epitaxial layer. It is a graph which shows an example of the calculation result of the relationship between a characteristic on-resistance and a gate insulating film electric field, and JFET width (Lj). It is a graph which shows an example of the calculation result of the relationship between a characteristic on-resistance increase rate, the gate insulating film electric field increase rate, and the width | variety (W) of impurity region. It is a graph which shows an example of the calculation result of the relationship between a characteristic on-resistance increase rate, the gate insulating film electric field increase rate, and the depth (d) of an impurity area | region. FIG. 14 is a main-portion cross-sectional view showing an example of a manufacturing process of the silicon carbide semiconductor device according to the present embodiment. FIG. 9 is a main-portion cross-sectional view showing the manufacturing process of the silicon carbide semiconductor device continued from FIG. 8; FIG. 10 is a cross-sectional view of a main portion showing the manufacturing process of the silicon carbide semiconductor device continued from FIG. 9; FIG. 11 is a main-portion cross-sectional view showing the manufacturing process of the silicon carbide semiconductor device continued from FIG. 10; FIG. 12 is a main-portion cross-sectional view showing the manufacturing process of the silicon carbide semiconductor device continued from FIG. 11; FIG. 13 is a main-portion cross-sectional view showing the manufacturing process of the silicon carbide semiconductor device continued from FIG. 12; FIG. 14 is a main-portion cross-sectional view showing the manufacturing process of the silicon carbide semiconductor device continued from FIG. 13; FIG. 15 is a main-portion cross-sectional view showing the manufacturing process of the silicon carbide semiconductor device continued from FIG. 14; FIG. 16 is a cross-sectional view of a main portion illustrating the manufacturing process of the silicon carbide semiconductor device continued from FIG. 15; FIG. 17 is a main-portion cross-sectional view showing the manufacturing process of the silicon carbide semiconductor device continued from FIG. 16; FIG. 18 is a main-portion cross-sectional view showing the manufacturing process of the silicon carbide semiconductor device continued from FIG. 17;

  In the following embodiments, when it is necessary for the sake of convenience, it will be described by dividing into a plurality of sections or embodiments, but unless specifically stated otherwise, they are not unrelated to each other, one is the other And some or all of the variations, details, and supplementary explanations.

  Further, in the following embodiments, when referring to the number of elements (including the number, numerical value, quantity, range, etc.), it is particularly pronounced and clearly limited to a specific number in principle. It is not limited to the specific number except for the number, and may be more or less than the specific number.

  Further, in the following embodiments, the constituent elements (including element steps and the like) are not necessarily essential except in the case where they are particularly clearly shown and where they are considered to be obviously essential in principle. Needless to say.

  In addition, when we say “consists of A”, “consists of A”, “have A”, and “include A”, except for those cases where it is clearly stated that it is only that element, etc., the other elements are excluded. It goes without saying that it is not something to do. Similarly, in the following embodiments, when referring to the shapes, positional relationships and the like of components etc., the shapes thereof are substantially the same unless particularly clearly stated and where it is apparently clearly not so in principle. It is assumed that it includes things that are similar or similar to etc. The same applies to the above numerical values and ranges.

  Further, in the drawings for explaining the following embodiments, the size of each part does not correspond to that of the actual device, and a specific part may be displayed relatively large in order to make the drawing easy to understand. . Moreover, what has the same function attaches | subjects the code | symbol same as a principle, and the description of the repetition is abbreviate | omitted.

  Hereinafter, the present embodiment will be described in detail based on the drawings.

<< Structure of Silicon Carbide Semiconductor Device >>
The structure of the silicon carbide semiconductor device according to the present embodiment will be described with reference to FIG. FIG. 1 is a sectional view of an essential part showing a silicon carbide semiconductor device according to the present embodiment. The silicon carbide semiconductor device is a MOSFET of a planar DMOS (Double diffused Metal Oxide Semiconductor) structure.

As shown in FIG. 1, silicon carbide (SiC) having an impurity concentration lower than that of n ⁺ -type SiC substrate 10 is formed on the surface (first main surface) of n ⁺ -type SiC substrate 10 made of silicon carbide (SiC) An n ⁻ -type epitaxial layer 11 is formed. The thickness of the n ⁻ -type epitaxial layer 11 is, for example, about 30 μm.

In the n ⁻ -type epitaxial layer 11, a plurality of p-type well regions (p-type body regions) 12 are formed spaced apart from each other with a predetermined depth from the surface of the n ⁻ -type epitaxial layer 11 . The depth from the surface of the n ⁻ -type epitaxial layer 11 of the p-type well region 12 is, for example, about 2.0 μm.

In the p-type well region 12, an n ⁺ -type source region 14 is formed with a predetermined depth from the surface of the n ⁻ -type epitaxial layer 11. The n ⁺ -type source region 14 is formed in the p-type well region 12 at a distance from the end side surface of the p-type well region 12, and from the surface of the n ⁻ -type epitaxial layer 11 of the n ⁺ -type source region 14. The depth is, for example, about 0.2 to 0.3 μm.

Further, ap ⁺ -type well contact region (p ⁺ -type potential fixing region) 13 for fixing the potential of the p-type well region 12 is formed. The depth from the surface of the n ⁻ -type epitaxial layer 11 of the p ⁺ -type well contact region 13 is, for example, about 0.3 to 0.4 μm.

A region sandwiched between the p-type well regions 12 adjacent to each other is a portion functioning as a JFET region (doping region) 15. Also, the end side surface of p-type well region 12 (the interface between JFET region 15 and p-type well region 12) and the end side surface of n ⁺ -type source region 14 (p-type well region 12 and n ⁺ -type source region 14) The p-type well region 12 located between the and the interface) is a portion functioning as a channel region CH.

In the n ⁻ -type epitaxial layer 11, the region excluding the p-type well region 12 and the JFET region 15 is a region that functions as a drift layer serving to secure a withstand voltage. In addition, the n ⁺ -type SiC substrate 10 is a region that functions as a drain layer.

In JFET region 15, first n-type impurity region 17 is formed having a predetermined depth from the surface of n ⁻ -type epitaxial layer 11 and a width W from the end side surface of p-type well region 12. ing. The width W is set shorter than 1⁄2 of the width of the JFET region 15 (the distance between the adjacent p-type well regions 12). The first n-type impurity region 17 has a function of adjusting the threshold voltage.

In JFET region 15, second n-type impurity region 16 a has a predetermined depth from the lower surface of first n-type impurity region 17 and a width W from the end side surface of p-type well region 12. It is formed. The second n-type impurity region 16 a has a function of reducing the resistance of the JFET region 15 by suppressing the extension of the depletion layer from the p-type well region 12 to the JFET region 15. The depth d of the second n-type impurity region 16 a from the surface of the n ⁻ -type epitaxial layer 11 is a position where the impurity concentration is 1 × 10 ¹⁶ to 2 × 10 ¹⁶ cm ⁻³ . In the present embodiment, the width of the first n-type impurity region 17 and the width of the second n-type impurity region 16a are the same width W. However, the widths do not necessarily have to be the same width W. Good.

  Further, in the JFET region 15, a third n-type impurity region 16b having a predetermined depth from the lower surface of the second n-type impurity region 16a and crossing between adjacent p-type well regions 12 is formed. . The third n-type impurity region 16 b suppresses the extension of the depletion layer from the p-type well region 12 to the JFET region 15, and the currents flowing from the second n-type impurity regions 16 a on both sides into the JFET region 15 merge and flow. It has a function to reduce the JFET resistance of the bottleneck portion. The impurity concentration of the second n-type impurity region 16a and the impurity concentration of the third n-type impurity region 16b may be the same.

Therefore, the surface layer portion of JFET region 15 has a depth d from the surface of n ^-- type epitaxial layer 11 in the central portion, and the impurity concentration of first n-type impurity region 17 and second n-type impurity region 16a A low impurity concentration region having a low impurity concentration is formed. In this embodiment, this low impurity concentration region has the same impurity concentration as the impurity concentration of the n ⁻ -type epitaxial layer 11.

Note that “ ⁻ ” and “ ⁺ ” are symbols indicating relative impurity concentration of n type or p type conductivity type, and for example, n type in the order of “n ⁻ ”, “n” and “n ⁺ ” The impurity concentration of the impurity increases, and the impurity concentration of the p-type impurity increases in the order of “p ⁻ ”, “p”, and “p ⁺ ”.

The preferable range of the impurity concentration of the n ⁺ -type SiC substrate 10 is, for example, about 2 × 10 ¹⁸ cm ⁻³ , and the preferable range of the impurity concentration of the n ⁻ -type epitaxial layer 11 is, for example, about 3 × 10 ¹⁵ cm ⁻³ . The preferable range of the impurity concentration of the p-type well region 12 is, for example, about 3 × 10 ¹⁶ to 1 × 10 ¹⁸ cm ⁻³ , and the preferable range of the impurity concentration of the n ⁺ -type source region 14 is, for example, 1 × 10 ¹⁸ to A preferable range of the impurity concentration of about 1 × 10 ²⁰ cm ⁻³ and the p ⁺ -type well contact region 13 is, for example, about 1 × 10 ¹⁸ to 1 × 10 ²⁰ cm ⁻³ . The preferable range of the impurity concentration of the first n-type impurity region 17 is determined by the threshold voltage, but is higher than the impurity concentration of the second n-type impurity region 16a, for example, 3 × 10 ^{16 to} 5 × 10 ¹⁶ cm ^−3. It is an extent. The preferable range of the impurity concentration of the second n-type impurity region 16a is, for example, about 1 × 10 ¹⁶ to 2 × 10 ¹⁶ cm ⁻³ , and the preferable range of the impurity concentration of the third n-type impurity region 16b is, for example, 1 × 10 ¹⁶ It is about ^-3 * 10 < ¹⁶ > cm < ^-3 >.

A gate insulating film 18 is formed on the channel region CH, and a gate electrode 19 is formed on the gate insulating film 18. In practice, the gate electrode 19 is disposed across the n ⁺ -type source region 14, the p-type well region 12 and the JFET region 15.

Gate insulating film 18 and gate electrode 19 are covered with interlayer insulating film 20. At the bottom of the opening CN formed in the interlayer insulating film 20, a part of the n ⁺ -type source region 14 and the p ⁺ -type well contact region 13 are exposed. A metal silicide layer may be formed on part of the n ⁺ -type source region 14 exposed on the bottom of the opening CN and the surface of the p ⁺ -type well contact region 13.

Further, a part of the n ⁺ -type source region 14 and the p ⁺ -type well contact region 13 are electrically connected to the source wiring electrode 21. Further, the back surface (second main surface) of the n ⁺ -type SiC substrate 10 is electrically connected to the drain wiring electrode 22. Moreover, although illustration is abbreviate | omitted, the gate electrode 19 is electrically connected to the electrode for gate wiring similarly. A source potential is applied to the source line electrode 21 from the outside, a drain potential is applied to the drain line electrode 22 from the outside, and a gate potential is applied to the gate line electrode from the outside.

  FIG. 2 is a sectional view of an essential part showing a silicon carbide semiconductor device according to a comparative example examined by the inventor.

As shown in FIG. 2, a first n-type impurity region 17N having a predetermined depth from the surface of the n ⁻ -type epitaxial layer 11 and crossing between the adjacent p-type well regions 12 is formed. Further, a second n-type impurity region 16N having a predetermined depth from the lower surface of the first n-type impurity region 17N and crossing between the adjacent p-type well regions 12 is formed.

  Next, the results of examining the width W of the first n-type impurity region 17 and the second n-type impurity region 16a formed in the JFET region 15 and the depth d of the second n-type impurity region 16a will be described using FIGS. Will be described below.

  FIG. 3 is a graph showing an example of the calculation result of the n-type impurity concentration profile in the depth direction from the surface of the epitaxial layer in the central portion of the JFET region. The case where nitrogen (N) is introduce | transduced by ion implantation as an n-type impurity is illustrated. The solid line in the figure indicates the result of the silicon carbide semiconductor device (see FIG. 1) according to this example, and the broken line indicates the result of the silicon carbide semiconductor device of the comparative example (see FIG. 2). Here, the result in the case where the lower limit value of the implantation energy of the third n-type impurity region 16 b is 320 keV (depth d is 0.3 μm) is shown.

As shown in FIG. 3, in the silicon carbide semiconductor device according to the present embodiment, the first n-type impurity region 17 and the second n-type impurity region 16 a are in the surface layer portion of the n ⁻ -type epitaxial layer 11 in the central portion of the JFET region 15. Not formed. Thereby, in the central portion of JFET region 15, the depth from the surface of n ^-- type epitaxial layer 11 to the depth d is less than 1 × 10 ¹⁶ cm ^-3 , for example, about 3 × 10 ¹⁵ cm ^-3. The third n-type impurity region 16 b formed in a region deeper than the depth d only has an n-type impurity concentration of about 1 × 10 ^{16 to} 3 × 10 ¹⁶ cm ⁻³ .

On the other hand, in the silicon carbide semiconductor device according to the comparative example, the first n-type impurity region 17N and the second n-type impurity region 16N are formed in the central portion of the JFET region 15, and the first n-type impurity region 17N is, for example, 3 × 10. ¹⁶ to 5 × has an n-type impurity concentration of about ¹⁰ 16 ^{cm -3,} the 2n-type impurity region 16N has an n-type impurity concentration of, for example, approximately ^{1.5 × 10 16 ~3 × 10 16} cm -3 .

  FIG. 4 is a graph showing an example of the calculation result of the gate insulating film electric field along the interface between the gate insulating film and the epitaxial layer. The solid line in the figure indicates the result of the silicon carbide semiconductor device (see FIG. 1) according to this example, and the broken line indicates the result of the silicon carbide semiconductor device of the comparative example (see FIG. 2). Here, the results when the drain voltage is 3,000 V and the JFET width Lj is 1.7 μm are shown. Also, the results are shown when the width W is 0.5 μm and the depth d is 0.3 μm.

  As shown in FIG. 4, in the silicon carbide semiconductor device according to the present example, the electric field of the gate insulating film is reduced by about 10% compared to the silicon carbide semiconductor device according to the comparative example.

  FIG. 5 is a graph showing an example of calculation results of the relationship between the characteristic on-resistance and the gate insulating film electric field and the JFET width (Lj). The solid line in the figure indicates the result of the silicon carbide semiconductor device (see FIG. 1) according to this example, and the broken line indicates the result of the silicon carbide semiconductor device of the comparative example (see FIG. 2). Here, the results when the width W is 0.5 μm and the depth d is 0.3 μm are shown.

  As shown in FIG. 5, in the silicon carbide semiconductor device according to the present embodiment and the silicon carbide semiconductor device according to the comparative example, when the JFET width Lj increases, the characteristic on-resistance decreases and the gate insulating film electric field tends to increase. However, although the characteristic on-resistance of the silicon carbide semiconductor device according to the present embodiment is the same as the characteristic on-resistance of the silicon carbide semiconductor device according to the comparative example, in the silicon carbide semiconductor device according to the present embodiment, the silicon carbide semiconductor device according to the comparative example Also, the gate insulating film electric field decreases by about 10%.

  Therefore, when the silicon carbide semiconductor device according to the present embodiment is compared with the silicon carbide semiconductor device according to the comparative example in a structure having the same JFET width Lj, the silicon carbide semiconductor device according to the present embodiment has a gate insulating film electric field of 1 Since it can be reduced relatively, the reliability of the gate insulating film 18 can be improved. Further, when comparing the silicon carbide semiconductor device according to the present embodiment and the silicon carbide semiconductor device according to the comparative example with the same gate insulating film electric field, the silicon carbide semiconductor device according to the present embodiment has a JFET width Lj of about Since the thickness can be increased by 0.3 μm, the characteristic on-resistance can be reduced by about one to twenty percent.

  FIG. 6 is a graph showing an example of calculation results of the relationship between the characteristic on resistance increase rate and the gate insulating film electric field increase rate and the width (W) of the impurity region. Here, the results are shown when the JFET width Lj is 1.7 μm and the depth d is 0.3 μm. In the silicon carbide semiconductor device according to the comparative example, the width W corresponds to a half of the JFET width Lj, that is, 0.85 μm.

  As shown in FIG. 6, when the width W is smaller than 0.85 μm, the gate insulating film electric field increasing rate decreases and the characteristic on resistance increasing rate increases. However, if the width W becomes smaller than 0.5 μm, the characteristic on-resistance increase rate increases remarkably, so the width W is desirably 0.5 μm or more in order to suppress the increase in the characteristic on-resistance increase rate. When the width W is 0.5 μm, the silicon carbide semiconductor device according to the present embodiment suppresses the characteristic on resistance increase rate to 1% and the gate insulating film electric field increase rate to about 1% as compared with the silicon carbide semiconductor device according to the comparative example. It can be reduced by 7%.

  FIG. 7 is a graph showing an example of calculation results of the relationship between the characteristic on resistance increase rate and the gate insulating film electric field increase rate and the depth (d) of the second n-type impurity region 16a. Here, the results when the JFET width Lj is 1.7 μm and the width W is 0.5 μm are shown. In the silicon carbide semiconductor device according to the comparative example, the depth d corresponds to the case of 0 (zero).

  As shown in FIG. 7, as the depth d increases, the electric field increase rate of the gate insulating film decreases and the characteristic on resistance increase rate increases. However, if the depth d is larger than 0.3 μm, the characteristic on-resistance increase rate is significantly increased. Therefore, in order to suppress the increase in the characteristic on-resistance increase rate, the depth d is preferably 0.3 μm or less. When the depth d is 0.3 μm, in the silicon carbide semiconductor device according to this example, the characteristic on-resistance increase rate is suppressed to 1% and the gate insulating film electric field increase rate is reduced as compared to the silicon carbide semiconductor device according to the comparative example. It can be reduced by about 7%.

«Method of manufacturing silicon carbide semiconductor device»
The manufacturing method of the silicon carbide semiconductor device by a present Example is demonstrated to process order using FIGS. 8-18. 8 to 18 are main-portion cross-sectional views showing an example of a manufacturing process of the silicon carbide semiconductor device according to the present embodiment.

First, as shown in FIG. 8, for example, an n ⁺ -type SiC substrate 10 is prepared. An n-type impurity is introduced to the n ⁺ -type SiC substrate 10. The n-type impurity is, for example, nitrogen (N) or phosphorus (P), and the impurity concentration of the n-type impurity is, for example, about 2 × 10 ¹⁸ cm ⁻³ . The thickness of the n ⁺ -type SiC substrate 10 is, for example, about 350 μm. Further, although the n ⁺ -type SiC substrate 10 has both surfaces of the Si surface and the C surface, the surface of the n ⁺ -type SiC substrate 10 may be either the Si surface or the C surface.

Next, the n ⁻ -type epitaxial layer 11 of silicon carbide (SiC) is formed on the surface of the n ⁺ -type SiC substrate 10 by the epitaxial growth method. An n-type impurity lower than the impurity concentration of the n ⁺ -type SiC substrate 10 is introduced into the n ⁻ -type epitaxial layer 11. The impurity concentration of the n ⁻ -type epitaxial layer 11 depends on the element rating of the silicon carbide semiconductor device, and is, for example, about 3 × 10 ¹⁵ cm ⁻³ . The thickness of the n ⁻ -type epitaxial layer 11 is, for example, 30 μm.

Next, as shown in FIG. 9, an oxide film 30 made of, for example, silicon oxide (SiO ₂ ) is formed on the n ⁻ -type epitaxial layer 11, and then the oxide film 30 is processed by etching using a resist pattern as a mask. Thus, the oxide film 30 in which the region where the p-type well region 12 is formed is opened is formed.

Subsequently, a p-type impurity such as aluminum (Al) is ion-implanted into the n ⁻ -type epitaxial layer 11 using the oxide film 30 as a mask. Thus, a plurality of p-type well regions 12 are formed in the element formation region of the n ⁻ -type epitaxial layer 11. A region sandwiched between the p-type well regions 12 adjacent to each other is a portion functioning as the JFET region 15, and the JFET width Lj is desirably, for example, about 1.7 μm. The depth from the surface of the n ⁻ -type epitaxial layer 11 of the p-type well region 12 is, for example, about 2.0 μm. The impurity concentration of the p-type well region 12 is, for example, about 3 × 10 ¹⁶ to 1 × 10 ¹⁸ cm ⁻³ .

Next, as shown in FIG. 10, the oxide film 30 is processed by isotropic etching, and the oxide film 30 is shrunk so that the amount of recession (etching amount) from the side surface becomes the width W. The width W of the amount of retraction is preferably about 0.5 μm, for example. Subsequently, a resist film 31 is formed on the n ⁻ -type epitaxial layer 11 so as to cover the shrunk oxide film 30.

  Next, as shown in FIG. 11, resist film 31 is processed to form JFET region 15 and a region having a predetermined width in p type well region 12 from the end side surface of p type well region 12 (AA A resist pattern 31a is formed in which an area shown by ') is opened.

Next, as shown in FIG. 12, using oxide film 30 and resist pattern 31 a as a mask, n ⁻ -type epitaxial layer 11 (a JFET region 15 on both sides of oxide film 30 and a p-type well An n-type impurity such as nitrogen (N) is ion-implanted into a region having a predetermined width (a region indicated by AB and A′-B ′) in the mold well region 12. In the ion implantation, multistage ion implantation is used in which ion implantation is performed multiple times while changing the implantation energy so that the impurity distribution has a desired thickness. Thus, first n-type impurity region 17 has a predetermined depth from the surface of n ⁻ -type epitaxial layer 11 and a width W in JFET region 15 from the end side surface of p-type well region 12. It is formed. Subsequently, the second n-type impurity region 16 a has a predetermined depth from the lower surface of the first n-type impurity region 17 and a width W in the JFET region 15 from the end side surface of the p-type well region 12. It is formed.

The first n-type impurity region 17 is a region having a function of adjusting the threshold voltage, and the depth of the first n-type impurity region 17 from the surface of the n ⁻ -type epitaxial layer 11 is, for example, 0.1 to 0. The implantation energy is, for example, about 10 to 60 keV. The impurity concentration of the first n-type impurity region 17 is set higher than the impurity concentration of the second n-type impurity region 16 a so that the threshold voltage has a desired value.

The second n-type impurity region 16 a is a region having a function of reducing the resistance of the JFET region 15 by suppressing the extension of the depletion layer from the p-type well region 12 to the JFET region 15. The impurity concentration of the second n-type impurity region 16 a is higher than the impurity concentration of the n ⁻ -type epitaxial layer 11 and is, for example, about 1 × 10 ¹⁶ to 2 × 10 ¹⁶ cm ⁻³ . The lower limit value of the implantation energy is larger than the implantation energy used to form the first n-type impurity region 17, and the upper limit value of the implantation energy is set so that the depth d becomes a desired value. The depth d is preferably, for example, about 0.3 μm, and the upper limit value of the implantation energy in this case is, for example, 320 keV.

Next, as shown in FIG. 13, after removing the oxide film 30, the resist pattern 31a as a mask, n ^- -type epitaxial layer 11 (JFET region 15 p-type well from the side surface of and the p-type well region 12, An n-type impurity such as nitrogen (N) is ion-implanted into a region (a region indicated by AA ′) having a predetermined width in the region 12. In the ion implantation, multistage ion implantation is used in which ion implantation is performed multiple times while changing the implantation energy so that the impurity distribution has a desired thickness. Thereby, a third n-type impurity region 16 b having a predetermined depth from the lower surface of the second n-type impurity region 16 a and crossing between the adjacent p-type well regions 12 is formed.

The third n-type impurity region 16 b suppresses the extension of the depletion layer from the p-type well region 12 to the JFET region 15, and the current flows from the second n-type impurity region 16 a on both sides into the JFET region 15. It is a region having a function to reduce the JFET resistance of the neck portion. The impurity concentration of the third n-type impurity region 16 b is higher than the impurity concentration of the n ⁻ -type epitaxial layer 11 and is, for example, about 1 × 10 ^{16 to} 3 × 10 ¹⁶ cm ⁻³ . The lower limit value of the implantation energy is set to be larger than the upper limit value of the implantation energy used to form the second n-type impurity region 16a.

  Thereby, in the surface layer portion of JFET region 15, first n-type impurity region 17 and second n-type impurity region 16 a are formed only at both end portions in contact with p-type well region 12. The impurity concentration at both ends in contact with region 12 can be relatively high, and the impurity concentration at the central portion of JFET region 15 can be relatively low.

Next, as shown in FIG. 14, after removing the resist pattern 31 a, an n-type impurity such as nitrogen (N) is ion-implanted into the n ⁻ -type epitaxial layer 11 using the pattern 32 made of a resist film or oxide film as a mask. Then, the n ⁺ -type source region 14 is formed in the p-type well region 12 so as to be separated from the end side surface of the p-type well region 12. The depth of the n ⁺ -type source region 14 from the surface of the n ⁻ -type epitaxial layer 11 is, for example, about 0.2 to 0.3 μm. The impurity concentration of the n ⁺ -type source region 14 is higher than the impurity concentration of the p-type well region 12 and is, for example, about 1 × 10 ¹⁸ to 1 × 10 ²⁰ cm ⁻³ .

Next, as shown in FIG. 15, after removing the pattern 32, a p-type impurity such as aluminum (Al) is ion-implanted into the n ^-- type epitaxial layer 11 using the pattern 33 made of a resist film or oxide film as a mask. Then, the p ⁺ -type well contact region 13 is formed in the region for fixing the potential of the p-type well region 12. The depth from the surface of the n ⁻ -type epitaxial layer 11 of the p ⁺ -type well contact region 13 is, for example, about 0.3 to 0.4 μm. The impurity concentration of the p ⁺ -type well contact region 13 is, for example, about 1 × 10 ¹⁸ to 1 × 10 ²⁰ cm ⁻³ .

  Next, after the pattern 33 is removed, heat treatment is performed in an atmosphere of inert gas such as argon (Ar) gas to activate the ion-implanted impurities.

Next, as shown in FIG. 16, a gate insulating film 18 made of silicon oxide (SiO ₂ ) or silicon oxynitride (SiON) is formed on the surface of the n ⁻ -type epitaxial layer 11. The gate insulating film 18 made of silicon oxynitride is formed, for example, by forming a silicon oxide (SiO ₂ ) film by a CVD (Chemical Vapor Deposition) method and then performing heat treatment in a nitrogen oxide (NO or N ₂ O) atmosphere. . The thickness of the gate insulating film 18 is, for example, about 0.05 to 0.15 μm.

  Next, a polycrystalline silicon (Si) film is formed on the gate insulating film 18, and the polycrystalline silicon (Si) film is processed by dry etching to form the gate electrode 19. The thickness of the gate electrode 19 is, for example, about 0.2 to 0.5 μm.

Next, as shown in FIG. 17, an interlayer insulating film 20 is formed on the surface of the n ⁻ -type epitaxial layer 11 by plasma CVD, for example, so as to cover the gate insulating film 18 and the gate electrode 19.

Next, as shown in FIG. 18, interlayer insulating film 20 and gate insulating film 18 are processed by dry etching to reach opening CN reaching a part of n ⁺ type source region 14 and p ⁺ type well contact region 13. And the interlayer insulating film 20 is processed by dry etching to form an opening (not shown) reaching the gate electrode 19.

Next, a drain wiring electrode 22 is formed to cover the back surface of the n ⁺ -type SiC substrate 10. The thickness of the drain wiring electrode 22 is, for example, about 0.4 μm.

Next, on interlayer insulating film 20 including the inside of opening CN reaching a portion of n ⁺ type source region 14 and p ⁺ well contact region 13 and the inside of the opening (not shown) reaching gate electrode 19 A stacked film of a metal film, for example, a titanium (Ti) film, a titanium nitride (TiN) film, and an aluminum (Al) film is deposited. The thickness of the aluminum (Al) film is preferably, for example, 2.0 μm or more. Subsequently, by processing the laminated film, a gate electrically connected to source wiring electrode 21 and gate electrode 19 electrically connected to a part of n ⁺ type source region 14 and p ⁺ type well contact region 13 A wiring electrode (not shown) is formed. Thereafter, external interconnections are electrically connected to source interconnection electrode 21 and gate interconnection electrode (not shown), whereby the silicon carbide semiconductor device is substantially completed.

«Effect of the example»
As described above, according to the silicon carbide semiconductor device according to the present embodiment, the first n-type impurity region 17, the second n-type impurity region 16a, and the third n-type impurity region 16b, through which current flows in the on state, have high impurity concentrations. And the characteristic on-resistance can be reduced. Further, the first n-type impurity region 17 and the second n-type impurity region 16a are not formed in the surface layer portion and the central portion of the JFET region 15, and regions having impurity concentrations lower than these are provided. The electric field in the gate insulating film 18 is relaxed.

  Therefore, it is possible to suppress the increase in the characteristic on-resistance and to improve the reliability of the gate insulating film 18 by reducing the electric field of the gate insulating film. Alternatively, the loss of the switching element can be reduced by suppressing the increase of the gate insulating film electric field and reducing the characteristic on-resistance.

  Furthermore, for example, when the silicon carbide semiconductor device according to the present embodiment is mounted as a switching element on a power module constituting a power conversion device (inverter), the silicon carbide semiconductor device according to the present embodiment has high withstand voltage as described above, And, since the characteristic on-resistance is low, a high performance and highly reliable power module can be realized.

  As mentioned above, although the invention made by the present inventor was concretely explained based on an embodiment, the present invention is not limited to the above-mentioned embodiment, and can be variously changed in the range which does not deviate from the gist. Needless to say.

10 n ⁺ type SiC substrate 11 n ⁻ type epitaxial layer 12 p type well region 13 p ⁺ type well contact region 14 n ⁺ type source region 15 JFET region 16 a second n type impurity region 16 b third n type impurity region 16 N second n type impurity Region 17 first n-type impurity region 17N first n-type impurity region 18 gate insulating film 19 gate electrode 20 interlayer insulating film 21 electrode for source wiring 22 electrode for drain wiring 30 oxide film 31 resist film 31a resist pattern 32, 33 pattern CH channel region CN opening

Claims (17)

A substrate of a first conductivity type having a first main surface and a second main surface opposite to the first main surface and made of silicon carbide;
An epitaxial layer of the first conductivity type formed of silicon carbide formed on the first main surface of the substrate;
A plurality of well regions of a second conductivity type different from the first conductivity type formed in the epitaxial layer from the surface of the epitaxial layer;
A JFET region of the first conductivity type sandwiched between the well regions adjacent to each other;
A first impurity region of the first conductivity type formed in the JFET region and having a first width from an end side surface of the well region and a first depth from a surface of the epitaxial layer; ,
A second impurity of the first conductivity type formed in the JFET region, having a second width from an end side surface of the well region and a second depth from a lower surface of the first impurity region. Area,
A third impurity region of the first conductivity type formed in the JFET region having a third depth from the lower surface of the second impurity region and crossing between the well regions adjacent to each other;
A source region of the first conductivity type formed in the well region from the surface of the epitaxial layer at a distance from an end side surface of the well region;
A channel region formed in a surface portion of the well region between an end side surface of the well region and an end side surface of the source region;
A gate insulating film formed in contact with the channel region;
A gate electrode formed in contact with the gate insulating film;
Have
The first width and the second width are smaller than 1/2 of the width of the JFET region,
Wherein the surface layer portion of the JFET region, and the impurity concentration of the epitaxial layer including a central portion, said first, rather lower than the impurity concentration of the second and third impurity regions,
The semiconductor device , wherein a depth of the third impurity region from the surface of the epitaxial layer is shallower than a depth of the well region from the surface of the epitaxial layer . In the semiconductor device according to claim 1,
The semiconductor device, wherein the depth from the surface of the epitaxial layer of the second impurity region is 0.3 μm or less. In the semiconductor device according to claim 1,
The semiconductor device according to claim 1, wherein the first width and the second width are 0.5 μm or more. In the semiconductor device according to claim 1,
The semiconductor device according to claim 1, wherein the first width and the second width are the same, and the first width and the second width are 0.5 μm or more. In the semiconductor device according to claim 1,
The semiconductor device, wherein the impurity concentration at the interface between the second impurity region and the third impurity region is 1 × 10 ¹⁶ to 2 × 10 ¹⁶ cm ⁻³ . In the semiconductor device according to claim 1,
The semiconductor device, wherein the impurity concentration of the first impurity region is higher than the impurity concentration of the second impurity region. In the semiconductor device according to claim 1,
The semiconductor device, wherein the impurity concentration of the surface layer portion and the central portion of the JFET region is the same as the impurity concentration of the epitaxial layer. In the semiconductor device according to claim 1,
The semiconductor device, wherein the impurity concentration of the second impurity region and the impurity concentration of the third impurity region are the same. In the semiconductor device according to claim 1,
A source wiring electrode electrically connected to the source region and the well region;
A drain wiring electrode formed on the second main surface of the substrate;
The semiconductor device which further has Semiconductor device manufacturing method including the following steps:
(A) forming an epitaxial layer of the first conductivity type made of silicon carbide on a first main surface of a substrate of the first conductivity type made of silicon carbide;
(B) forming a plurality of well regions by ion implanting an impurity of a second conductivity type different from the first conductivity type into the epitaxial layer from the surface of the epitaxial layer using a first mask; ;
(C) Using the second mask, the impurity of the first conductivity type is ion-implanted from the surface of the epitaxial layer into the epitaxial layer to form the well in a region sandwiched between the adjacent well regions. Forming a first impurity region having a first width from an end side surface of the region and having a first depth from a surface of the epitaxial layer;
(D) The impurity of the first conductivity type is ion-implanted from the surface of the epitaxial layer into the epitaxial layer from the surface of the epitaxial layer using the second mask, in a region sandwiched between the well regions adjacent to each other Forming a second impurity region having a second width from the end side surface of the well region and having a second depth from the lower surface of the first impurity region;
(E) implanting the impurity of the first conductivity type into the epitaxial layer from the surface of the epitaxial layer using a third mask to form the third conductive layer in a region sandwiched between the well regions adjacent to each other; (2) forming a third impurity region having a third depth from the lower surface of the impurity region and crossing between the well regions adjacent to each other;
(F) forming a source region by ion-implanting the impurity of the first conductivity type into the well region from the surface of the epitaxial layer at a distance from the side surface of the end of the well region;
(G) forming a gate insulating film in contact with the surface of the epitaxial layer, and forming a gate electrode on the gate insulating film;
Here, the first width and the second width is rather smaller than half the width of the region sandwiched by the well region adjacent to each other,
The impurity concentration of the epitaxial layer including a region sandwiched between the well regions adjacent to each other and surrounded by the first, second and third impurity regions is the same as that of the first, second and third impurity regions. Lower than the impurity concentration,
A method of manufacturing a semiconductor device , wherein a depth from the surface of the epitaxial layer of the third impurity region is shallower than a depth from the surface of the epitaxial layer of the well region . In the method of manufacturing a semiconductor device according to claim 10 ,
The upper limit of the implantation energy of the ion implantation which forms said 2nd impurity area | region of the said (d) process is a manufacturing method of the semiconductor device which is 320 keV. In the method of manufacturing a semiconductor device according to claim 10 ,
The semiconductor device manufacturing method, wherein the depth from the surface of the epitaxial layer of the second impurity region is 0.3 μm or less. In the method of manufacturing a semiconductor device according to claim 10 ,
The manufacturing method of the semiconductor device whose said 1st width and said 2nd width are 0.5 micrometer or more. In the method of manufacturing a semiconductor device according to claim 10 ,
The method of manufacturing a semiconductor device, wherein the first width and the second width are the same, and the first width and the second width are 0.5 μm or more. In the method of manufacturing a semiconductor device according to claim 10 ,
A method of manufacturing a semiconductor device, wherein an impurity concentration at an interface between the second impurity region and the third impurity region is 1 × 10 ¹⁶ to 2 × 10 ¹⁶ cm ⁻³ . In the method of manufacturing a semiconductor device according to claim 10 ,
The method of manufacturing a semiconductor device, wherein the impurity concentration of the first impurity region is higher than the impurity concentration of the second impurity region. In the method of manufacturing a semiconductor device according to claim 10,
(H) forming a drain wiring electrode on a second main surface of the substrate opposite to the first main surface;
(I) forming an electrode for source wiring connected to the source region and the well region;
A method of manufacturing a semiconductor device, further comprising:

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