CN113113464B - Semiconductor device and manufacturing method thereof - Google Patents
Semiconductor device and manufacturing method thereof Download PDFInfo
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- CN113113464B CN113113464B CN202010035212.9A CN202010035212A CN113113464B CN 113113464 B CN113113464 B CN 113113464B CN 202010035212 A CN202010035212 A CN 202010035212A CN 113113464 B CN113113464 B CN 113113464B
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 266
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 13
- 238000000034 method Methods 0.000 claims description 24
- 238000005468 ion implantation Methods 0.000 claims description 18
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical group [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 claims description 10
- 229910010271 silicon carbide Inorganic materials 0.000 claims description 9
- 239000000463 material Substances 0.000 claims description 6
- 229910044991 metal oxide Inorganic materials 0.000 claims description 4
- 150000004706 metal oxides Chemical class 0.000 claims description 4
- 230000005669 field effect Effects 0.000 abstract description 25
- 230000005684 electric field Effects 0.000 description 13
- 230000008569 process Effects 0.000 description 7
- 239000000758 substrate Substances 0.000 description 7
- 230000004888 barrier function Effects 0.000 description 6
- 230000000694 effects Effects 0.000 description 3
- 239000002019 doping agent Substances 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 description 1
- 239000000969 carrier Substances 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 229910003460 diamond Inorganic materials 0.000 description 1
- 239000010432 diamond Substances 0.000 description 1
- 230000007480 spreading Effects 0.000 description 1
- 238000003892 spreading Methods 0.000 description 1
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
- H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66234—Bipolar junction transistors [BJT]
- H01L29/66325—Bipolar junction transistors [BJT] controlled by field-effect, e.g. insulated gate bipolar transistors [IGBT]
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/66681—Lateral DMOS transistors, i.e. LDMOS transistors
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
- H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors
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Abstract
The invention discloses a semiconductor device and a manufacturing method thereof, the semiconductor device includes: a first conductive type semiconductor layer; a plurality of first semiconductor regions of a second conductivity type disposed within the first conductivity type semiconductor layer, the plurality of first semiconductor regions extending in a first direction; and a plurality of second semiconductor regions of a second conductivity type extending in the second direction, disposed in the first conductivity type semiconductor layer and between and in contact with two adjacent first semiconductor regions. According to the semiconductor device provided by the embodiment of the invention, the widths of the junction field effect region and the second semiconductor region can be adjusted, and the unit cell size of the semiconductor device can be reduced by reducing the width of the junction field effect region.
Description
Technical Field
The invention relates to the field of transistor structures, in particular to a semiconductor device and a manufacturing method thereof.
Background
For semiconductor devices, one potential problem is the presence of high electric fields at the gate oxide of the Junction Field Effect (JFET) region of the device. The JFET region is typically the active portion of the N-type drift region, which may include N-type dopants, and is located between two P-type wells. The JFET region may refer to a region in contact with a channel region reaching the surface of the P-type well by applying a gate voltage. The JFET region together with the N + source region, the channel region, the N-drift region, the substrate and the drain electrode form a conduction path for electrons. Under operating conditions where a high bias voltage is applied to the drain (near the operating maximum) and the gate is held near ground potential, a high electric field is present in the gate oxide over the JFET region, at which point defects in the interface material and gate oxide can cause gate oxide failure and hot carriers can also be injected into the gate oxide.
Generally, as shown in fig. 7, in order to reduce the high electric field at the gate oxide of the junction field effect region of the semiconductor device, it is often adopted to introduce a P + region in the middle of the junction field effect region. However, this method reduces the high electric field at the gate oxide of the junction field effect region of the semiconductor device, which results in a large unit cell size because the P + region itself needs to occupy a portion of the junction field effect region and is introduced in the middle of the junction field effect region, and there is a gap between the P + region and the adjacent P + well region. In order to further reduce the on-resistance of the device, it is necessary to increase the channel density per unit area as much as possible, i.e., to reduce the cell size, while keeping the channel mobility constant. But it is difficult to reduce the unit cell size with the above structure.
Disclosure of Invention
In view of the above, the present invention provides a semiconductor device and a method for manufacturing the same.
According to a first aspect, embodiments of the present invention provide a semiconductor device, including: a first conductive type semiconductor layer; a plurality of first semiconductor regions of a second conductivity type disposed within the first conductivity type semiconductor layer, the plurality of first semiconductor regions extending in a first direction; and a plurality of second semiconductor regions of a second conductivity type extending in the second direction, disposed in the first conductivity type semiconductor layer and between and in contact with two adjacent first semiconductor regions.
Optionally, the first semiconductor region has a doping concentration of 1 x 10 15 cm －3 －1＊10 18 cm －3 。
Optionally, the second semiconductor region has a doping concentration of 5 ANGSTROM 10 16 cm －3 －5＊10 20 cm －3 。
Optionally, the length of the second semiconductor region is less than 2 μm.
Alternatively, the first conductive type semiconductor layer is made of a wide bandgap semiconductor.
Optionally, the material of the wide bandgap semiconductor is silicon carbide.
Optionally, the semiconductor device comprises: MOSFET, insulated gate bipolar transistor, and metal oxide semiconductor controlled thyristor.
According to a second aspect, embodiments of the present invention provide a method of manufacturing a semiconductor device, including: forming a first conductive type semiconductor layer; forming a plurality of first semiconductor regions in the first conductive type semiconductor layer, the first semiconductor regions being of a second conductive type, the plurality of first conductive type semiconductor regions extending in a first direction; a plurality of second semiconductor regions of a second conductivity type are formed in the first conductivity type semiconductor layer, extend in the second direction, are located between adjacent two of the first semiconductor regions, and are in contact with the adjacent two of the first semiconductor regions.
Optionally, forming several first semiconductor regions within the first conductivity type semiconductor layer includes: a plurality of first semiconductor regions are formed in the first conductive type semiconductor layer by an ion implantation method, wherein the first semiconductor regions are of the second conductive type, and the plurality of first conductive type semiconductor regions extend in the first direction.
Optionally, forming several first semiconductor regions within the first conductivity type semiconductor layer includes: a plurality of first semiconductor regions are formed in the first conductive type semiconductor layer by a tilted ion implantation method, wherein the first semiconductor regions are of the second conductive type, and the plurality of first conductive type semiconductor regions extend in the first direction.
Optionally, forming several second semiconductor regions within the first conductivity type semiconductor layer includes: and forming a plurality of second semiconductor regions in the first conductivity type semiconductor layer by ion implantation, wherein the second semiconductor regions are of the second conductivity type, extend in the second direction, are positioned between two adjacent first semiconductor regions, and are in contact with the two adjacent first semiconductor regions.
Optionally, forming a first conductivity type semiconductor layer includes: the first conductive type semiconductor layer is formed using a wide bandgap semiconductor.
Compared with the prior art that a P + region is introduced in the middle of a junction field effect region and extends along a second direction, the semiconductor device and the manufacturing method thereof provided by the embodiment of the invention have the advantages that a plurality of second semiconductor regions are arranged at intervals in the second direction of the junction field effect region to form a barrier layer in the second direction, and the barrier layer can achieve the same effect as the P + region in the prior art, namely, the electric field at a grid oxide from a drain electrode side to a grid electrode side is blocked, so that the high electric field at the grid oxide of the junction field effect region of the semiconductor device is reduced; and the second semiconductor region extends along the first direction and contacts with the first semiconductor region, thereby not considering the connection process of the first semiconductor and the second semiconductor; meanwhile, since each second semiconductor region is in contact with the first semiconductor region, there is no gap between the second semiconductor region and the adjacent first semiconductor region, so that the widths of the junction field effect region and the second semiconductor region can be adjusted, and the unit cell size of the semiconductor device can be reduced by reducing the width of the junction field effect region.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, and it is obvious that the drawings in the following description are some embodiments of the present invention, and other drawings can be obtained by those skilled in the art without creative efforts.
FIG. 1 illustrates a top view of a semiconductor device structure according to an embodiment of the present invention;
FIG. 2 illustrates a cross-sectional view of a semiconductor device structure in accordance with an embodiment of the present invention;
FIG. 3 illustrates another cross-sectional view of a semiconductor device structure in accordance with an embodiment of the present invention;
FIG. 4 illustrates a cross-sectional view of a MOSFET structure in accordance with an embodiment of the present invention;
FIG. 5 shows a cross-sectional view of an IGBT structure according to an embodiment of the invention;
FIG. 6 illustrates a flow chart of a method of manufacturing a semiconductor device according to an embodiment of the present invention;
fig. 7 is a schematic cross-sectional view of a structure of a semiconductor device in the related art.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, but not all, embodiments of the present invention. All other embodiments, which can be obtained by a person skilled in the art without inventive step based on the embodiments of the present invention, are within the scope of protection of the present invention.
This invention may be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete and will fully convey the concept of the invention to those skilled in the art, and the present invention will only be defined by the appended claims. In the drawings, the size and relative sizes of layers and regions may be exaggerated for clarity.
It will be understood that when an element such as a layer, region or substrate is referred to as being "on" or extending "onto" another element, it can be directly on or extend directly onto the other element or intervening elements may also be present. In contrast, when an element is referred to as being "directly on" or extending "directly onto" another element, there are no intervening elements present. Also, it will be understood that when an element (e.g., a layer, region or substrate) is referred to as being "on" or extending "over" another element, it can be directly on or extend directly over the other element, or intervening elements may also be present. In contrast, when an element is referred to as being "directly on" or extending "directly over" another element, there are no intervening elements present. It will also be understood that when an element is referred to as being "connected" or "coupled" to another element, it can be directly connected or coupled to the other element or intervening elements may also be present. In contrast, when an element is referred to as being "directly connected" or "directly coupled" to another element, there are no intervening elements present.
Relative terms (e.g., "below …" or "above …" or "upper" or "lower" or "horizontal" or "vertical") may be used herein to describe the relationship of one element, layer or region to another element, layer or region as illustrated in the figures. It will be understood that these terms and those discussed above are intended to encompass different orientations of the device in addition to the orientation depicted in the figures.
Since there is a need for a semiconductor device with a reduced electric field at the gate oxide interface and a reduced cell size, embodiments of the present invention provide a semiconductor device having a new structure so that the electric field at the gate oxide interface is reduced and the cell size can be reduced. As shown in fig. 1 to 3, the semiconductor device includes: a first conductivity type semiconductor layer 1; a plurality of first semiconductor regions 7, the first semiconductor regions 7 being of a second conductivity type, disposed within the first conductivity type semiconductor layer 1, the plurality of first semiconductor regions 7 extending in a first direction; and a plurality of second semiconductor regions 2, wherein the second semiconductor regions 2 are of a second conductivity type, extend in a second direction, are perpendicular to the first direction, are arranged in the first conductivity type semiconductor layer 1, are positioned between two adjacent first semiconductor regions 7, and are in contact with the two adjacent first semiconductor regions 7.
In particular, the semiconductor device has a gate, a source and a drain and comprises a first epitaxial layer 4 of the second conductivity type, a second epitaxial layer 5 of the first conductivity type on the first epitaxial layer and a gate oxide 3 adjacent a first surface of the transistor device. The semiconductor device further comprises a well region 6 of the second conductivity type extending from the first outer lateral layer down into the semiconductor layer 1 of the first conductivity type of the semiconductor device to a depth, the thin layer of the well region of the second conductivity type on the contact surface of the well region 6 of the second conductivity type with the gate oxide 3 being a first semiconductor region 7, a JFET region adjacent to the well region 6 of the second conductivity type and the substrate under the well region, under the first conductivity type semiconductor layer, of the semiconductor layer 1 of the first conductivity type.
Several second semiconductor regions 2 introduced in the JFET region are arranged between two adjacent first semiconductor regions 7 and on the side of the JFET region close to the gate oxide 3. The first semiconductor region 7 extends in a first direction, the second semiconductor regions 2 extend in a second direction and are in contact with the first semiconductor region 7, and a plurality of the second semiconductor regions 2 are arranged at intervals in the first direction.
Compared with the prior art in which a P + region is introduced in the middle of a junction field effect region, the P + region extends along a second direction, the semiconductor device provided by the embodiment of the invention is characterized in that a plurality of second semiconductor regions are arranged at intervals in the second direction of the junction field effect region to form a barrier layer in the second direction, and the barrier layer can achieve the same effect as the P + region in the prior art, namely, the electric field at a gate oxide from a drain side to a gate side is blocked, so that the high electric field at the gate oxide of the junction field effect region of the semiconductor device is reduced; and the second semiconductor region extends along the first direction and contacts with the first semiconductor region, thereby not considering the connection process of the first semiconductor and the second semiconductor; meanwhile, since each second semiconductor region is in contact with the first semiconductor region, there is no gap between the second semiconductor region and the adjacent first semiconductor region, so that the width of the junction field effect region and the second semiconductor region can be adjusted, and the unit cell size of the semiconductor device can be reduced by reducing the width of the junction field effect region.
In alternative embodiments, the first conductivity type may be N-type and the second conductivity type may be P-type. The JFET region is generally the active portion of the N-type drift region that may include N-type dopants and is located between two P-type wells (e.g., well region 6 of the second conductivity type). The JFET region may generally refer to a region in contact with a surface channel region (i.e. the first semiconductor region 7) that is reached by applying a gate voltage to the P-well. The JFET region together with the source region, the N-drift region, the first conductivity type region 1 and the drain electrode form a conduction path for electrons. The JFET region may be provided by epitaxial growth or by ion implantation. In some embodiments, the JFET region can have a thickness ranging from 0.5 microns to 1.5 microns. The JFET region has a width of between 0.5 microns and 1 micron and the second semiconductor region 2 introduced within the JFET region may have a thickness that is less than the thickness of the first semiconductor region 7, which may mitigate the charge spreading resistance.
In an alternative embodiment, the length of the second semiconductor region is preferably less than between 2 microns.
In an alternative embodiment, the doping concentration of the first semiconductor region 7 is greaterDegree of 1 x 10 15 cm －3 －5＊10 17 cm －3 . The first semiconductor region is doped with a low doping concentration, and a channel can be formed in the first semiconductor region.
In an alternative embodiment, the doping concentration of the second semiconductor region 2 is 5 x 10 16 cm －3 －5＊10 20 cm －3 . The doping concentration of the second conductivity type region is high doping, and the second conductivity type region can be prevented from being broken down by a large electric field from the drain side to the gate side.
In an alternative embodiment, the first conductive type semiconductor layer 1 is made of a wide bandgap semiconductor. Specifically, the first conductivity type semiconductor layer is a drift region. Preferably, the material of the wide bandgap semiconductor is silicon carbide.
In an alternative embodiment, as shown in fig. 4, the semiconductor device may be a MOSFET device, and even more preferably a silicon carbide MOSFET device. As shown in fig. 5, the semiconductor device may be an Insulated Gate Bipolar Transistor (IGBT). Of course, the transistor device may also be any type of device having a transistor (e.g., a MOSFET, a double differential field effect transistor, a trench gate metal oxide semiconductor field effect transistor, an Insulated Gate Bipolar Transistor (IGBT), or a metal oxide semiconductor controlled thyristor).
An embodiment of the present invention further provides a method for manufacturing a semiconductor device, as shown in fig. 6, including:
s101, forming a first conductive type semiconductor layer; specifically, the first conductivity type semiconductor layer may be formed by a known means.
S102, forming a plurality of first semiconductor regions in the first conduction type semiconductor layer, wherein the first semiconductor regions are of a second conduction type, and the plurality of first conduction type semiconductor regions extend in a first direction; specifically, after the first conductivity type semiconductor layer is formed, the method further includes: forming at least two second conductive type well regions on the first conductive type semiconductor layer; providing a first epitaxial layer such that the first epitaxial layer covers at least a portion of the well region; a second epitaxial layer provided on the first epitaxial layer; providing a gate oxide over a portion of the second epitaxial layer; first semiconductor regions are formed at interfaces of the well regions of the second conductivity type and the gate oxide, and a number of the first semiconductor regions are formed mainly by ion implantation.
And S103, forming a plurality of second semiconductor regions in the first conductivity type semiconductor layer, wherein the second semiconductor regions are of a second conductivity type and extend in a second direction, and the second direction is perpendicular to the first direction, is positioned between two adjacent first semiconductor regions and is in contact with the two adjacent first semiconductor regions. Specifically, the plurality of second semiconductor regions are mainly formed by ion implantation.
Compared with the prior art in which a P + region is introduced in the middle of a junction field effect region and extends along a second direction, the method for manufacturing the semiconductor device provided by the embodiment of the invention is characterized in that a plurality of second semiconductor regions are arranged at intervals in the second direction of the junction field effect region to form a barrier layer in the second direction, and the barrier layer can achieve the same effect as the P + region in the prior art, namely, the electric field at the gate oxide from the drain side to the gate side is blocked, so that the high electric field at the gate oxide of the junction field effect region of the semiconductor device is reduced; and the second semiconductor region extends along the first direction and contacts with the first semiconductor region, thereby not considering the connection process of the first semiconductor and the second semiconductor; meanwhile, since each second semiconductor region is in contact with the first semiconductor region, there is no gap between the second semiconductor region and the adjacent first semiconductor region, so that the width of the junction field effect region and the second semiconductor region can be adjusted, and the unit cell size of the semiconductor device can be reduced by reducing the width of the junction field effect region.
In an alternative embodiment, forming a number of first semiconductor regions within the first conductivity type semiconductor layer includes: a plurality of first semiconductor regions are formed in the first conductive type semiconductor layer by an ion implantation method, the first semiconductor regions being of the second conductive type, the plurality of first conductive type semiconductor regions extending in a first direction. The ion implantation is a mature process, and a plurality of first semiconductor regions are formed in the first conductive type semiconductor layer by the ion implantation method, so that the process is simple, and the doping concentration of the first semiconductor regions can be accurately controlled.
In an alternative embodiment, forming a number of first semiconductor regions within the first conductivity type semiconductor layer includes: a plurality of first semiconductor regions are formed in the first conductive type semiconductor layer by a tilted ion implantation method, the first semiconductor regions being of the second conductive type, the plurality of first conductive type semiconductor regions extending in a first direction. For example, for a silicon carbide substrate, the tilt angle may be less than 13 °. By forming several first semiconductor regions in the first conductivity type semiconductor layer by the oblique ion implantation method, the doping concentration of the first semiconductor regions can be precisely controlled, and the energy and temperature at the time of ion implantation can be reduced.
In an alternative embodiment, forming several second semiconductor regions within the first conductivity type semiconductor layer includes: and forming a plurality of second semiconductor regions in the first conductive type semiconductor layer by ion implantation, wherein the second semiconductor regions are of the second conductive type, extend in the second direction, are positioned between two adjacent first semiconductor regions and are in contact with the two adjacent first semiconductor regions. The ion implantation is a mature process, a plurality of second semiconductor regions are formed in the first conductive type semiconductor layer through the ion implantation method, the process is simple, and the doping concentration of the second semiconductor regions can be accurately controlled.
In an alternative embodiment, forming the first conductive type semiconductor layer includes: the first conductive type semiconductor layer is formed using a wide bandgap semiconductor. Specifically, the first conductivity type semiconductor layer may include a drift region, and the material of the wide bandgap semiconductor may be silicon carbide (SiC), gallium nitride (GaN), diamond, or the like, and preferably, the material of the wide bandgap semiconductor is silicon carbide, for example, a silicon carbide substrate is formed by a known means. A drift region is formed on a silicon carbide substrate by epitaxial growth. The body of the transistor now comprises a semiconductor layer of silicon carbide for controlling electrical conduction from top to bottom.
Although the embodiments of the present invention have been described in conjunction with the accompanying drawings, those skilled in the art can make various modifications and variations without departing from the spirit and scope of the invention, and such modifications and variations fall within the scope defined by the appended claims.
Claims (12)
1. A semiconductor device, comprising:
a first conductive type semiconductor layer;
a plurality of first semiconductor regions of a second conductivity type disposed within the first conductivity type semiconductor layer, the plurality of first semiconductor regions extending in a first direction;
the second semiconductor regions are of a second conductivity type, extend in a second direction, are arranged in the first conductivity type semiconductor layer, are positioned between two adjacent first semiconductor regions, and are in contact with the two adjacent first semiconductor regions, the second direction is perpendicular to the first direction, and the thickness of the second semiconductor regions is smaller than that of the first semiconductor regions.
2. The semiconductor device of claim 1, wherein the first semiconductor region has a doping concentration of 1 x 10 15 cm -3 -1*10 18 cm -3 。
3. The semiconductor device of claim 1, wherein the second semiconductor region has a doping concentration of 5 x 10 16 cm -3 -5*10 20 cm -3 。
4. The semiconductor device according to claim 1, wherein a length of the second semiconductor region is less than 2 μm.
5. The semiconductor device according to claim 1, wherein the first conductivity type semiconductor layer is made of a wide bandgap semiconductor.
6. The semiconductor device according to claim 5, wherein a material of the wide bandgap semiconductor is silicon carbide.
7. The semiconductor device according to claim 1, characterized in that the semiconductor device comprises:
MOSFET, insulated gate bipolar transistor, and metal oxide semiconductor controlled thyristor.
8. A method of manufacturing a semiconductor device, comprising:
forming a first conductive type semiconductor layer;
forming a plurality of first semiconductor regions within a first conductivity type semiconductor layer, the first semiconductor regions being of a second conductivity type, the plurality of first conductivity type semiconductor regions extending in a first direction;
forming a plurality of second semiconductor regions spaced apart in the first conductive type semiconductor layer, the second semiconductor regions being of a second conductive type, extending in a second direction, between and contacting two adjacent first semiconductor regions, the second direction being perpendicular to the first direction, the second semiconductor regions having a thickness smaller than that of the first semiconductor regions.
9. The method according to claim 8, wherein the forming of the first semiconductor regions in the first conductivity type semiconductor layer comprises:
and forming a plurality of first semiconductor regions in the first conductive type semiconductor layer by an ion implantation method, wherein the first semiconductor regions are of the second conductive type, and the plurality of first conductive type semiconductor regions extend in the first direction.
10. The method according to claim 8, wherein the forming of the first semiconductor regions in the first conductivity type semiconductor layer comprises:
forming a plurality of first semiconductor regions in the first conductive type semiconductor layer by a tilted ion implantation method, wherein the first semiconductor regions are of a second conductive type, and the plurality of first conductive type semiconductor regions extend in a first direction.
11. The method of manufacturing a semiconductor device according to claim 8, wherein the forming of the second semiconductor regions in the first conductivity type semiconductor layer comprises:
and forming a plurality of second semiconductor regions in the first conductivity type semiconductor layer by an ion implantation method, wherein the second semiconductor regions are of a second conductivity type, extend in a second direction, are positioned between two adjacent first semiconductor regions, and are in contact with the two adjacent first semiconductor regions.
12. The method of manufacturing a semiconductor device according to claim 8, wherein the forming of the first conductivity type semiconductor layer includes:
the first conductive type semiconductor layer is formed using a wide bandgap semiconductor.
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