TWI548095B - Semiconductor device and method of forming the same - Google Patents

Description

Semiconductor component and method of manufacturing same

The present invention relates to a semiconductor device and a method of fabricating the same.

The UHV component must have a high breakdown voltage and a low on-state resistance (Ron) during operation to reduce power loss. In the current ultra-high voltage components, it is often found that there is a very large current concentration effect at the source terminal, which becomes a collapse point, causing a breakdown voltage of the component to drop, and the leakage current is very serious.

Embodiments of the present invention provide a semiconductor device and a method of fabricating the same to provide a semiconductor device having a high breakdown voltage and a low leakage current.

The present invention provides a semiconductor device including a substrate, an isolation structure, a gate structure, a source region and a drain region having a first conductivity type, and a conductor layer. The source region and the drain region are located in the substrate. The isolation structure is located between the source region and the drain region. The gate structure is on the substrate between the source region and the isolation structure. The conductor layer is located above the substrate, at least from above the source region to above the isolation structure, and electrically connected to the source region. The substrate includes a first region and a second region, a curvature of a contour of the source region of the second region being greater than a curvature of a contour of the source region of the first region, and a conductor layer covering the isolation structure over the second region The width of the portion is greater than the width of the portion of the conductor layer overlying the isolation structure above the first region.

According to an embodiment of the invention, the conductor layer is the uppermost metal layer.

According to an embodiment of the invention, the semiconductor component includes a plurality of linear regions and a plurality of turning regions, one of the linear regions being located in the first region; and one of the turning regions is located in the second region.

According to an embodiment of the invention, the semiconductor device further includes: a top layer having a second conductivity type, located in the substrate under the isolation structure; and a step layer having the first conductivity type between the top layer and the isolation structure.

According to an embodiment of the present invention, the semiconductor device further includes a first well region having a second conductivity type, located in the substrate, wherein the source region is located in the first well region, and the gate structure covers a portion of the first well region; a doped region having a second conductivity type is located in the first well region, adjacent to the source region, and commonly connected to the source region; and a second well region having the first conductivity type is located in the substrate, wherein The first well zone and the bungee zone are located in the second well zone.

The present invention also provides a method of fabricating a semiconductor device comprising forming an isolation structure on a substrate. A gate structure is formed on the substrate. A source region having a first conductivity type and a drain region having a first conductivity type are formed in the substrate on both sides of the gate structure and the isolation structure. The source region is close to the gate structure, and the drain region is close to the isolation structure. A conductor layer is formed over the substrate. The conductor layer extends from above the source region to above the isolation structure and is electrically connected to the source region. The substrate includes a first region and a second region, a curvature of a contour of the source region of the second region being greater than a curvature of a contour of the source region of the first region, and a conductor layer covering the isolation structure over the second region The width of the portion is greater than the width of the portion of the conductor layer overlying the isolation structure above the first region.

According to an embodiment of the invention, the conductor layer is the uppermost metal layer.

According to an embodiment of the invention, the semiconductor component includes a plurality of linear regions and a plurality of turning regions, one of the linear regions being located in the first region; and one of the turning regions is located in the second region.

According to an embodiment of the invention, the method of fabricating the semiconductor device further includes: forming a top layer having a second conductivity type in a substrate under the isolation structure; and forming a ladder having a first conductivity type between the top layer and the isolation structure Floor.

According to an embodiment of the invention, the method of fabricating the semiconductor device further includes: forming a first well region having a second conductivity type in the substrate, wherein the source region is located in the first well region, and the gate structure covers the portion a well region; forming a doped region having a second conductivity type in the first well region, the doped region is adjacent to the source region, and the conductor layer is commonly connected to the source region; and forming the first conductive layer in the substrate A second well zone of the type wherein the first well zone and the bungee zone are located in the second well zone.

Based on the above, the semiconductor component of the present invention designs the conductor layers of the source end (such as the uppermost metal layer) to have different widths according to the curvature of the contour of the source region, so as to disperse the electric field at a large curvature or a corner, and improve the collapse. Voltage, reducing leakage current.

The above described features and advantages of the present invention will be more apparent from the following description.

The concept of the present invention can be applied to a semiconductor element having a turning region in the source region, for example, a semiconductor element whose source region is a racetrack type or a U-shape, but is not limited thereto. The semiconductor component of the present invention is designed to have different widths of the source layer of the conductor layer (such as the uppermost metal layer) according to the curvature of the source region profile to disperse the electric field at a larger curvature or a corner, thereby increasing the breakdown voltage. Reduce leakage current. The following is a description of a semiconductor element having a U-type source region, however, the invention is not limited thereto.

1 is a top plan view of a semiconductor device in accordance with an embodiment of the present invention. 2G is a cross-sectional view of the tangent I-I and II-II of FIG. 1.

In the following embodiments, the first conductivity type is an N type, and the second conductivity type is a P type. The P-type doping is, for example, boron; the N-type doping is, for example, phosphorus or arsenic. However, the invention is not limited thereto. In other embodiments, the first conductivity type may be P-type and the second conductivity type may be N-type.

1 and 2G, the semiconductor device 99 of the present invention may be a high voltage component, an ultrahigh voltage component (operating voltage 300V to 1000V), a power component, a laterally diffused metal oxide semiconductor (LDMOS), or an insulated gate bipolar transistor. (IGBT). The semiconductor component 99 includes a substrate 10, isolation structures 24a-24d, a gate structure 30, a source region 34, a drain region 36, and a metal interconnect 60 (including conductor layers 50a, 50b, etc.). The semiconductor component 99 of the present invention may further include well regions 12, 16, 18, top layer 20, ladder layer 22, and doped regions 38, 40.

The substrate 10 is, for example, a semiconductor substrate having a second conductivity type, such as a P-type substrate. The material of the semiconductor substrate is, for example, at least one material selected from the group consisting of Si, Ge, SiGe, GaP, GaAs, SiC, SiGeC, InAs, and InP. Substrate 10 can also be a blanket insulating (SOI) substrate. The substrate 10 may be an epitaxial wafer having a second conductivity type, such as a P-type epitaxial (P-epi) wafer.

In one embodiment, the semiconductor element 99 includes a plurality of linear regions and a plurality of turning regions, but is not limited thereto. In the present embodiment, the first region 100 of the substrate 10 may be a linear region (where the curvature of the contour of the source region 34 is small or zero); the second region 200 of the substrate 10 may be a turning region (where the source region 34 The curvature of the contour is large).

The well region 12 has a first conductivity type that is located in the substrate 10. The well zone 12 is, for example, a well N, or a high pressure N well (HVNW). Well zones 16 and 18 have a second conductivity type, such as a P well. Well zone 16 is located in substrate 10 adjacent to well zone 12. Well zone 18 is located in well zone 12.

The isolation structures 24a-24d are located on the substrate 10. In more detail, the isolation structure 24a covers a portion of the well region 16. The isolation structure 24b covers another portion of the well region 16 and extends over a portion of the well region 12 and the well region 18. The isolation structures 24c and 24d are located on a portion of the well region 12 on one side of the well region 18. The isolation structure 24c is located between the well region 18 and the isolation structure 24d. The isolation structures 24a, 24b, 24c, 24d are insulating materials such as undoped yttrium oxide, tantalum nitride or combinations thereof.

The gate structure 30 includes a gate dielectric layer 26 and a gate conductor layer 28. The gate structure 30 is located on the substrate 12, covering a portion of the well region 18, the well region 12, and the gate structure 30 can extend over the isolation structure 24c. There is also a spacer 32 on the sidewall of the gate structure 30. The material of the spacer 32 is, for example, ruthenium oxide, tantalum nitride or a combination thereof.

The source region 34 and the drain region 36 have a first conductivity type, such as an N-type source region and an N-type drain region (N+). The source region 34 and the drain region 36 are respectively located in the substrate 10 on both sides of the isolation structure 24c and the gate structure 30, wherein the source region 34 is close to the gate structure 30, and the drain region 36 is close to the isolation structure 24c. More specifically, the source region 34 is located in the well region 18 on one side of the gate structure 30. The drain region 36 is located in the well region 12 between the isolation structure 24c and the isolation structure 24d. The doping concentration of the source region 34 and the drain region 36 is, for example, 1 ́10 ¹⁴ /cm ² to 9 ^{́10 16} /cm ² .

The doped regions 38, 40 have a second conductivity type, such as a P-type heavily doped region (P+). Doped region 38 is located in well region 18 between isolation structure 24b and source region 34. Doped region 40 is located in well region 16. The doping concentration of the doping regions 38, 40 is, for example, 1 ́10 ¹⁴ /cm ² to 9 ^{́10 16} /cm ² .

The top layer 20 has a second conductivity type, such as a P-type top layer (P-Top). The top layer 20 is located in the well region 12 below the isolation structure 24c for raising the breakdown voltage. The step layer 22 has a first conductivity type, such as an N-grade layer. The step 22 is located between the top layer 20 and the isolation structure 24c to reduce the on-resistance. The doping concentration of the ladder layer 22 is not less than the doping concentration of the well region 12. The doping concentration of the top layer 20 is, for example, 1 ^{́10 11} /cm ² to 9 ́10 ¹³ /cm ² . The doping concentration of the step layer 22 is, for example, 1 ^{́10 11} /cm ² to 9 ́10 ¹³ /cm ² .

In one embodiment, the metal interconnect 60 includes a dielectric layer 42, contact windows 44a-44e, conductor layers (or first metal layers) 46a-46d, dielectric layer 48, vias 52a-52b, and conductors. Layer (or top metal layer) 50a~50b, but not limited to this. In other embodiments, the metal interconnect 60 may further include a plurality of conductor layers (or metal layers) between the conductor layers 46a-46d and the conductor layers 50a-50b and a plurality of vias. The conductor layer 46a is electrically connected to the doping region 40 through the contact window 44a. The conductor layer 46b is electrically connected to the doping region 38 and the source region 34 through the contact windows 44b and 44c, respectively. The conductor layer 46c is electrically connected to the gate conductor layer 28 via the contact window 44d. The conductor layer 46d is electrically connected to the drain region 36 via the contact window 44e.

The conductor layers 50a and 50b may be the uppermost metal layer of the metal interconnect 60, and are electrically connected to the conductor layers 46a to 46d via the vias 52a to 52b. The conductor layer 50a may be referred to as a source metal layer, extending at least from above the source region 34 (or from the isolation structure 24b) to the isolation structure 24c, and electrically connected through the via window 52a, the conductor layer 46b, and the contact window 44c. Source region 34. The conductor layer 50b may be referred to as a gate metal layer, extending at least from above the isolation structure 24c to the isolation structure 24d, and electrically connected to the drain region 36 through the via 52b, the conductor layer 46d and the contact window 44e.

Referring to FIG. 1 and FIG. 2G, the width W1 of the portion of the conductor layer 50a covering the isolation structure 24c on the first region 100 is such that the conductor layer 50a of the first region 100 corresponds to the end point OP1 of the isolation structure 24c to the conductor layer. The distance of the edge of 50a (adjacent conductor layer 50b). The width W2 of the portion of the second region 200 covering the conductor layer 50a of the isolation structure 24c is such that the conductor layer 50a of the second region 200 corresponds to the end point OP2 of the isolation structure 24c to the conductor layer 50a (adjacent to the conductor layer 50b). The distance from the edge. In the present embodiment, the width W2 of the portion of the conductor layer 50a on the second region 200 is larger than the width W1 of the portion of the conductor layer 50a on the first region 100, that is, W2 > W1. The width W2 is, for example, 1.5 to 5 times the width W1.

From the top view of FIG. 1, from the region 100 to the region 200, the curvature of the contour of the source region 34 is increased. In the present embodiment, the width of the portion of the conductor layer 50a covering the isolation structure 24c is also gradually increased from the region 100 to the region 200, so that the conductor layer 50a has a smooth profile (as shown in FIG. 1). In another embodiment (not shown), the width of the portion of the conductor layer 50a covering the isolation structure 24c may also gradually increase from the region 100 to the region 200 such that the conductor layer 50a has a stepped profile.

In the above embodiment, on the first region 100 of the substrate 10 is a linear region of the semiconductor element 99; on the second region 200 of the substrate 10 is a turning region of the semiconductor element 99. However, the present invention is not limited thereto as long as the curvature of the outline of the source region 34 of the portion of the semiconductor element 99 on the second region 200 is greater than the source region of the portion of the semiconductor device 99 on the first region 100. The curvature of the outline of 34 is the scope covered by the present invention.

2A to 2G are schematic cross-sectional views showing a method of fabricating a semiconductor device in accordance with an embodiment of the present invention.

Referring to FIG. 2A, a substrate 10 is provided. The substrate 10 includes a first region 100 and a second region 200. Next, a patterned mask layer 102 is formed on the substrate 10. The material of the patterned mask layer 102 is, for example, a photoresist or a dielectric material. Thereafter, the patterned mask layer 102 is used as an implant mask to perform an ion implantation process to form a well region 12 having a first conductivity type in the substrate 10. The well zone 12 is, for example, the N well. The doping implanted by the ion implantation process is, for example, phosphorus or arsenic, and the doping dose is, for example, 1 ^{́10 11} /cm ² to 9 ́10 ¹³ /cm ² , and the implanted energy is, for example, 50 KeV to 200 KeV. .

Thereafter, referring to FIG. 2B, the patterned mask layer 102 is removed. Thereafter, a patterned mask layer 104 is formed on the substrate 10. The material of the patterned mask layer 104 is, for example, a photoresist or a dielectric material. Thereafter, the patterned mask layer 104 is used as an implant mask to perform an ion implantation process to form well regions 16 and 18 having a second conductivity type in the substrate 10. The well areas 16, 18 are for example P wells. The doping implanted by the ion implantation process is, for example, boron, and the doping dose is, for example, 1 ^{́10 11} /cm ² to 9 ́10 ¹³ /cm ² , and the implanted energy is, for example, 50 KeV to 200 KeV.

Thereafter, referring to FIG. 2C, the patterned mask layer 104 is removed. A patterned mask layer 106 is then formed on the substrate 10. The material of the patterned mask layer 106 is, for example, a photoresist or a dielectric material. Thereafter, the patterned mask layer 106 is used as an implant mask to perform an ion implantation process to form a top layer 20 having a second conductivity type in the substrate 10. The top layer 20 is, for example, a P-type top layer. The doping implanted by the ion implantation process is, for example, boron, and the doping dose is, for example, 1 ^{́10 11} /cm ² to 9 ́10 ¹³ /cm ² , and the implanted energy is, for example, 50 KeV to 200 KeV.

Next, referring to FIG. 2C, the patterned mask layer 106 is used as an implant mask to perform an ion implantation process to form a step layer 22 having a first conductivity type in the substrate 10. The step layer 22 is, for example, an N-type ladder layer. The doping implanted by the ion implantation process is, for example, phosphorus or arsenic, and the doping dose is, for example, 1 ^{́10 11} /cm ² to 9 ́10 ¹³ /cm ² , and the implanted energy is, for example, 50 KeV to 200 KeV. .

Thereafter, referring to FIG. 2D, the patterned mask layer 106 is removed. Isolation structures 24a, 24b, 24c, 24d are then formed to define the active regions. The material of the isolation structures 24a, 24b, 24c, 24d is, for example, undoped cerium oxide, which can be formed by field oxidation isolation or shallow trench isolation. The thickness of the isolation structures 24a, 24b, 24c, 24d is, for example, 100 nm to 800 nm.

Thereafter, referring to FIG. 2E, a gate structure 30 is formed on the substrate 10 adjacent to the isolation structure 24c. In an embodiment, the gate structure 30 also extends to cover a portion of the isolation structure 24c. The gate structure 30 includes a gate dielectric layer 26 and a gate conductor layer 28. The material of the gate dielectric layer 26 can be, for example, a low dielectric constant material or a high dielectric constant material. A low dielectric constant material refers to a dielectric material having a dielectric constant of less than 4, such as cerium oxide or cerium oxynitride. The high dielectric constant material refers to a dielectric material having a dielectric constant higher than 4, such as HfAlO, HfO ₂ , Al ₂ O ₃ or Si ₃ N ₄ . The formation method is, for example, a thermal oxidation method or a chemical vapor deposition method. The gate conductor layer 28 includes polysilicon, a metal, a metal halide, or a combination thereof, and is formed by, for example, a chemical vapor deposition method.

Thereafter, a spacer 32 is formed on the sidewall of the gate structure 30. The material of the spacer 32 is, for example, ruthenium oxide, tantalum nitride or a combination thereof. The method of forming may first form a layer of spacer material, and then perform an anisotropic etching.

Thereafter, a source region 34 having a first conductivity type is formed in the well region 18 on the side of the gate structure 30, and is formed in the well region 12 on the other side of the gate structure 30 (or the isolation structure 24c). A conductive type drain region 36. The method of forming the source region 34 and the drain region 36 may form a patterned mask layer (not shown) and then be formed by an ion implantation process. The source region 34 and the drain region 36 are, for example, N-type heavily doped regions. The doping implanted by the ion implantation process is, for example, phosphorus or arsenic, and the doping dose is, for example, 1 ́10 ¹⁴ /cm ² to 9 ^{́10 16} /cm ² , and the implanted energy is, for example, 50 KeV to 200 KeV. .

Thereafter, referring to FIG. 2F, a doped region 38 having a second conductivity type is formed in the well region 18, and a doped region 40 having a second conductivity type is formed in the well region 16. The method of forming the doped regions 38, 40 can be formed by forming a patterned mask layer (not shown) and then performing an ion implantation process. The doped regions 38, 40 are, for example, P-type doped regions. The doping implanted by the ion implantation process is, for example, boron, and the doping dose is, for example, 1 ́10 ¹⁴ /cm ² to 9 ^{́10 16} /cm ² , and the implanted energy is, for example, 50 keV to 200 keV.

Next, referring to FIG. 2G, a metal interconnect 60 is formed on the substrate 10. In the present embodiment, the metal interconnect 60 includes a dielectric layer 42, contact windows 44a-44e, conductor layers (or first metal layers) 46a-46d, dielectric layer 48, vias 52a-52b, and conductors. Layer (or top metal layer) 50a~50b, but not limited to this. In an embodiment, the method of forming the metal interconnect 60 includes the following steps. The dielectric layer 42 can be formed prior to the substrate 10. Next, contact windows 44a to 44e are formed in the dielectric layer 42. Thereafter, conductor layers 46a to 46d are formed on the dielectric layer 42. Thereafter, a dielectric layer 48 is formed on the substrate 10, and vias 52a-52b are formed in the dielectric layer 48. Thereafter, conductor layers (or top metal layers) 50a to 50b are formed on the dielectric layer 48. The material of the dielectric layer 42 and the dielectric layer 48 is, for example, hafnium oxide, tantalum nitride, hafnium oxynitride or a low dielectric constant material having a dielectric constant of less than 4. The method of forming is, for example, chemical vapor deposition or spin coating. law. The materials of the contact windows 44a to 44e and the vias 52a to 52b are, for example, aluminum, tungsten or an alloy thereof, and are formed by, for example, chemical vapor deposition or physical vapor deposition. The contact windows 44a-44e are formed by, for example, forming a contact opening in the dielectric layer 42, depositing a layer of conductive material in the contact opening, and then performing an etch back or chemical mechanical polishing process to remove the dielectric layer 42. A portion of the conductor material layer outside the opening of the contact window. The forming method of the vias 52a to 52b is similar to the method of forming the contact windows 44a to 44e, and will not be described herein. The method of forming the conductor layers 46a to 46d and the conductor layers 50a to 50b is, for example, forming a conductor material layer separately, and then patterning by a lithography and etching process. The layer of conductor material may be a metal or a metal alloy such as aluminum, tungsten or alloys thereof. The method of forming the conductor material layer is, for example, a chemical vapor deposition method or a physical vapor deposition method. The method of forming the metal interconnect 60 is not limited thereto. In another embodiment, the metal interconnect 60 can also be formed by damascene.

After the metal interconnect 60 is formed, a protective layer (not shown) may be further formed on the substrate 10 to cover the conductive layers 50a-50b and the dielectric layer 48. The protective layer can be a single layer or a two layer structure. The material of the protective layer may be an inorganic material, an organic material, or a combination thereof. The inorganic material is, for example, cerium oxide, cerium nitride or a combination thereof. The organic material is, for example, polyimine (PI).

3 and FIG. 4 respectively show leakage current curves and breakdown voltage curves of three kinds of semiconductor elements tested in the electrostatic discharge protection element 2kV, and the semiconductor elements are covered at respective turning regions (eg, the second region 200 of FIG. 2G). The width W2 of the portion of the conductor layer 50a of the isolation structure 24c is different. The width W2 of the semiconductor element may be a, b, c (where a < b < c).

The experimental results show that the smaller the width of the portion of the conductor layer covering the isolation structure at the source end, the smaller the leakage current and the larger the breakdown voltage. In other words, the 700V semiconductor component of the present invention can be tested by the electrostatic discharge protection component 2kV as long as the width of the portion of the conductor layer covering the isolation structure at the source end is appropriately adjusted. In practical applications, the structure of the present invention can be applied to an ultrahigh voltage semiconductor element having an operating voltage of 300V to 1000.

In summary, in the present invention, the width of the portion covering the conductor layer of the isolation structure is adjusted to a different width depending on different regions in the semiconductor element. For example, the width of the source region is larger or the width of the conductor layer (such as the uppermost metal layer) at the corner is increased to be larger than the conductor layer having a smaller curvature or straight line in the source region (eg, the uppermost layer). The width of the metal layer). In other words, increasing the area of the source region with a larger curvature or a conductor layer at the corner (such as the uppermost metal layer) can effectively uniformly disperse the high electric field there. In this way, a semiconductor element capable of providing a high breakdown electric field, low leakage current, and high electrostatic discharge protection can be provided.

Furthermore, the method of fabricating the semiconductor device of the present invention can change the mask of the pattern defining the conductor layer (such as the uppermost metal layer), that is, the conductor layer (such as the uppermost metal layer) having a larger curvature or a corner can be added. The width (or area) can effectively disperse the high electric field there, reduce the electric field of collapse, and reduce the leakage current, so the ability of electrostatic discharge protection can be improved.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the invention, and any one of ordinary skill in the art can make some modifications and refinements without departing from the spirit and scope of the invention. The scope of the invention is defined by the scope of the appended claims.

10‧‧‧Base
12, 14, 16, 18, 32‧‧‧ well areas
20‧‧‧ top
22‧‧‧Layer
24a~24d‧‧‧Isolation structure
26‧‧‧gate dielectric layer
28‧‧‧ gate conductor layer
30‧‧‧ gate structure
32‧‧‧ spacer
34‧‧‧ source area
36‧‧‧Bungee Area
38, 40‧‧‧Doped area
42, 48‧‧‧ dielectric layer
44a~44e‧‧‧Contact window
46a~46d, 50a~50b‧‧‧ conductor layer
52a~52b‧‧・Intermediate window
60‧‧‧Metal interconnection
99‧‧‧Semiconductor components
100‧‧‧First District
200‧‧‧Second District
104, 106‧‧‧ mask
W1, W2, W3, W4‧‧‧ width
OP1, OP2‧‧‧ endpoint
II, II-II‧‧‧ Tangent

1 is a top plan view of a semiconductor device in accordance with an embodiment of the present invention. 2A to 2G are schematic cross-sectional views showing a method of fabricating a semiconductor device in accordance with an embodiment of the present invention, wherein Fig. 2G is a cross-sectional view taken along line I-I and II-II of Fig. 1. Fig. 3 is a graph showing leakage currents of three kinds of semiconductor elements tested in the electrostatic discharge protection element 2kV, which have different widths at portions of the conductor layers covering the isolation structures at respective source terminals. 4 is a breakdown voltage curve of three kinds of semiconductor elements tested in the electrostatic discharge protection element 2kV, which have different widths at portions of the conductor layers covering the isolation structures at respective source terminals.

24c‧‧‧Isolation structure

30‧‧‧ gate structure

34‧‧‧ source area

36‧‧‧Bungee Area

50a, 50b‧‧‧ conductor layer

60‧‧‧Metal interconnection

99‧‧‧Semiconductor components

100‧‧‧First District

200‧‧‧Second District

W1, W2‧‧‧ width

OP1, OP2‧‧‧ endpoint

I-I, II-II‧‧‧ tangent

Claims (8)

A semiconductor device comprising: a source region having a first conductivity type and a drain region having the first conductivity type in a substrate; and an isolation structure located in the source region and the drain region a gate structure on the substrate between the source region and the isolation structure; a conductor layer above the substrate, extending at least from above the source region to above the isolation structure, and electrically connected The source region, wherein the conductor layer is an uppermost metal layer, the substrate includes a first region and a second region, and a curvature of a contour of the source region in the second region is greater than in the first region a curvature of a contour of the source region, and a width of a portion of the second region covering the conductor layer of the isolation structure is greater than a width of a portion of the first region covering the conductor layer of the isolation structure. The semiconductor device of claim 1, wherein the semiconductor device comprises a plurality of linear regions and a plurality of turning regions, one of the linear regions being located in the first region; wherein one of the turning regions is located Second district. The semiconductor device of claim 1, further comprising: a top layer having a second conductivity type in the substrate under the isolation structure; and a ladder layer having the first conductivity type Between the top layer and the isolation structure. The semiconductor device of claim 1, further comprising: a first well region having a second conductivity type, located in the substrate, wherein the source a pole region is located in the first well region, and the gate structure covers a portion of the first well region; a doped region having the second conductivity type is located in the first well region adjacent to the source region And interconnecting the conductor layer with the source region; and a second well region having the first conductivity type is located in the substrate, wherein the first well region and the drain region are located in the second well region. A method of fabricating a semiconductor device, comprising: forming an isolation structure on a substrate; forming a gate structure on the substrate; forming a first conductive layer in the substrate on both sides of the gate structure and the isolation structure a source region and a drain region having the first conductivity type, wherein the source region is adjacent to the gate structure, the drain region is adjacent to the isolation structure; a conductor layer is formed over the substrate, the conductor The layer extends from above the source region to the upper portion of the isolation structure, and is electrically connected to the source region, wherein the conductor layer is an uppermost metal layer, and the substrate includes a first region and a second region. a curvature of a contour of the source region of the second region is greater than a curvature of a contour of the source region of the first region, and a width of a portion of the second region covering the conductor layer of the isolation structure is greater than the first region A portion of the conductor layer covering the isolation structure. The method of manufacturing a semiconductor device according to claim 5, wherein the semiconductor device comprises a plurality of linear regions and a plurality of turning regions, one of the linear regions being located in the first region; and one of the turning regions Located in the second zone. The method for fabricating a semiconductor device according to claim 5, further comprising: forming a top layer having a second conductivity type in the substrate under the isolation structure; and forming a top layer and the isolation structure A step layer having the first conductivity type. The method for manufacturing a semiconductor device according to claim 5, further comprising: forming a first well region having a second conductivity type in the substrate, wherein the source region is located in the first well region, And the gate structure covers a portion of the first well region; forming a doped region having the second conductivity type in the first well region, the doped region being adjacent to the source region, and the source region The region is commonly connected to the conductor layer; and a second well region having the first conductivity type is formed in the substrate, wherein the first well region and the drain region are located in the second well region.