CN109300790A - 具有牺牲多晶硅层的接触蚀刻停止层 - Google Patents

具有牺牲多晶硅层的接触蚀刻停止层 Download PDF

Info

Publication number
CN109300790A
CN109300790A CN201810679506.8A CN201810679506A CN109300790A CN 109300790 A CN109300790 A CN 109300790A CN 201810679506 A CN201810679506 A CN 201810679506A CN 109300790 A CN109300790 A CN 109300790A
Authority
CN
China
Prior art keywords
layer
sacrifice
gate structure
polysilicon layer
nitride
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN201810679506.8A
Other languages
English (en)
Other versions
CN109300790B (zh
Inventor
黄海苟
高金晟
盛海峰
刘金平
高明哈
臧辉
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
GlobalFoundries US Inc
Original Assignee
GlobalFoundries Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by GlobalFoundries Inc filed Critical GlobalFoundries Inc
Publication of CN109300790A publication Critical patent/CN109300790A/zh
Application granted granted Critical
Publication of CN109300790B publication Critical patent/CN109300790B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66545—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02164—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon oxide, e.g. SiO2
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/0217—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/02227—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
    • H01L21/0223—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/02227—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
    • H01L21/0223—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate
    • H01L21/02233—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer
    • H01L21/02236—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer group IV semiconductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
    • H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
    • H01L21/0228—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition deposition by cyclic CVD, e.g. ALD, ALE, pulsed CVD
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02296—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
    • H01L21/02318—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment
    • H01L21/02321—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment introduction of substances into an already existing insulating layer
    • H01L21/02323—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment introduction of substances into an already existing insulating layer introduction of oxygen
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02524—Group 14 semiconducting materials
    • H01L21/02532—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02587—Structure
    • H01L21/0259—Microstructure
    • H01L21/02595—Microstructure polycrystalline
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/32105—Oxidation of silicon-containing layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76837—Filling up the space between adjacent conductive structures; Gap-filling properties of dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823418—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823431—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
    • H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823437—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes

Abstract

本发明涉及具有牺牲多晶硅层的接触蚀刻停止层，该接触蚀刻停止层包括形成于牺牲栅极结构上面的氮化物层与形成于该氮化物层上面的多晶硅层。在后续制程期间，该多晶硅层适合氧化且形成氧化物层。该多晶硅层的氧化有效遮蔽底下的氮化物接触蚀刻停止层免受氧化，这保护该氮化物层的机械完整性。

Description

具有牺牲多晶硅层的接触蚀刻停止层
技术领域
本申请大体涉及半导体装置，且更特别的是，涉及例如场效晶体管的晶体管及其制法。
背景技术
制造例如场效晶体管(field effect transistor；FET)的半导体装置通常涉及由层沉积、图案化及蚀刻组成的多个步骤以在衬底上界定各种结构。使用例如间隔体及帽盖层的整合方案可用来精确地界定各个导电及绝缘结构，从而最小化相邻导电结构之间的泄漏以改善装置效能。
在某些办法中，接触蚀刻停止层(contact etch stop layer；CESL)可加入制造方案使得有可能选择性移除一或更多层。不过，充分选择性蚀刻制程的无法利用，且跟着接触蚀刻停止层可能受损而导致受保护层受损，这对制造生产量及良率有不利影响。
发明内容
鉴于上述，揭露一种方法用于形成具有改良接触蚀刻停止层的半导体结构。该接触蚀刻停止层包括多晶硅牺牲层。在可能氧化及损伤接触蚀刻停止层和接触蚀刻停止层底下诸层的制程期间，该多晶硅层本身可氧化且抑制这些层的氧化。
根据本申请的具体实施例，一种制造装置的方法包括形成一牺牲栅极结构于一半导体衬底上面，其中该牺牲栅极结构包括一牺牲栅极与形成于该牺牲栅极上面的一牺牲栅极间隙，形成一侧壁间隔体层于该牺牲栅极结构的多个侧壁上面，且形成一氮化物接触蚀刻停止层于该侧壁间隔体层上面。然后，形成一多晶硅层于该氮化物层的多个上部上面，且形成一氧化物层于该多晶硅层上面，其中，在该氧化物层的形成期间，该多晶硅层会被氧化。
根据另一方法，在一半导体衬底上面形成各自包括一牺牲栅极与形成于该牺牲栅极上面的一牺牲栅极间隙的多个牺牲栅极结构。形成一侧壁间隔体层于该多个牺牲栅极结构的侧壁上面，且形成一氮化物接触蚀刻停止层于该侧壁间隔体层上面。
该方法更包括：形成一流动性氧化物层于在相邻牺牲栅极结构之间的间隙内且于该氮化物层的多个下部上面，形成一多晶硅层于该氮化物层的多个上部上面，且形成一高密度电浆(HDP)氧化物层于该多晶硅层上面，致使该多晶硅层在该HDP氧化物层的形成期间被氧化。
附图说明
阅读时结合下列附图可充分明白以下本申请的特定具体实施例的详细说明，其中类似的结构用相同的元件符号表示。
图1的透射电子显微镜(transmission electron microscope；TEM)显微图图示包括共形氮化物接触蚀刻停止层的半导体结构，该共形氮化物接触蚀刻停止层是在用流动性介电质材料填满相邻牺牲栅极结构之间的间隙以及使介电质材料凹陷之后设置于相邻牺牲栅极结构上面；
图2的透射电子显微镜(TEM)显微图图示图1的结构的多个部分，包括氮化物接触蚀刻停止层及底下侧壁间隔体层在高密度电浆沉积一氧化物层于在相邻牺牲栅极结构之间的多个凹陷区中后的崩解(breakdown)；
图3为根据各种具体实施例的半导体结构的透射电子显微镜(TEM)显微图，其图示邻接牺牲栅极结构的氮化物接触蚀刻停止层及底下侧壁间隔体层在形成牺牲多晶硅层和高密度电浆沉积一氧化物层于多个凹陷区中且于在相邻牺牲栅极结构之间的多晶硅层上面后的存留(retention)；
图4为装置架构的横截面示意图，其根据各种具体实施例图示沉积氮化物接触蚀刻停止层于相邻牺牲栅极结构上面，以及图示后续沉积流动性氧化物层于在栅极结构之间的间隙中；
图5的横截面示意图图示在流动性氧化物层的凹陷蚀刻(recess etch)后的图4的装置架构；
图6图示沉积共形多晶硅层于凹陷流动性氧化物层上面且于牺牲栅极结构上面，包括直接于氮化物接触蚀刻停止层的多个上部上面；
图7图示沉积高密度电浆氧化物直接于多晶硅层上面且于在相邻牺牲栅极结构之间的间隙的多个上部中以及多晶硅层的伴随氧化；以及
图8图示高密度电浆氧化物的平坦化。
符号说明
100 半导体衬底或衬底
120 半导体鳍片或鳍片
140 浅沟槽隔离层
210 源极/漏极接面
300 牺牲栅极结构
310 牺牲栅极或多晶硅栅极
320 牺牲栅极帽盖
410 侧壁间隔体
510 氮化物接触蚀刻停止层(CESL)或氮化物层
520 牺牲多晶硅层或多晶硅层
530 氧化物层
610 流动性氧化物层、沉积层或介电层
620 高密度电浆(HDP)氧化物层、氧化物层或介电层
800 间隙。
具体实施方式
此时参考本申请的专利标的的各种具体实施例的更详细细节，附图图示本发明的一些具体实施例。诸图用相同的元件符号表示相同或类似的部件。
揭露于各种具体实施例的是一种制造半导体装置的方法，例如具有改良接触蚀刻停止层的鳍片场效晶体管(FinFET)装置。可给合栅极最后(gate last)或取代金属栅极(replacement metal gate；RMG)制程实施所揭露的方法。用于制造取代金属栅极(RMG)晶体管的典型制程流程包括形成暂时性或牺牲栅极，形成附加晶体管结构，然后移除牺牲栅极留下沉积各种材料层(例如，栅极介电质及栅极导体材料)于其中以形成功能栅极的沟槽。此办法延后形成栅极直到在可能损害栅极材料的制程之后，例如暴露于升高温度及/或离子植入。如本文所使用的，“功能栅极”指用来使用电场或在某些情况下使用磁场控制半导体装置的输出电流(亦即，通过通道的载子流动)的结构，且包括栅极介电质与栅极导体。
根据各种具体实施例，该方法包括形成牺牲多晶硅层于氮化物接触蚀刻停止层(CESL)上面。该多晶硅层适合在后续制程期间优先氧化底下氮化物层及侧壁间隔体层。因此，该氮化物接触蚀刻停止层及侧壁间隔体层在一或更多制程步骤期间可有效保护各种装置特征。特别是，该CESL适合在接触蚀刻期间限制特定区域(例如，在相邻栅极结构之间)的蚀刻。该CESL对于随后用来蚀刻将会形成接触的区域的化学物应有良好的抗蚀刻性。
在各种具体实施例中，该多晶硅层从在相邻牺牲栅极结构之间的位置内直接形成于氮化物接触蚀刻停止层上面，亦即，于在凹陷蚀刻流动性氧化物后横向邻接牺牲栅极堆迭的氮化物接触蚀刻停止层(CESL)的多个上部上面。本案申请人已发现，在后续制程期间，相对于氮化物CESL层的氧化选择性地进行多晶硅层的氧化，这可保护氮化物CESL层的完整性且抑制牺牲栅极的非所欲腐蚀。
图1的透射电子显微镜(TEM)显微图图示包括设置于浅沟槽隔离层140上面的多个牺牲栅极结构300的装置架构。图1图示在主动装置区之间的横截面图，亦即，图示沿着在相邻平行半导体鳍片之间的非接触横截面。
牺牲栅极结构300各自包括牺牲栅极310与形成于牺牲栅极310上面的牺牲栅极帽盖(sacrificial gate cap)320。如本领域技术人员所知，牺牲栅极310可包括非晶硅或多晶硅，且牺牲栅极帽盖320可包括氮化物层，例如氮化硅。
侧壁间隔体410设置在牺牲栅极结构300的侧壁(垂直面)上面。侧壁间隔体410的形成可通过毯覆沉积间隔体材料，接着是定向蚀刻(directional etch)，例如反应性离子蚀刻(reactive ion etching；RIE)，以从水平面移除间隔体材料。合适侧壁材料包括氧化物、氮化物及氮氧化物，例如二氧化硅、氮化硅、氮氧化硅、及低电介质常数(低k)材料，例如非晶碳、碳氧化硅(SiOC)、氮碳氧化硅(SiOCN)及氮碳硼化硅(SiBCN)，以及低k介电质材料。如本文所使用的，低k材料具有小于二氧化硅的电介质常数。在某些具体实施例中，侧壁间隔体410的厚度为4到20纳米，例如4、10、15或20纳米，包括在上述数值中的任一者之间的范围。
共形氮化物接触蚀刻停止层510设置在位于相邻牺牲栅极结构300之间的侧壁间隔体410上面。在某些具体实施例中，氮化物接触蚀刻停止层510的厚度可在2至6纳米之间，例如2、4或6纳米，包括在上述数值中的任一者之间的范围。氮化物接触蚀刻停止层510例如可由原子层沉积(atomic layer deposition；ALD)形成。
如本文所述，层或结构的形成或沉积可能涉及适用于被沉积的材料或层或被形成的结构的一或更多技术。此类技术包括但不限于：化学气相沉积(chemical vapordeposition；CVD)、低压化学气相沉积(low pressure chemical vapor deposition；LPCVD)、电浆增强化学气相沉积(plasma enhanced chemical vapor deposition；PECVD)、金属有机CVD(metal organic CVD；MOCVD)、原子层沉积(ALD)、分子束磊晶(molecularbeam epitaxy；MBE)、电镀、无电电镀、离子束沉积及物理气相沉积(physical vapordeposition；PVD)技术，例如溅镀或蒸镀。
在各种具体实施例中，由彼此可选择性地蚀刻的材料形成侧壁间隔体410及氮化物CESL层510。在多个特定具体实施例中，侧壁间隔体410包含氮碳氧化硅(SiOCN)，以及氮化物接触蚀刻停止层510包含氮化硅。
此外，应了解，氮化硅与二氧化硅的化合物有各自标称表示为Si3N4及SiO2的组成物。用语氮化硅及二氧化硅不仅指称这些化学计量组成物，也指偏离化学计量组成物的氮化物及氧化物组成物。
在一示范实施例中，如部分图示于图1，直接沉积一层流动性氧化物610于氮化物接触蚀刻停止层510上面以填满在牺牲栅极结构300之间的间隙。在各种具体实施例中，流动性材料至少部分填满间隙然后被转换成二氧化硅膜。此一制程可用来填满高深宽比(high aspect ratio)的间隙，包括深宽比在3：1到10：1之间的间隙。
在各种方法中，使用一或更多含硅前驱体与一氧化气体沉积流动性二氧化硅。示范硅前驱体材料包括但不限于：烷氧基硅烷(alkoxysilanes)，例如，四氧甲基环四硅氧烷(tetraoxymethylcyclotetrasiloxane；TOMCTS)，八甲基环四硅氧烷(octamethylcyclotetrasiloxane；OMCTS)，四乙氧基硅烷(tetraethoxysilane；TEOS)，三乙氧基硅烷(triethoxysilane；TES)，三甲氧基硅烷(trimethoxysilane；TriMOS)，甲基三乙氧基正硅酸盐(methyltriethoxyorthosilicate；MTEOS)，四甲基正硅酸盐(tetramethylorthosilicate；TMOS)，甲基三甲氧基硅烷(methyltrimethoxysilane；MTMOS)，二甲基二甲氧基硅烷(dimethyldimethoxysilane；DMDMOS)，二乙氧基硅烷(diethoxysilane；DES)，二甲氧基硅烷(dimethoxysilane，DMOS)，三苯基乙氧基硅烷(triphenylethoxysilane)，1-(三乙氧基硅烷基)-2-(二乙氧基甲基硅烷基)乙烷(1-(triethoxysilyl)-2-(diethoxymethylsilyl)ethane)，三第三丁氧基硅醇(tri-t-butoxylsilanol)。示范氧化气体包括但不限于：臭氧、过氧化氢、氧、水(蒸气)、及醇类，例如甲醇、乙醇及异丙醇。
在该流动性材料的沉积期间及/或之后，例如，可使用固化/退火制程，致密化(densify)沉积层610的一部分或全部。根据各种具体实施例，固化/退火制程涉及暴露于在氧化或惰性环境中的蒸气、热、紫外线(UV)、电子束(e-beam)、微波、雷射或电浆源。
尽管流动性氧化物的致密化退火(densification anneal)，然而用在贴近填充间隙的顶部(亦即，横向邻接牺牲栅极结构300的顶部)有品质较高、较密的氧化物取代流动性氧化物610可能是有利的，以便改善在后续制程期间填满间隙的暴露氧化物材料的抗蚀刻性。
再参考图1，流动性氧化物层610的凹陷蚀刻重新开放间隙在结构的顶部的一部分且暴露氮化物接触蚀刻停止层510的多个上部。参考图2，覆盖流动性氧化物层610的高密度电浆(HDP)氧化物620可形成于凹陷区内。HDP氧化物通常从合适的含硅前驱体在氧化条件下用高密度电浆化学气相沉积(HDP-CVD)沉积。
尽管在制造高密度氧化物上有效，然而用来形成高密度电浆(HDP)氧化物层620于凹陷流动性氧化物层610上面的制程条件可能蚀刻氮化物CESL 510的暴露部分，如图2所示。已观察到，与高密度电浆氧化物层620的沉积相关的氧化条件可能对氮化物层510及/或侧壁间隔体410有不利影响，导致这些层的抗蚀刻性崩解。在图示结构中，HDP氧化物沉积已部分移除氮化物CESL 510和横向邻接牺牲栅极310的顶部的底下侧壁间隔体410。
在氮化物层510及侧壁间隔体410的崩解导致暴露牺牲栅极310的上部的制程中，牺牲栅极310的相关损伤可能导致相邻接触的电气短路，例如，在随后形成于栅极间间隙(inter-gate gap)内的源极/漏极接触与上覆栅极的栅极接触之间。
应了解，图2的横截面图是沿着主动装置区绘出，亦即，沿着穿过半导体鳍片120的接触横截面，且图示上覆鳍片120(亦即，鳍片在源极/漏极接面210之间的通道区上面)的多个牺牲栅极结构300。
在各种具体实施例中，半导体装置可包含鳍片场效晶体管(FinFET)。在此类具体实施例中，通过图案化及蚀刻例如SOI衬底的复合衬底的半导体层或块状半导体衬底100的顶部，可形成一或更多半导体鳍片120。
例如，半导体衬底100可包含半导体材料，例如硅(Si)或含硅材料。含硅材料包括但不限于：单晶硅、多晶硅、单晶硅锗(SiGe)、多晶硅锗、掺有碳的硅(Si：C)、非晶硅、以及由彼等组成的组合及多层。
不过，半导体衬底100不限于含硅材料，因为衬底100可包含其他半导体材料，包括锗及化合物半导体，例如砷化镓(GaAs)、砷化铟(InAs)及其他类似半导体。半导体衬底100的多个部分可为非晶、多晶或单晶体。
用来形成鳍片120的蚀刻制程通常包含各向异性蚀刻。在某些具体实施例中，可使用干蚀刻制程，例如，反应性离子蚀刻(RIE)。在其他具体实施例中，可使用湿化学蚀刻剂。又在其他具体实施例中，可使用干蚀刻与湿蚀刻的组合。
例如，鳍片120可使用侧壁影像转移(sidewall image transfer；SIT)制程形成，这包括形成间隔体材料于心轴(mandrel)的侧壁表面上。该间隔体包括蚀刻选择性与心轴不同的材料，致使，在间隔体形成后，用蚀刻移除该心轴。然后，各间隔体在界定鳍片的后续蚀刻制程期间用作硬掩模。
半导体鳍片120通常平行配置且通过浅沟槽隔离层140互相横向隔离。增高式(raised)源极/漏极接面210设置在鳍片120贴近其顶面的部分上面(亦即，源极及漏极区)。如本领域技术人员所知，源极/漏极接面210可用离子植入或选择性磊晶形成，视需要使用牺牲栅极结构300作为对准掩模。例如，根据各种具体实施例，源极/漏极接面210用选择性磊晶形成于在牺牲栅极结构之间界定于鳍片上面的自对准空腔中。亦即，源极/漏极接面210形成于鳍片120在位于牺牲栅极结构300底下的通道区的任一侧上的源极及漏极区上面。
源极/漏极接面210可包含硅(例如，Si)或含硅材料，例如硅锗(SiGe)。例如，硅锗源极/漏极接面可并入p-MOS装置以提供压缩应力予通道，这可改善载子迁移率。
仍参考图2，可见，在源极/漏极接触位置内，亦即，在接触区内，氮化物接触蚀刻停止层510形成于侧壁间隔体410上面且于源极/漏极接面210上面。
参考图3，且根据各种具体实施例，在相邻牺牲栅极结构300之间与在源极/漏极接面210上面形成双重介电层610、620。可形成包括流动性氧化物层610与上覆高密度电浆氧化物层620的介电层而不有害地蚀刻氮化物CESL 510通过在使流动性氧化物层610凹陷之后和在沉积高密度电浆氧化物层620之前，形成牺牲多晶硅层直接于氮化物接触蚀刻停止层510上面。
参考图4至图8，描述一种形成改良CESL架构的方法。描述于此的是在形成高密度电浆氧化物层620之前，形成牺牲多晶硅层520于氮化物接触蚀刻停止层510上面的复合CESL层。在高密度电浆氧化物层620的沉积期间，多晶硅层520被原位氧化以形成附加氧化物层530。
根据各种具体实施例，一种制造例如FinFET装置的装置的方法，其包括形成牺牲栅极结构300于半导体衬底上面，其中牺牲栅极结构300包括牺牲栅极310与形成于牺牲栅极310上面的牺牲栅极间隙320。形成侧壁间隔体层410于牺牲栅极结构300的侧壁上面。然后，形成氮化物(CESL)层510于侧壁间隔体层410上面。该方法更包括：形成多晶硅层520于氮化物层510的多个上部上面，且形成例如HDP氧化物层620的氧化物层于多晶硅层520上面。在氧化物层620的形成期间，多晶硅层520被完全氧化。
图4为图示沉积共形氮化物接触蚀刻停止层510于牺牲栅极结构300上面的横截面示意图。如图所示，氮化物层510直接形成于在相邻牺牲栅极结构300之间的源极/漏极接面210上面且直接于侧壁间隔体410上面。ALD制程可用来形成氮化物层510。在相邻牺牲栅极结构300之间且在氮化物层510上面形成流动性氧化物层610。
图5的横截面示意图图示在凹陷蚀刻流动性氧化物层610以开放在相邻牺牲栅极结构300之间的间隙800之后的图4结构。在凹陷蚀刻流动性氧化物层610后，氮化物层510的多个部分被暴露。在各种具体实施例中，流动性氧化物层610的凹陷蚀刻暴露在牺牲栅极结构300的多个上部上面的氮化物层，致使暴露氮化物层510在间隙800内的多个上部，同时流动性氧化物层610的其余部分设置在氮化物层510的下部上面。
请参考图6，形成共形多晶硅层520于间隙800内且于牺牲栅极结构300上面。在图示具体实施例中，多晶硅层520直接形成于氮化物层510的多个上部上面，以及直接于牺牲栅极帽盖320的顶面上面。
可使用低压化学气相沉积(LPCVD)技术沉积多晶硅(多晶体硅)层520。例如，可用在低压高温分解(pyrolytic decomposition)硅烷气体来沉积LPCVD多晶硅层，然而可利用其他反应方法。
在凹陷蚀刻流动性氧化物层610和沉积牺牲多晶硅层520后，形成高密度电浆氧化物层620于间隙800内且于牺牲栅极结构300上面。高密度电浆氧化物层620直接形成于牺牲多晶硅层520上面。伴随高密度电浆氧化物层620的沉积的是多晶硅层520的氧化以形成附加氧化物层530。氧化物层530原位形成于牺牲栅极帽盖320的多个上部上面且于氮化物接触蚀刻停止层510的多个上部上面。在某些具体实施例中，多晶硅层520在HDP氧化物层620的沉积期间被完全氧化以形成氧化物层530致使没有多晶硅材料残留。
请参考图8，在沉积高密度电浆氧化物620后，可平坦化该结构。“平坦化”为至少运用例如磨擦媒介的机械力的材料移除制程，以产生实质二维表面。平坦化制程可包括化学机械研磨(chemical mechanical polishing；CMP)或磨光。化学机械研磨(CMP)为利用化学反应及机械力两者以移除材料且平坦化表面的材料移除制程。牺牲栅极帽盖320可用作平坦化制程的CMP蚀刻停止层。在图示具体实施例中，氧化物层620的顶面与牺牲栅极帽盖320的顶面共面。
再参考图3，通过保护氮化物CESL 510及侧壁间隔体410以免氧化，可避免在下游制程期间不必要地蚀刻或腐蚀多晶硅栅极310。
所揭示的方法提供一种复合接触蚀刻停止层(CESL)架构。用接触蚀刻停止层架构制成的装置有牺牲栅极腐蚀的减少倾向以及较少的接触间电气短路意外。用本方法制成的集成电路有改善的可靠性及效能，以及栅极与源极/漏极接触之间的泄漏最少，且电路故障的例子减少。
如本文所使用的，单数形式“一(a)”、“一(an)”、及“该(the)”旨在也包括复数形式，除非上下文中另有明确指示。因此，例如，“牺牲栅极结构”的引用包括有两个或更多此类“牺牲栅极结构”的实施例，除非上下文中另有明确指示。
除非另有明文规定，决非旨在提及于本文的任何方法被理解为它的步骤需要按照特定的顺序执行。相应地，在方法权利要求没有实际列举其步骤将会遵循的顺序或权利要求或说明中没有另外特别说明该等步骤受限于特定顺序时，决非旨在暗示任何特定顺序。任一权利要求中的任何列举单一或多个特征或方面可与任何其他权利要求或多个权利要求中的任何其他列举特征或方面排列或组合。
应了解，当指例如层、区域或衬底的元件形成、沉积或设置于另一元件“上”或“上面”时，它可直接在该另一元件上或者也可存在中介元件。相比之下，当指一元件“直接”在另一元件“上”或“上面”时，不存在中介元件。
尽管使用传统片语“包含(comprising)”可揭示特定具体实施例的各种特征、元件或步骤，然而应了解，替代具体实施例暗示包括可用传统片语“由…组成(consisting)”或“实质由…组成(consisting essentially of)”描述者。因此，例如，包含氮化硅的接触蚀刻停止层的暗示替代具体实施例包括接触蚀刻停止层实质由氮化硅组成的具体实施例与接触蚀刻停止层由氮化硅组成的具体实施例。
本领域技术人员明白，本发明可做出各种修改及变体而不脱离本发明的精神及范畴。由于体现本发明精神及主旨的修改、组合、次组合及变体对本领域技术人员而言可能出现，因此本发明应被视为涵盖在随附权利要求书及其等效陈述的范畴内的任何事物。

Claims (19)

1.一种制造装置的方法，其包含：
形成一牺牲栅极结构于一半导体衬底上面，其中，该牺牲栅极结构包括一牺牲栅极与形成于该牺牲栅极上面的一牺牲栅极间隙；
形成一侧壁间隔体层于该牺牲栅极结构的多个侧壁上面；
形成一氮化物层于该侧壁间隔体层上面；
形成一多晶硅层于该氮化物层的多个上部上面；以及
形成一氧化物层于该多晶硅层上面，其中，该多晶硅层在该氧化物层的形成期间被氧化。
2.如权利要求1所述的方法，其特征在于，该氮化物层由原子层沉积形成。
3.如权利要求1所述的方法，其特征在于，该氮化物层包含氮化硅。
4.如权利要求1所述的方法，其特征在于，该多晶硅层直接形成于该氮化物层的该多个上部上面。
5.如权利要求1所述的方法，其特征在于，该多晶硅层在该氧化物层的形成期间被完全氧化。
6.如权利要求1所述的方法，其特征在于，该多晶硅层直接形成于该牺牲栅极帽盖的一顶面上面。
7.如权利要求1所述的方法，进一步包含：在形成该多晶硅层之前，形成一流动性氧化物层于该氮化物层的多个下部上面。
8.如权利要求7所述的方法，其特征在于，该多晶硅层形成于该流动性氧化物层的一顶面上面且直接于该氮化物层的该多个上部上面横向邻接该牺牲栅极。
9.如权利要求1所述的方法，其特征在于，该氧化物层包含一高密度氧化物。
10.如权利要求1所述的方法，其特征在于，形成该牺牲栅极结构包含：形成多个牺牲栅极结构于该半导体衬底上面。
11.权利要求10所述的方法，进一步包含：在该多个牺牲栅极结构的相邻牺牲栅极结构之间形成一源极/漏极接面于该半导体衬底上面。
12.如权利要求11所述的方法，其特征在于，该氮化物层直接形成于该源极/漏极接面上面。
13.一种制造装置的方法，其包含：
形成多个牺牲栅极结构于一半导体衬底上面，其特征在于，该多个牺牲栅极结构各自包括一牺牲栅极与形成于该牺牲栅极上面的一牺牲栅极间隙；
形成一侧壁间隔体层于该牺牲栅极结构的多个侧壁上面；
形成一氮化物层于该侧壁间隔体层上面；
形成一流动性氧化物层于相邻牺牲栅极结构之间且于该氮化物层的多个下部上面；
形成一多晶硅层于该氮化物层的多个上部上面；以及
形成一氧化物层于该多晶硅层上面，其中，该多晶硅层在该氧化物层的形成期间被氧化。
14.如权利要求13所述的方法，进一步包含：在形成该多晶硅层之前，使该流动性氧化物层凹陷形成于该相邻牺牲栅极结构之间。
15.如权利要求13所述的方法，其特征在于，该多晶硅层在该氧化物层的形成期间被完全氧化。
16.如权利要求13所述的方法，其特征在于，该氧化物层包含一高密度氧化物。
17.如权利要求13所述的方法，进一步包含：在该相邻牺牲栅极结构之间形成一源极/漏极接面于该半导体衬底上面。
18.如权利要求17所述的方法，其特征在于，该氮化物层直接形成于该源极/漏极接面上面。
19.如权利要求13所述的方法，进一步包含：从该半导体衬底形成多个鳍片，以及形成该多个牺牲栅极结构于该多个鳍片上面。
CN201810679506.8A 2017-07-24 2018-06-27 具有牺牲多晶硅层的接触蚀刻停止层 Active CN109300790B (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US15/657,594 2017-07-24
US15/657,594 US9991363B1 (en) 2017-07-24 2017-07-24 Contact etch stop layer with sacrificial polysilicon layer

Publications (2)

Publication Number Publication Date
CN109300790A true CN109300790A (zh) 2019-02-01
CN109300790B CN109300790B (zh) 2021-11-02

Family

ID=62235584

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201810679506.8A Active CN109300790B (zh) 2017-07-24 2018-06-27 具有牺牲多晶硅层的接触蚀刻停止层

Country Status (3)

Country Link
US (1) US9991363B1 (zh)
CN (1) CN109300790B (zh)
TW (1) TWI670760B (zh)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10629739B2 (en) 2018-07-18 2020-04-21 Globalfoundries Inc. Methods of forming spacers adjacent gate structures of a transistor device
US11728405B2 (en) * 2019-09-28 2023-08-15 Taiwan Semiconductor Manufacturing Co., Ltd. Stress-inducing silicon liner in semiconductor devices

Citations (44)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000299380A (ja) * 1998-11-12 2000-10-24 Hyundai Electronics Ind Co Ltd 半導体素子のコンタクト形成方法
US6198144B1 (en) * 1999-08-18 2001-03-06 Micron Technology, Inc. Passivation of sidewalls of a word line stack
WO2001069665A1 (fr) * 2000-03-13 2001-09-20 Tadahiro Ohmi Procede de formation de pellicule dielectrique
CN1518112A (zh) * 2003-01-17 2004-08-04 ���ǵ�����ʽ���� 半导体器件及其制造方法
CN1567571A (zh) * 2003-07-10 2005-01-19 南亚科技股份有限公司 具有几何形状沟槽的沟槽型电容的制程
US6924180B2 (en) * 2003-02-10 2005-08-02 Chartered Semiconductor Manufacturing Ltd. Method of forming a pocket implant region after formation of composite insulator spacers
CN1666320A (zh) * 2002-07-08 2005-09-07 因芬尼昂技术股份公司 短沟道场效晶体管制造方法
US20060211200A1 (en) * 2005-03-15 2006-09-21 Oki Electric Industry Co., Ltd. Method of manufacturing semiconductor device
CN101064249A (zh) * 2006-04-30 2007-10-31 中芯国际集成电路制造(上海)有限公司 改进浅沟槽隔离间隙填充工艺的方法
CN101114615A (zh) * 2006-07-28 2008-01-30 国际商业机器公司 实现具有改进硅化物控制的双应力层的结构和方法
CN101165917A (zh) * 2006-10-18 2008-04-23 台湾积体电路制造股份有限公司 具有连续接触蚀刻停止层的金属氧化物半导体元件
KR20080060388A (ko) * 2006-12-27 2008-07-02 주식회사 하이닉스반도체 리프팅 방지를 위한 반도체 소자 및 그 제조방법
CN101231969A (zh) * 2007-01-26 2008-07-30 台湾积体电路制造股份有限公司 集成电路结构的形成方法
US7456062B1 (en) * 2004-10-20 2008-11-25 Advanced Micro Devices, Inc. Method of forming a semiconductor device
KR20080114241A (ko) * 2007-06-27 2008-12-31 주식회사 하이닉스반도체 반도체 소자의 제조방법
US7517766B2 (en) * 2006-09-12 2009-04-14 United Microelectronics Corp. Method of removing a spacer, method of manufacturing a metal-oxide-semiconductor transistor device, and metal-oxide-semiconductor transistor device
CN101635260A (zh) * 2008-07-24 2010-01-27 世界先进积体电路股份有限公司 半导体装置、晶体管及其制造方法
JP4417439B2 (ja) * 1994-06-29 2010-02-17 フリースケール セミコンダクター インコーポレイテッド エッチング・ストップ層を利用する半導体装置構造とその方法
US20100207196A1 (en) * 2009-02-16 2010-08-19 Shin Min Jung Semiconductor device having internal gate structure and method for manufacturing the same
US20100240182A1 (en) * 2007-01-15 2010-09-23 Sandisk Corporation Spacer Patterns Using Assist Layer For High Density Semiconductor Devices
CN101901751A (zh) * 2009-01-26 2010-12-01 半导体元件工业有限责任公司 半导体元件及其制造方法
CN102683190A (zh) * 2011-03-07 2012-09-19 中芯国际集成电路制造(上海)有限公司 一种金属栅极及mos晶体管的形成方法
US20130052787A1 (en) * 2011-08-23 2013-02-28 Samsung Electronics Co., Ltd. Method of manufacturing semiconductor device
CN103137451A (zh) * 2011-11-23 2013-06-05 中芯国际集成电路制造(上海)有限公司 一种半导体器件的制造方法
CN103515210A (zh) * 2012-06-20 2014-01-15 中芯国际集成电路制造(上海)有限公司 一种后栅极工艺晶体管及其形成方法
CN103545215A (zh) * 2012-07-17 2014-01-29 中国科学院微电子研究所 半导体器件及其制造方法
CN103579124A (zh) * 2012-08-08 2014-02-12 爱思开海力士有限公司 半导体器件的制造方法
CN103594414A (zh) * 2012-08-17 2014-02-19 华邦电子股份有限公司 沟槽隔离结构及其形成方法
CN103915341A (zh) * 2013-01-08 2014-07-09 中芯国际集成电路制造(上海)有限公司 晶体管及其形成方法
CN104022026A (zh) * 2013-03-01 2014-09-03 中芯国际集成电路制造(上海)有限公司 多晶硅栅极的形成方法
WO2014149682A1 (en) * 2013-03-19 2014-09-25 Applied Materials, Inc. Multilayer passivation or etch stop tft
US20140361364A1 (en) * 2013-06-05 2014-12-11 Taiwan Semiconductor Manufacturing Co., Ltd. Doped protection layer for contact formation
US20150021672A1 (en) * 2011-09-15 2015-01-22 Taiwan Semiconductor Manufacturing Company, Ltd. Contact for high-k metal gate device
CN104347485A (zh) * 2013-08-06 2015-02-11 中芯国际集成电路制造(上海)有限公司 一种半导体器件的制造方法
US20150061010A1 (en) * 2013-08-27 2015-03-05 International Business Machines Corporation Structure for improved contact resistance and extension diffusion control
CN104465347A (zh) * 2013-09-24 2015-03-25 北大方正集团有限公司 多晶硅表面处理方法及系统
CN104900706A (zh) * 2014-03-06 2015-09-09 三星显示有限公司 薄膜晶体管、其基板、显示设备及制造薄膜晶体管的方法
CN106257645A (zh) * 2015-06-16 2016-12-28 北大方正集团有限公司 Cmos器件的制作方法
CN106449643A (zh) * 2012-11-01 2017-02-22 北京芯盈速腾电子科技有限责任公司 非挥发性内存单元的制造方法
CN106601679A (zh) * 2015-10-15 2017-04-26 中芯国际集成电路制造(上海)有限公司 一种半导体器件及其制作方法、电子装置
CN106611696A (zh) * 2015-10-21 2017-05-03 国网智能电网研究院 一种碳化硅表面氧化膜的制备方法
CN106856172A (zh) * 2015-12-09 2017-06-16 中芯国际集成电路制造(上海)有限公司 鳍式场效应晶体管的形成方法
US9685385B1 (en) * 2016-07-05 2017-06-20 United Microelectronics Corp. Method of fabricating semiconductor device
US9685383B2 (en) * 2015-05-13 2017-06-20 United Microelectronics Corp. Method of forming semiconductor device

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6346468B1 (en) 2000-02-11 2002-02-12 Chartered Semiconductor Manufacturing Ltd. Method for forming an L-shaped spacer using a disposable polysilicon spacer
US6881616B1 (en) * 2001-12-14 2005-04-19 Advanced Micro Devices, Inc. System for forming a semiconductor device and method thereof including implanting through a L shaped spacer to form source and drain regions
US7405116B2 (en) 2004-08-11 2008-07-29 Lsi Corporation Application of gate edge liner to maintain gate length CD in a replacement gate transistor flow
US10134895B2 (en) * 2012-12-03 2018-11-20 Stmicroelectronics, Inc. Facet-free strained silicon transistor

Patent Citations (44)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4417439B2 (ja) * 1994-06-29 2010-02-17 フリースケール セミコンダクター インコーポレイテッド エッチング・ストップ層を利用する半導体装置構造とその方法
JP2000299380A (ja) * 1998-11-12 2000-10-24 Hyundai Electronics Ind Co Ltd 半導体素子のコンタクト形成方法
US6198144B1 (en) * 1999-08-18 2001-03-06 Micron Technology, Inc. Passivation of sidewalls of a word line stack
WO2001069665A1 (fr) * 2000-03-13 2001-09-20 Tadahiro Ohmi Procede de formation de pellicule dielectrique
CN1666320A (zh) * 2002-07-08 2005-09-07 因芬尼昂技术股份公司 短沟道场效晶体管制造方法
CN1518112A (zh) * 2003-01-17 2004-08-04 ���ǵ�����ʽ���� 半导体器件及其制造方法
US6924180B2 (en) * 2003-02-10 2005-08-02 Chartered Semiconductor Manufacturing Ltd. Method of forming a pocket implant region after formation of composite insulator spacers
CN1567571A (zh) * 2003-07-10 2005-01-19 南亚科技股份有限公司 具有几何形状沟槽的沟槽型电容的制程
US7456062B1 (en) * 2004-10-20 2008-11-25 Advanced Micro Devices, Inc. Method of forming a semiconductor device
US20060211200A1 (en) * 2005-03-15 2006-09-21 Oki Electric Industry Co., Ltd. Method of manufacturing semiconductor device
CN101064249A (zh) * 2006-04-30 2007-10-31 中芯国际集成电路制造(上海)有限公司 改进浅沟槽隔离间隙填充工艺的方法
CN101114615A (zh) * 2006-07-28 2008-01-30 国际商业机器公司 实现具有改进硅化物控制的双应力层的结构和方法
US7517766B2 (en) * 2006-09-12 2009-04-14 United Microelectronics Corp. Method of removing a spacer, method of manufacturing a metal-oxide-semiconductor transistor device, and metal-oxide-semiconductor transistor device
CN101165917A (zh) * 2006-10-18 2008-04-23 台湾积体电路制造股份有限公司 具有连续接触蚀刻停止层的金属氧化物半导体元件
KR20080060388A (ko) * 2006-12-27 2008-07-02 주식회사 하이닉스반도체 리프팅 방지를 위한 반도체 소자 및 그 제조방법
US20100240182A1 (en) * 2007-01-15 2010-09-23 Sandisk Corporation Spacer Patterns Using Assist Layer For High Density Semiconductor Devices
CN101231969A (zh) * 2007-01-26 2008-07-30 台湾积体电路制造股份有限公司 集成电路结构的形成方法
KR20080114241A (ko) * 2007-06-27 2008-12-31 주식회사 하이닉스반도체 반도체 소자의 제조방법
CN101635260A (zh) * 2008-07-24 2010-01-27 世界先进积体电路股份有限公司 半导体装置、晶体管及其制造方法
CN101901751A (zh) * 2009-01-26 2010-12-01 半导体元件工业有限责任公司 半导体元件及其制造方法
US20100207196A1 (en) * 2009-02-16 2010-08-19 Shin Min Jung Semiconductor device having internal gate structure and method for manufacturing the same
CN102683190A (zh) * 2011-03-07 2012-09-19 中芯国际集成电路制造(上海)有限公司 一种金属栅极及mos晶体管的形成方法
US20130052787A1 (en) * 2011-08-23 2013-02-28 Samsung Electronics Co., Ltd. Method of manufacturing semiconductor device
US20150021672A1 (en) * 2011-09-15 2015-01-22 Taiwan Semiconductor Manufacturing Company, Ltd. Contact for high-k metal gate device
CN103137451A (zh) * 2011-11-23 2013-06-05 中芯国际集成电路制造(上海)有限公司 一种半导体器件的制造方法
CN103515210A (zh) * 2012-06-20 2014-01-15 中芯国际集成电路制造(上海)有限公司 一种后栅极工艺晶体管及其形成方法
CN103545215A (zh) * 2012-07-17 2014-01-29 中国科学院微电子研究所 半导体器件及其制造方法
CN103579124A (zh) * 2012-08-08 2014-02-12 爱思开海力士有限公司 半导体器件的制造方法
CN103594414A (zh) * 2012-08-17 2014-02-19 华邦电子股份有限公司 沟槽隔离结构及其形成方法
CN106449643A (zh) * 2012-11-01 2017-02-22 北京芯盈速腾电子科技有限责任公司 非挥发性内存单元的制造方法
CN103915341A (zh) * 2013-01-08 2014-07-09 中芯国际集成电路制造(上海)有限公司 晶体管及其形成方法
CN104022026A (zh) * 2013-03-01 2014-09-03 中芯国际集成电路制造(上海)有限公司 多晶硅栅极的形成方法
WO2014149682A1 (en) * 2013-03-19 2014-09-25 Applied Materials, Inc. Multilayer passivation or etch stop tft
US20140361364A1 (en) * 2013-06-05 2014-12-11 Taiwan Semiconductor Manufacturing Co., Ltd. Doped protection layer for contact formation
CN104347485A (zh) * 2013-08-06 2015-02-11 中芯国际集成电路制造(上海)有限公司 一种半导体器件的制造方法
US20150061010A1 (en) * 2013-08-27 2015-03-05 International Business Machines Corporation Structure for improved contact resistance and extension diffusion control
CN104465347A (zh) * 2013-09-24 2015-03-25 北大方正集团有限公司 多晶硅表面处理方法及系统
CN104900706A (zh) * 2014-03-06 2015-09-09 三星显示有限公司 薄膜晶体管、其基板、显示设备及制造薄膜晶体管的方法
US9685383B2 (en) * 2015-05-13 2017-06-20 United Microelectronics Corp. Method of forming semiconductor device
CN106257645A (zh) * 2015-06-16 2016-12-28 北大方正集团有限公司 Cmos器件的制作方法
CN106601679A (zh) * 2015-10-15 2017-04-26 中芯国际集成电路制造(上海)有限公司 一种半导体器件及其制作方法、电子装置
CN106611696A (zh) * 2015-10-21 2017-05-03 国网智能电网研究院 一种碳化硅表面氧化膜的制备方法
CN106856172A (zh) * 2015-12-09 2017-06-16 中芯国际集成电路制造(上海)有限公司 鳍式场效应晶体管的形成方法
US9685385B1 (en) * 2016-07-05 2017-06-20 United Microelectronics Corp. Method of fabricating semiconductor device

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
黄海苟: "约束刻蚀剂层技术用于砷化镓三维规整细微图形的复制加工", 《中国优秀硕士学位论文全文数据库 工程科技Ⅰ辑》 *

Also Published As

Publication number Publication date
US9991363B1 (en) 2018-06-05
CN109300790B (zh) 2021-11-02
TW201909254A (zh) 2019-03-01
TWI670760B (zh) 2019-09-01

Similar Documents

Publication Publication Date Title
CN105225951B (zh) 鳍式场效应晶体管的形成方法
CN106057672B (zh) 半导体器件及其制造方法
US9209243B2 (en) Method of forming a shallow trench isolation structure
CN105097704B (zh) 闪存器件及其形成方法
CN106952873B (zh) 鳍式场效应管的形成方法
CN105225950B (zh) 鳍式场效应晶体管的形成方法、mos晶体管的形成方法
US8030173B2 (en) Silicon nitride hardstop encapsulation layer for STI region
CN103515321B (zh) 半导体器件的侧墙形成方法
JP2006269789A (ja) 半導体装置及びその製造方法
CN104779147B (zh) 一种金属栅极结构及其制备方法
CN105810738A (zh) 半导体器件及其制造方法
KR20170051269A (ko) 반도체 디바이스 및 그 제조 방법
CN104124195B (zh) 沟槽隔离结构的形成方法
CN103794543A (zh) 隔离结构及其形成方法
CN109411537A (zh) 复合接触蚀刻停止层
CN109300790A (zh) 具有牺牲多晶硅层的接触蚀刻停止层
CN104051248A (zh) 栅极的形成方法
US20110117714A1 (en) Integration of Multiple Gate Oxides with Shallow Trench Isolation Methods to Minimize Divot Formation
TW201918578A (zh) 形成氧化矽層的方法
CN106233452A (zh) 由局部硅外延籽晶形成的体晶片中的隔离半导体层
CN102361011B (zh) 形成半导体器件的栅极的方法
US7670895B2 (en) Process of forming an electronic device including a semiconductor layer and another layer adjacent to an opening within the semiconductor layer
CN103531476B (zh) 半导体器件制造方法
CN102456561A (zh) 沟槽式功率器件中沟槽底部厚栅氧化层的形成方法
US10170330B2 (en) Method for recessing a carbon-doped layer of a semiconductor structure

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
TA01 Transfer of patent application right
TA01 Transfer of patent application right

Effective date of registration: 20210308

Address after: California, USA

Applicant after: Lattice chip (USA) integrated circuit technology Co.,Ltd.

Address before: Greater Cayman Islands, British Cayman Islands

Applicant before: GF

GR01 Patent grant
GR01 Patent grant