TW201909254A - 具有犧牲多晶矽層之接觸蝕刻停止層 - Google Patents

具有犧牲多晶矽層之接觸蝕刻停止層 Download PDF

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TW201909254A
TW201909254A TW106130145A TW106130145A TW201909254A TW 201909254 A TW201909254 A TW 201909254A TW 106130145 A TW106130145 A TW 106130145A TW 106130145 A TW106130145 A TW 106130145A TW 201909254 A TW201909254 A TW 201909254A
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layer
sacrificial gate
forming
nitride
over
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TWI670760B (zh
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海苟 黃
金晟 高
海峰 盛
金平 劉
明哈 高
輝 臧
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美商格芯（美國）集成電路科技有限公司
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Abstract

一種接觸蝕刻停止層，其包括形成於犧牲閘極結構上面的氮化物層與形成於該氮化物層上面的多晶矽層。在後續製程期間，該多晶矽層適合氧化且形成氧化物層。該多晶矽層的氧化有效遮蔽底下的氮化物接觸蝕刻停止層免受氧化，這保護該氮化物層的機械完整性。

Description

具有犧牲多晶矽層之接觸蝕刻停止層
本申請案大體有關於半導體裝置，且更特別的是，有關於例如場效電晶體的電晶體及其製法。
製造例如場效電晶體(field effect transistor；FET)的半導體裝置通常涉及由層沉積、圖案化及蝕刻組成的多個步驟以在基板上界定各種結構。使用例如間隔體及帽蓋層的整合方案可用來精確地界定各個導電及絕緣結構，從而最小化相鄰導電結構之間的洩漏以改善裝置效能。
在某些辦法中，接觸蝕刻停止層(contact etch stop layer；CESL)可加入製造方案使得有可能選擇性移除一或更多層。不過，充分選擇性蝕刻製程的無法利用，且跟著接觸蝕刻停止層可能受損而導致受保護層受損，這對製造生產量及良率有不利影響。
鑑於上述，揭露一種方法用於形成具有改良接觸蝕刻停止層的半導體結構。該接觸蝕刻停止層包括多晶矽犧牲層。在可能氧化及損傷接觸蝕刻停止層和接觸蝕 刻停止層底下諸層的製程期間，該多晶矽層本身可氧化且抑制這些層的氧化。
根據本申請案的具體實施例，一種製造裝置之方法包括形成一犧牲閘極結構於一半導體基板上面，其中該犧牲閘極結構包括一犧牲閘極與形成於該犧牲閘極上面的一犧牲閘極間隙，形成一側壁間隔體層於該犧牲閘極結構的數個側壁上面，且形成一氮化物接觸蝕刻停止層於該側壁間隔體層上面。然後，形成一多晶矽層於該氮化物層的數個上部上面，且形成一氧化物層於該多晶矽層上面，其中，在該氧化物層的氧化期間，該多晶矽層會被氧化。
根據另一方法，在一半導體基板上面形成各自包括一犧牲閘極與形成於該犧牲閘極上面之一犧牲閘極間隙的數個犧牲閘極結構。形成一側壁間隔體層於該數個犧性閘極結構的側壁上面，且形成一氮化物接觸蝕刻停止層於該側壁間隔體層上面。
該方法更包括：形成一流動性氧化物層於在相鄰犧牲閘極結構之間的間隙內且於該氮化物層的數個下部上面，形成一多晶矽層於該氮化物層的數個上部上面，且形成一高密度電漿(HDP)氧化物層於該多晶矽層上面，致使該多晶矽層在該HDP氧化物層的形成期間被氧化。
100‧‧‧半導體基板或基板
120‧‧‧半導體鰭片或鰭片
140‧‧‧淺溝槽隔離層
210‧‧‧源極/汲極接面
300‧‧‧犧牲閘極結構
310‧‧‧犧牲閘極或多晶矽閘極
320‧‧‧犧牲閘極帽蓋
410‧‧‧側壁間隔體
510‧‧‧氮化物接觸蝕刻停止層(CESL)或氮化物層
520‧‧‧犧牲多晶矽層或多晶矽層
530‧‧‧氧化物層
610‧‧‧流動性氧化物層、沉積層或介電層
620‧‧‧高密度電漿(HDP)氧化物層、氧化物層或介電層
800‧‧‧間隙
閱讀時結合下列附圖可充分明白以下本申請案之特定具體實施例的詳細說明，其中類似的結構用相同 的元件符號表示。
第1圖的透射電子顯微鏡(transmission electron microscope；TEM)顯微圖圖示包括共形氮化物接觸蝕刻停止層的半導體結構，該共形氮化物接觸蝕刻停止層是在用流動性介電質材料填滿相鄰犧牲閘極結構之間的間隙以及使介電質材料凹陷之後設置於相鄰犧牲閘極結構上面；第2圖的透射電子顯微鏡(TEM)顯微圖圖示第1圖之結構的數個部份，包括氮化物接觸蝕刻停止層及底下側壁間隔體層在高密度電漿沉積一氧化物層於在相鄰犧牲閘極結構之間的數個凹陷區中後的崩解(breakdown)；第3圖為根據各種具體實施例之半導體結構的透射電子顯微鏡(TEM)顯微圖，其圖示鄰接犧牲閘極結構的氮化物接觸蝕刻停止層及底下側壁間隔體層在形成犧牲多晶矽層和高密度電漿沉積一氧化物層於數個凹陷區中且於在相鄰犧牲閘極結構之間的多晶矽層上面後的存留(retention)；第4圖為裝置架構的橫截面示意圖，其根據各種具體實施例圖示沉積氮化物接觸蝕刻停止層於相鄰犧牲閘極結構上面，以及圖示後續沉積流動性氧化物層於在閘極結構之間的間隙中；第5圖的橫截面示意圖圖示在流動性氧化物層之凹陷蝕刻(recess etch)後的第4圖的裝置架構；第6圖圖示沉積共形多晶矽層於凹陷流動性 氧化物層上面且於犧牲閘極結構上面，包括直接於氮化物接觸蝕刻停止層的數個上部上面；第7圖圖示沉積高密度電漿氧化物直接於多晶矽層上面且於在相鄰犧牲閘極結構之間的間隙的數個上部中以及多晶矽層的伴隨氧化；以及第8圖圖示高密度電漿氧化物的平坦化。
此時參考本申請案之專利標的之各種具體實施例的更詳細細節，附圖圖示本發明的一些具體實施例。諸圖用相同的元件符號表示相同或類似的部件。
揭露於各種具體實施例的是一種製造半導體裝置的方法，例如具有改良接觸蝕刻停止層的鰭片場效電晶體(FinFET)裝置。可給合閘極最後(gate last)或取代金屬閘極(replacement metal gate；RMG)製程實施所揭露的方法。用於製造取代金屬閘極(RMG)電晶體的典型製程流程包括形成暫時性或犧牲閘極，形成附加電晶體結構，然後移除犧牲閘極留下沉積各種材料層(例如，閘極介電質及閘極導體材料)於其中以形成功能閘極的溝槽。此辦法延後形成閘極直到在可能損害閘極材料的製程之後，例如暴露於升高溫度及/或離子植入。如本文所使用的，“功能閘極”係指用來使用電場或在某些情況下使用磁場控制半導體裝置之輸出電流(亦即，通過通道的載子流動)的結構，且包括閘極介電質與閘極導體。
根據各種具體實施例，該方法包括形成犧牲 多晶矽層於氮化物接觸蝕刻停止層(CESL)上面。該多晶矽層適合在後續製程期間優先氧化底下氮化物層及側壁間隔體層。因此，該氮化物接觸蝕刻停止層及側壁間隔體層在一或更多製程步驟期間可有效保護各種裝置特徵。特別是，該CESL適合在接觸蝕刻期間限制特定區域(例如，在相鄰閘極結構之間)的蝕刻。該CESL對於隨後用來蝕刻將會形成接觸之區域的化學物應有良好的抗蝕刻性。
在各種具體實施例中，該多晶矽層從在相鄰犧牲閘極結構之間的位置內直接形成於氮化物接觸蝕刻停止層上面，亦即，於在凹陷蝕刻流動性氧化物後橫向鄰接犧牲閘極堆疊之氮化物接觸蝕刻停止層(CESL)的數個上部上面。本案申請人已發現，在後續製程期間，相對於氮化物CESL層之氧化選擇性地進行多晶矽層的氧化，這可保護氮化物CESL層的完整性且抑制犧牲閘極的非所欲腐蝕。
第1圖的透射電子顯微鏡(TEM)顯微圖圖示包括設置於淺溝槽隔離層140上面之數個犧牲閘極結構300的裝置架構。第1圖圖示在主動裝置區之間的橫截面圖，亦即，圖示沿著在相鄰平行半導體鰭片之間的非接觸橫截面。
犧牲閘極結構300各自包括犧牲閘極310與形成於犧牲閘極310上面的犧牲閘極帽蓋(sacrificial gate cap)320。如熟諳此藝者所知，犧牲閘極310可包括非晶矽或多晶矽，且犧牲閘極帽蓋320可包括氮化物層，例如氮化矽。
側壁間隔體410設置在犧牲閘極結構300的側壁(垂直面)上面。側壁間隔體410的形成可藉由毯覆沉積間隔體材料，接著是定向蝕刻(directional etch)，例如反應性離子蝕刻(reactive ion etching；RIE)，以從水平面移除間隔體材料。合適側壁材料包括氧化物、氮化物及氮氧化物，例如二氧化矽、氮化矽、氮氧化矽、及低電介質常數(低k)材料，例如非晶碳、碳氧化矽(SiOC)、氮碳氧化矽(SiOCN)及氮碳硼化矽(SiBCN)，以及低k介電質材料。如本文所使用的，低k材料具有小於二氧化矽的電介質常數。在某些具體實施例中，側壁間隔體410之厚度為4到20奈米，例如4、10、15或20奈米，包括在上述數值中之任一者之間的範圍。
共形氮化物接觸蝕刻停止層510設置在位於相鄰犧牲閘極結構300之間的側壁間隔體410上面。在某些具體實施例中，氮化物接觸蝕刻停止層510的厚度可在2至6奈米之間，例如2、4或6奈米，包括在上述數值中之任一者之間的範圍。氮化物接觸蝕刻停止層510例如可由原子層沉積(atomic layer deposition；ALD)形成。
如本文所述，層或結構的形成或沉積可能涉及適用於被沉積之材料或層或被形成之結構的一或更多技術。此類技術包括但不限於：化學氣相沉積(chemical vapor deposition；CVD)、低壓化學氣相沉積(low pressure chemical vapor deposition；LPCVD)、電漿增強化學氣相沉積(plasma enhanced chemical vapor deposition；PECVD)、金屬有機 CVD(metal organic CVD；MOCVD)、原子層沉積(ALD)、分子束磊晶(molecular beam epitaxy；MBE)、電鍍、無電電鍍、離子束沉積及物理化學沉積(physical vapor deposition；PVD)技術，例如濺鍍或蒸鍍。
在各種具體實施例中，由彼此可選擇性地蝕刻的材料形成側壁間隔體410及氮化物CESL層510。在數個特定具體實施例中，側壁間隔體410包含氮碳氧化矽(SiOCN)，以及氮化物接觸蝕刻停止層510包含氮化矽。
此外，應瞭解，氮化矽與二氧化矽的化合物有各自標稱表示為Si3N4及SiO2的組成物。用語氮化矽及二氧化矽不僅指稱這些化學計量組成物，也指偏離化學計量組成物的氮化物及氧化物組成物。
在一示範實施例中，如部份圖示於第1圖者，直接沉積一層流動性氧化物610於氮化物接觸蝕刻停止層510上面以填滿在犧牲閘極結構300之間的間隙。在各種具體實施例中，流動性材料至少部份填滿間隙然後被轉換成二氧化矽膜。此一製程可用來填滿高深寬比(high aspect ratio)的間隙，包括深寬比在3：1到10：1之間的間隙。
在各種方法中，使用一或更多含矽前驅物與一氧化氣體沉積流動性二氧化矽。示範矽前驅物材料包括但不限於：烷氧基矽烷(alkoxysilanes)，例如，四氧甲基環四矽氧烷(tetraoxymethylcyclotetrasiloxane；TOMCTS)，八甲基環四矽氧烷(octamethylcyclotetrasiloxane；OMCTS)，四 乙氧基矽烷(tetraethoxysilane；TEOS)，三乙氧基矽烷(triethoxysilane；TES)，三甲氧基矽烷(trimethoxysilane；TriMOS)，甲基三乙氧基正矽酸鹽(methyltriethoxyorthosilicate；MTEOS)，四甲基正矽酸鹽(tetramethylorthosilicate；TMOS)，甲基三甲氧基矽烷(methyltrimethoxysilane；MTMOS)，二甲基二甲氧基矽烷(dimethyldimethoxysilane；DMDMOS)，二乙氧基矽烷(diethoxysilane；DES)，二甲氧基矽烷(dimethoxysilane，DMOS)，三苯基乙氧基矽烷(triphenylethoxysilane)，1-(三乙氧基矽烷基)-2-(二乙氧基甲基矽烷基)乙烷(1-(triethoxysilyl)-2-(diethoxymethylsilyl)ethane)，三第三丁氧基矽醇(tri-t-butoxylsilanol)。示範氧化氣體包括但不限於：臭氧、過氧化氫、氧、水(蒸氣)、及醇類，例如甲醇、乙醇及異丙醇。
在該流動性材料的沉積期間及/或之後，例如，可使用固化/退火製程，緻密化(densify)沉積層610的一部份或全部。根據各種具體實施例，固化/退火製程涉及暴露於在氧化或惰性環境中的蒸氣、熱、紫外線(UV)、電子束(e-beam)、微波、雷射或電漿源。
儘管流動性氧化物的緻密化退火(densification anneal)，然而用在貼近填充間隙之頂部(亦即，橫向鄰接犧牲閘極結構300的頂部)有品質較高、較密的氧化物取代流動性氧化物610可能是有利的，以便改善在後續製程期間填滿間隙之暴露氧化物材料的抗蝕刻性。
再參考第1圖，流動性氧化物層610的凹陷蝕刻重新開放間隙在結構之頂部的一部份且暴露氮化物接觸蝕刻停止層510的數個上部。參考第2圖，覆蓋流動性氧化物層610的高密度電漿(HDP)氧化物620可形成於凹陷區內。HDP氧化物通常從合適的含矽前驅物在氧化條件下用高密度電漿化學氣相沉積(HDP-CVD)沉積。
儘管在製造高密度氧化物上有效，然而用來形成高密度電漿(HDP)氧化物層620於凹陷流動性氧化物層610上面的製程條件可能蝕刻氮化物CESL 510的暴露部份，如第2圖所示。已觀察到，與高密度電漿氧化物層620之沉積相關的氧化條件可能對氮化物層510及/或側壁間隔體410有不利影響，導致這些層的抗蝕刻性崩解。在圖示結構中，HDP氧化物沉積已部份移除氮化物CESL 510和橫向鄰接犧性閘極310之頂部的底下側壁間隔體410。
在氮化物層510及側壁間隔體410之崩解導致暴露犧牲閘極310之上部的製程中，犧牲閘極310的相關損傷可能導致相鄰接觸的電氣短路，例如，在隨後形成於閘極間間隙(inter-gate gap)內的源極/汲極接觸與上覆閘極的閘極接觸之間。
應瞭解，第2圖的橫截面圖是沿著主動裝置區繪出，亦即，沿著穿過半導體鰭片120的接觸橫截面，且圖示上覆鰭片120(亦即，鰭片在源極/汲極接面210之間的通道區上面)的數個犧牲閘極結構300。
在各種具體實施例中，半導體裝置可包含鰭 片場效電晶體(FinFET)。在此類具體實施例中，藉由圖案化及蝕刻例如SOI基板之複合基板的半導體層或塊狀半導體基板100的頂部，可形成一或更多半導體鰭片120。
例如，半導體基板100可包含半導體材料，例如矽(Si)或含矽材料。含矽材料包括但不限於：單晶矽、多晶矽、單晶矽鍺(SiGe)、多晶矽鍺、摻有碳的矽(Si：C)、非晶矽、以及由彼等組成的組合及多層。
不過，半導體基板100不限於含矽材料，因為基板100可包含其他半導體材料，包括鍺及化合物半導體，例如砷化鎵(GaAs)、砷化銦(InAs)及其他類似半導體。半導體基板100的數個部份可為非晶、多晶或單晶體。
用來形成鰭片120的蝕刻製程通常包含非等向性蝕刻。在某些具體實施例中，可使用乾蝕刻製程，例如，反應性離子蝕刻(RIE)。在其他具體實施例中，可使用濕化學蝕刻劑。又在其他具體實施例中，可使用乾蝕刻與濕蝕刻的組合。
例如，鰭片120可使用側壁影像轉移(sidewall image transfer；SIT)製程形成，這包括形成間隔體材料於心軸(mandrel)的側壁表面上。該間隔體包括蝕刻選擇性與心軸不同的材料，致使，在間隔體形成後，用蝕刻移除該心軸。然後，各間隔體在界定鰭片的後續蝕刻製程期間用作硬遮罩。
半導體鰭片120通常平行配置且藉由淺溝槽隔離層140互相橫向隔離。增高式(raised)源極/汲極接面 210設置在鰭片120貼近其頂面的部份上面(亦即，源極及汲極區)。如熟諳此藝者所知，源極/汲極接面210可用離子植入或選擇性磊晶形成，視需要使用犧牲閘極結構300作為對準遮罩。例如，根據各種具體實施例，源極/汲極接面210用選擇性磊晶形成於在犧牲閘極結構之間界定於鰭片上面的自對準空腔中。亦即，源極/汲極接面210形成於鰭片120在位於犧牲閘極結構300底下之通道區的任一側上的源極及汲極區上面。
源極/汲極接面210可包含矽(例如，Si)或含矽材料，例如矽鍺(SiGe)。例如，矽鍺源極/汲極接面可併入p-MOS裝置以提供壓縮應力予通道，這可改善載子移動率。
仍參考第2圖，可見，在源極/汲極接觸位置內，亦即，在接觸區內，氮化物接觸蝕刻停止層510係形成於側壁間隔體410上面且於源極/汲極接面210上面。
參考第3圖，且根據各種具體實施例，在相鄰犧牲閘極結構300之間與在源極/汲極接面210上面形成雙重介電層610、620。可形成包括流動性氧化物層610與上覆高密度電漿氧化物層620的介電層而不有害地蝕刻氮化物CESL 510係藉由在使流動性氧化物層610凹陷之後和在沉積高密度電漿氧化物層620之前，形成犧牲多晶矽層直接於氮化物接觸蝕刻停止層510上面。
參考第4圖至第8圖，描述一種形成改良CESL架構之方法。描述於此的是在形成高密度電漿氧化物 層620之前，形成犧牲多晶矽層520於氮化物接觸蝕刻停止層510上面的複合CESL層。在高密度電漿氧化物層620的沉積期間，多晶矽層520被原位氧化以形成附加氧化物層530。
根據各種具體實施例，一種製造例如FinFET裝置之裝置的方法，其包括形成犧牲閘極結構300於半導體基板上面，其中犧牲閘極結構300包括犧牲閘極310與形成於犧牲閘極310上面的犧牲閘極間隙320。形成側壁間隔體層410於犧牲閘極結構300的側壁上面。然後，形成氮化物(CESL)層510於側壁間隔體層410上面。該方法更包括：形成多晶矽層520於氮化物層510的數個上部上面，且形成例如HDP氧化物層620的氧化物層於多晶矽層520上面。在氧化物層620的形成期間，多晶矽層520被完全氧化。
第4圖為圖示沉積共形氮化物接觸蝕刻停止層510於犧牲閘極結構300上面的橫截面示意圖。如圖所示，氮化物層510直接形成於在相鄰犧牲閘極結構300之間的源極/汲極接面210上面且直接於側壁間隔體410上面。ALD製程可用來形成氮化物層510。在相鄰犧牲閘極結構300之間且在氮化物層510上面形成流動性氧化物層610。
第5圖的橫截面示意圖圖示在凹陷蝕刻流動性氧化物層610以開放在相鄰犧牲閘極結構300之間的間隙800之後的第4圖結構。在凹陷蝕刻流動性氧化物層610 後，氮化物層510的數個部份被暴露。在各種具體實施例中，流動性氧化物層610的凹陷蝕刻暴露在犧牲閘極結構300之數個上部上面的氮化物層，致使暴露氮化物層510在間隙800內的數個上部，同時流動性氧化物層610的其餘部份設置在氮化物層510的下部上面。
請參考第6圖，形成共形多晶矽層520於間隙800內且於犧牲閘極結構300上面。在圖示具體實施例中，多晶矽層520直接形成於氮化物層510的數個上部上面，以及直接於犧牲閘極帽蓋320的頂面上面。
可使用低壓化學氣相沉積(LPCVD)技術沉積多晶矽(多晶體矽)層520。例如，可用在低壓高溫分解(pyrolytic decomposition)矽烷氣體來沉積LPCVD多晶矽層，然而可利用其他反應方法。
在凹陷蝕刻流動性氧化物層610和沉積犧牲多晶矽層520後，形成高密度電漿氧化物層620於間隙800內且於犧牲閘極結構300上面。高密度電漿氧化物層620直接形成於犧牲多晶矽層520上面。伴隨高密度電漿氧化物層620之沉積的是多晶矽層520的氧化以形成附加氧化物層530。氧化物層530原位形成於犧牲閘極帽蓋320的數個上部上面且於氮化物接觸蝕刻停止層510的數個上部上面。在某些具體實施例中，多晶矽層520在HDP氧化物層620的沉積期間被完全氧化以形成氧化物層530致使沒有多晶矽材料殘留。
請參考第8圖，在沉積高密度電漿氧化物620 後，可平坦化該結構。“平坦化”為至少運用例如磨擦媒介之機械力的材料移除製程，以產生實質二維表面。平坦化製程可包括化學機械研磨(chemical mechanical polishing；CMP)或磨光。化學機械研磨(CMP)為利用化學反應及機械力兩者以移除材料且平坦化表面的材料移除製程。犧牲閘極帽蓋320可用作平坦化製程的CMP蝕刻停止層。在圖示具體實施例中，氧化物層620的頂面與犧牲閘極帽蓋320的頂面共面。
再參考第3圖，藉由保護氮化物CESL 510及側壁間隔體410以免氧化，可避免在下游製程期間不必要地蝕刻或腐蝕多晶矽閘極310。
所揭示的方法提供一種複合接觸蝕刻停止層(CESL)架構。用接觸蝕刻停止層架構製成的裝置有犧牲閘極腐蝕的減少傾向以及較少的接觸間電氣短路意外。用本方法製成的積體電路有改善的可靠性及效能，以及閘極與源極/汲極接觸之間的洩漏最少，且電路故障的例子減少。
如本文所使用的，單數形式“一(a)”、“一(an)”、及“該(the)”旨在也包括複數形式，除非上下文中另有明確指示。因此，例如，“犧牲閘極結構”的引用包括有兩個或更多此類“犧牲閘極結構”的實施例，除非上下文中另有明確指示。
除非另有明文規定，決非旨在提及於本文的任何方法被理解為它的步驟需要按照特定的順序執行。相應地，在方法請求項沒有實際列舉其步驟將會遵循的順序 或請求項或說明中沒有另外特別說明該等步驟受限於特定順序時，決非旨在暗示任何特定順序。任一請求項中的任何列舉單一或多個特徵或方面可與任何其他請求項或數個請求項中的任何其他列舉特徵或方面排列或組合。
應瞭解，當指例如層、區域或基板的元件形成、沉積或設置於另一元件“上”或“上面”時，它可直接在該另一元件上或者也可存在中介元件。相比之下，當指一元件“直接”在另一元件“上”或“上面”時，不存在中介元件。
儘管使用傳統片語“包含(comprising)”可揭示特定具體實施例的各種特徵、元件或步驟，然而應瞭解，替代具體實施例暗示包括可用傳統片語“由…組成(consisting)”或“實質由…組成(consisting essentially of)”描述者。因此，例如，包含氮化矽之接觸蝕刻停止層的暗示替代具體實施例包括接觸蝕刻停止層實質由氮化矽組成的具體實施例與接觸蝕刻停止層由氮化矽組成的具體實施例。
熟諳此藝者明白，本發明可做出各種修改及變體而不脫離本發明的精神及範疇。由於體現本發明精神及主旨的修改、組合、次組合及變體對熟諳此藝者而言可能出現，因此本發明應被視為涵蓋在隨附申請專利範圍及其等效陳述之範疇內的任何事物。

Claims (19)

  1. 一種製造裝置之方法，其包含：形成一犧牲閘極結構於一半導體基板上面，其中，該犧牲閘極結構包括一犧牲閘極與形成於該犧牲閘極上面的一犧牲閘極間隙；形成一側壁間隔體層於該犧牲閘極結構的數個側壁上面；形成一氮化物層於該側壁間隔體層上面；形成一多晶矽層於該氮化物層的數個上部上面；以及形成一氧化物層於該多晶矽層上面，其中，該多晶矽層在該氧化物層的形成期間被氧化。
  2. 如申請專利範圍第1項所述之方法，其中，該氮化物層係由原子層沉積形成。
  3. 如申請專利範圍第1項所述之方法，其中，該氮化物層包含氮化矽。
  4. 如申請專利範圍第1項所述之方法，其中，該多晶矽層直接形成於該氮化物層的該數個上部上面。
  5. 如申請專利範圍第1項所述之方法，其中，該多晶矽層在該氧化物層的形成期間被完全氧化。
  6. 如申請專利範圍第1項所述之方法，其中，該多晶矽層直接形成於該犧牲閘極帽蓋的一頂面上面。
  7. 如申請專利範圍第1項所述之方法，更包含：在形成該多晶矽層之前，形成一流動性氧化物層於該氮化物層的 數個下部上面。
  8. 如申請專利範圍第7項所述之方法，其中，該多晶矽層形成於該流動性氧化物層的一頂面上面且直接於該氮化物層的該數個上部上面橫向鄰接該犧牲閘極。
  9. 如申請專利範圍第1項所述之方法，其中，該氧化物層包含一高密度氧化物。
  10. 如申請專利範圍第1項所述之方法，其中，形成該犧牲閘極結構包含：形成數個犧牲閘極結構於該半導體基板上面。
  11. 如申請專利範圍第10項所述之方法，更包含：在該數個犧牲閘極結構的相鄰犧牲閘極結構之間形成一源極/汲極接面於該半導體基板上面。
  12. 如申請專利範圍第11項所述之方法，其中，該氮化物層直接形成於該源極/汲極接面上面。
  13. 一種製造裝置之方法，其包含：形成數個犧牲閘極結構於一半導體基板上面，其中，該數個犧牲閘極結構各自包括一犧牲閘極與形成於該犧牲閘極上面的一犧牲閘極間隙；形成一側壁間隔體層於該犧牲閘極結構的數個側壁上面；形成一氮化物層於該側壁間隔體層上面；形成一流動性氧化物層於相鄰犧牲閘極結構之間且於該氮化物層的數個下部上面；形成一多晶矽層於該氮化物層的數個上部上面； 以及形成一氧化物層於該多晶矽層上面，其中，該多晶矽層在該氧化物層的氧化期間被氧化。
  14. 如申請專利範圍第13項所述之方法，更包含：在形成該多晶矽層之前，形成該流動性氧化物層於該相鄰犧牲閘極結構之間。
  15. 如申請專利範圍第13項所述之方法，其中，該多晶矽層在該氧化物層的形成期間被完全氧化。
  16. 如申請專利範圍第13項所述之方法，其中，該氧化物層包含一高密度氧化物。
  17. 如申請專利範圍第13項所述之方法，其更包含：在該相鄰犧牲閘極結構之間形成一源極/汲極接面於該半導體基板上面。
  18. 如申請專利範圍第17項所述之方法，其中，該氮化物層直接形成於該源極/汲極接面上面。
  19. 如申請專利範圍第12項所述之方法，其更包含：從該半導體基板形成數個鰭片，以及形成該數個犧牲閘極結構於該數個鰭片上面。
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