CN101165917A - 具有连续接触蚀刻停止层的金属氧化物半导体元件 - Google Patents
具有连续接触蚀刻停止层的金属氧化物半导体元件 Download PDFInfo
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Abstract
本发明提供一种半导体结构,包括一基板,一栅极堆栈于该基板上,一源极/漏极区域邻近该栅极堆栈,一源极/漏极硅化物区域于该源极/漏极区域上,一保护层于该源极/漏极硅化物区域上,其中位于该栅极堆栈上的一区域大致上无该保护层,以及一接触蚀刻停止层具一应力于该保护层上,且延伸于该栅极堆栈上。
Description
技术领域
本发明涉及金属-氧化物-半导体(MOS)元件的结构及制造方法,尤其与MOS元件的硅化物区域的形成有关。
背景技术
超大规模集成电路(VLSI)系统所需的深次微米(deep-submicron)微缩技术已主导微电子工业的设计观。随着栅极电极长度的微缩化,源极与漏极接面亦需随之缩小,以抑制所谓的短通道效应(short channel effect,SCE)。短信道效应会使缩小化的元件性能劣化。互补式金属-氧化物-半导体(CMOS)元件微缩时所遭遇到的主要问题为增加不想要的寄生电容。随着源极/漏极接面深度与多晶硅线宽微缩至深次微米的范围,接触电阻变得更明显且必须将其降低。
降低多晶硅栅极及漏极/源极区域与内联机之间的电阻的主要方法为形成金属硅化物于漏极/源极区域与栅极电极的顶部上。于最常用的金属硅化物材料中,硅化镍与硅化钴通常用于自对准硅化物(self-aligned silicide,简称salicide)加工工艺。于salicide制程中,一金属薄层毯覆性地形成于一具有裸露源极/漏极与门极区域的半导体晶片上。接着,将此晶片置于一或多重步骤的退火加工工艺中,导致金属薄层选择性地与源极/漏极与门极区域处裸露的硅发生反应,因而形成金属硅化物。上述步骤之所以被称为自对准硅化物(salicide)加工工艺是由于硅化物层仅仅形成于金属材料与源极/漏极区域的硅及多晶硅栅极电极直接接触的位置。
于传统的硅化物加工工艺中,若栅极电极系由多晶硅构成,则硅化物形成于栅极电极上。各种用户化设计可针对符合不同需求而实施。例如,完全硅化的(fully silicided,简称FUSI)栅极可形成以消除多晶硅空乏效应,其可能导致多晶硅相对低的电荷供应能力。NMOS元件与PMOS元件亦可具有不同功函数的硅化物栅极。上述用户化设计必需将源极/漏极硅化物区域与栅极硅化物区域分别形成。
图1显示传统MOS元件制造步骤的剖面示意图。于形成源极/漏极区域14与源极/漏极硅化物区域12之后,接着毯覆性地形成一接触蚀刻停止层(CESL)10。为了进行多晶硅栅极4的硅化步骤,需实施一化学机械研磨(CPM)步骤移除多晶硅栅极4的结构,其包括位于多晶硅栅极4上的部分接触蚀刻停止层(CESL)10。接着,以传统的硅化加工工艺将多晶硅栅极4硅化。
图2系显示如图1所示结构的俯视图。应注意的是,由于实施CMP工艺的缘故,接触蚀刻停止层(CESL)10被分隔成两部分,其中一部分位于源极区域上,另一部分位于漏极区域上。因此,此结构明显地降低接触蚀刻停止层10施于完成后MOS元件的信道区域上的应力。进一步衍生的问题是,由于多晶硅栅极4上的接触蚀刻停止层10已被移除,于后续的在层间介电层(inter-layer dielectric)中形成接触开口步骤时,便无接触蚀刻停止层以终止蚀刻步骤。一部分的栅极硅化物区域,甚至多晶硅栅极4本身,可能因此受到蚀刻步骤的影响,进而导致接触电阻增加。
因此,业界亟需一种新的半导体元件的结构与方法,协同分别形成的栅极及源极/漏极硅化物区域的形成步骤,利用用户化栅极与源极/漏极硅化物区域的优点,同时又能避免公知技术所造成不良的影响。
发明内容
有鉴于此,本发明的一个目的在于提供一种半导体结构,包括一基板,一栅极堆栈于该基板上,一源极/漏极区域邻近该栅极堆栈,一源极/漏极硅化物区域于该一源极/漏极区域上,一保护层于该源极/漏极硅化物区域上,其中位于该栅极堆栈上的一区域大致上无该保护层,以及一接触蚀刻停止层(CESL)于该保护层上。
本发明之另一目的在于提供一种半导体结构,包括一基板,一栅极堆栈于该基板上,一栅极硅化物区域于该栅极堆栈的一顶部中,一源极区域邻近该栅极堆栈,一源极硅化物区域于该一源极区域上,一漏极区域邻近该栅极堆栈且位于该栅极堆栈的对侧,一漏极硅化物区域于该一漏极区域上,其中该源极及该漏极硅化物区域与该栅极硅化物区具有基本上不同的厚度或具有基本上不同的组成,一保护层于该源极/漏极硅化物区域上,其中该保护层包括一源极保护及一漏极保护,且该源极保护及该漏极保护彼此间不连接,以及一接触蚀刻停止层于该保护层上,且延伸于该栅极硅化物区域上。
本发明的另一目的在于提供一种半导体结构,包括一基板,一PMOS元件与一NMOS元件。该PMOS元件包括一第一栅极堆栈于该基板上,一第一栅极硅化物区域于该第一栅极堆栈的一顶部中,一第一源极/漏极区域邻近该第一栅极堆栈,一第一源极/漏极硅化物区域于该第一源极/漏极区域上,以及一保护层于该第一源极/漏极硅化物区域上,其中位于该第一栅极堆栈上的一区域实质上无该保护层。该NMOS元件包括一第二栅极堆栈于该基板上,一第二栅极硅化物区域于该第二栅极堆栈的一顶部中,其中该第一与该第二栅极硅化物区域具实质上不同的组成,一第二源极/漏极区域邻近该第二栅极堆栈,以及一第二源极/漏极硅化物区域于该第二源极/漏极区域上,其中该保护层于该第二源极/漏极硅化物区域上,且其中位于该第二栅极堆栈上的一区域实质上无该保护层。以及一接触蚀刻停止层(CESL)于该保护层及该第一与该第二栅极硅化物区域上。
本发明的又一样态在于提供一种半导体结构的制造方法,包括提供一基板,形成一栅极堆栈于该基板上,形成一源极/漏极区域邻近该栅极堆栈,形成一源极/漏极硅化物区域于该一源极/漏极区域上,形成一保护层于该源极/漏极硅化物区域上,基本上移除位于该栅极堆栈上的该保护层,以及形成一接触蚀刻停止层于该保护层上。
本发明的又一目的在于提供一种半导体结构的制造方法,包括提供一基板,形成一栅极堆栈于该基板上,形成一栅极硅化物区域于该栅极堆栈的一顶部中,形成一源极区域邻近该栅极堆栈,一源极硅化物区域于该一源极区域上,一漏极区域邻近该栅极堆栈且位于该栅极堆栈的对侧,一漏极硅化物区域于该一漏极区域上,其中该源极及该漏极硅化物区域与该栅极硅化物区具有基本上不同的厚度或具有基本上不同的组成,形成一保护层于该源极/漏极硅化物区域上,形成一可移除层于该保护层与该栅极堆栈上,将该可移除层薄化以露出该栅极堆栈上的该保护层,移除该栅极堆栈上的该保护层,将栅极堆栈上的一栅极电极与一金属反应以成为硅化物栅极,移除该可移除层,以及形成一接触蚀刻停止层于该保护层上,且延伸于该栅极硅化物区域上。
为使本发明之上述目的、特征和优点能更明显易懂,下文特举较佳实施例,并配合附图,作详细说明如下:
附图说明
图1和图2分别显示传统的MOS元件的制造方法的中间阶段的剖面图与俯视图,其中于栅极堆栈上的部分实施停止层被移除;
图3至图11显示本发明之较佳实施例的MOS元件的制造方法的中间阶段的剖面示意图。
其中,附图标记说明如下:
图1和图2
2~栅极介电层;4~多晶硅栅极;10~接触蚀刻停止层;12~源极/漏极硅化物区域;14~源极/漏极区域。
图3至图11
20~基板;22~浅沟槽绝缘(STI)区;100~NMOS元件区;200~PMOS元件区;130、230~栅极介电层;124、224、226~源极/漏极区域;132、232~栅极电极;134、234~屏蔽层;128、228~硅化物区域;40~保护层;42~可移除层;45~虚线;146、246~栅极硅化物区域;244~屏蔽层;48、148、248~接触蚀刻停止层;50~层间介电层;154、254~接触栓。
具体实施方式
本发明实施例提供一种金属-氧化物-半导体(MOS)元件及其制造方法。根据本发明之较佳实施例,上述MOS元件的制造方法的中间阶段亦揭示于附图中。
请参阅图3,提供一基板20,可由一般的半导体材料或结构形成,例如硅块材、绝缘层上有硅(SOI)基板、硅锗(SiGe)基板、嵌入式硅锗(eSiGe)基板、锗基板及其它半导体基板。浅沟槽绝缘(STI)区22形成于基板20中,定义出一NMOS元件区100以及一PMOS元件区200。于NMOS元件区100中,一栅极堆栈包括一栅极介电层130、一栅极电极132以及一屏蔽层134,形成于基板20上。于PMOS元件区200中,一栅极堆栈包括一栅极介电层230、一栅极电极232以及一屏蔽层234,形成于基板20上。
栅极介电层130与230皆可采用一般常用的介电材料形成,例如氧化物、高介电常数(high-k)材料、氮化物、氮氧化物,及上述材料的组合、以及视设计需要而采用适合的材料。根据本发明的较佳实施例,栅极电极132与232可采以多晶硅层或多晶硅含薄金属层的形式形成,且多晶硅可分别掺杂n-型及p-型掺杂物。或者,栅极电极132与232可采以金属材料形成。屏蔽层134与234较佳者为介电材料氮化硅、氮氧化硅、碳化硅及其它介电材料。
源极/漏极区域124与224分别形成于NMOS元件区100与PMOS元件区200中。于PMOS元件区200中,另可形成SiGe应力子(SiGe stressor),其可施以一压应力于对应PMOS元件的信道区。硅化物区域128形成于源极/漏极区域124,以及硅化物区域228形成于源极/漏极区域224。于较佳实施例中,硅化物区域128与228包括金属(例如Ni、Ni-Yb、Ni-Pt及其它同性质的金属材料或合金)与硅或SiGe于低温下反应形成。然而,亦可使用其它金属形成硅化物,例如钴、铂、镁、钯及其它同性质的金属材料或合金。硅化物区域128与228可分别形成且分别包括不同材料。
请参阅图4,一保护层40毯覆性地覆盖该元件区100与200。保护层40较佳者为一薄层,使得后续形成的蚀刻停止层所施于信道区域的应变所造成的副作用降至最低。于一较佳的实施例中,保护层40的厚度较佳为约小于400埃(),更佳者为约小于200埃()。保护层40可包括氧化物、氮化物、氮氧化物、上述材料的组合,及上述材料的多层结构。
图4还显示一可移除层42形成于保护层40上。于本发明较佳实施例中,可移除层42为一光阻层。于其它实施例中,可移除层42为一旋涂玻璃介质(spin-on glass,简称SOG)层。于另一实施例中,可移除层42包括以化学气相沉积法(CVD)形成的介电材料,例如以电浆辅助化学气相沉积法(PECVD)、选择区域化学气相沉积法(SACVD)、及其它形式的化学气相沉积法形成。较佳者为,可移除层42与保护层40具有不同的蚀刻选择特性。
在图5中,将可移除层42薄化以显露出保护层40的顶部区域。可移除层42的薄化步骤可通过化学机械研磨法(CMP)或蚀刻法实现。上述蚀刻法包括干式蚀刻法与湿式蚀刻法。于蚀刻或CMP步骤完成之后,部分的可移除层42仍遗留在保护层40上,以保护下层的保护层40。
图6显示露出的栅极电极132与232。接着,将露出的保护层40移除,较佳者为以湿蚀刻或干蚀刻法移除。接着,移除屏蔽层134与234,使下层的栅极电极132与232露出。
在另一实施例中,于可移除层42的沉积步骤之后,即施以化学机械研磨法(CMP)。该化学机械研磨法(CMP)于栅极电极132及/或232的表面露出后即停止。其结果为,于所获得的元件结构中,位于虚线45上且位于栅极电极132与232侧壁上的间隙壁部分与保护层40部分被移除。
图7A与图7B显示栅极硅化物区域146与246的形成步骤示意图,其中以完全硅化(FUSI)栅极为例说明。如同发明背景所知,为了形成硅化物区域,必须形成一金属层(未示出)于栅极电极132与232上(请参阅图6)。接着,施以一退火步骤使金属层与下层的Si/SiGe层间发生反应。接着,移除未反应的金属层,移除的方以选用会侵蚀未反应金属层而不会侵蚀硅化物的化学药剂。于其一实施例中,相同材质的金属层(未示出)形成于栅极电极132与232上,结果图示于图7A,其所获得的硅化物栅极146与246具有相同组成的硅化物。在另一实施例中,请参阅图7B,不同材质的金属层沉积于栅极电极132与232上,其所获得的硅化物栅极164与246具有不同的组成。在一比较实施例中,屏蔽层244形成以保护栅极电极132与232之一(例如栅极电极232),且仅栅极电极132硅化成硅化物栅极164。接着再将屏蔽层244移除。相同地,可形成另一屏蔽层(未示出)以保护栅极硅化物146,且栅极电极232硅化形成硅化物栅极246。所获得的结构与图7A所示的结构相似。于此实施例中,硅化物栅极164与246可包括不同的金属硅化物,较佳为具有不同功函数(work function)的硅化物栅极。
本发明实施例特别适用于形成MOS元件,其栅极硅化物区域与源极/漏极硅化物区域具有不同的组成,其中“不同的组成”定义为用以形成源极/漏极硅化物区域或栅极硅化物区域的金属,彼此之间包括至少一不同的金属元素。再者,“不同的组成”亦可表示该栅极硅化物区域与源极/漏极硅化物区域的金属元素含量的百分比实质上不同,即使上述金属层中的金属元素种类实质上相同。例如,若是于栅极硅化物区域与源极/漏极硅化物区域中的一金属元素具有一实质的含量百分比差异,例如其差异大于约百分之五,所形成的硅化物亦被视为具有不同的组成。本发明实施例亦适用于形成栅极硅化物区域与对应的源极/漏极硅化物区域,具有实质上不同的厚度。例如,一FUSI栅极硅化物区域的厚度可大于源极/漏极硅化物区域的厚度。
图8及图9显示根据本发明另一实施例的栅极硅化物区域的形成步骤示意图。图8所示的结构与图3所示的结构相似,不同之处在于栅极堆栈,例如位于元件区域200的栅极堆栈还包括一额外的多晶硅层236及一额外的屏蔽层238。有鉴于此,栅极电极232具有较小的厚度,例如其厚度可能只有栅极电极132厚度的一半。由于栅极电极132与232具有不同的厚度,所获得的硅化物栅极146与246将具有不同的组成。在一比较实施例中,于图4到图6所示的步骤实施之后,相继移除标号为134、238、236与234的层以形成如图9所示的结构。于后续形成的硅化物步骤中,由于栅极电极232的厚度小于栅极电极132的厚度,所获得的栅极硅化物区域具有不同的组成。例如,当形成镍硅化物时,硅化物栅极146可包括NiSi,而硅化物栅极246(请参阅图7)则可包括Ni2Si。通过调整栅极电极132与232(请参阅图3)的厚度,以及用以形成硅化物栅极146与246所采用的金属,因此可得到不同组成的硅化物栅极146与246。
于目前所讨论的实施例中,栅极硅化物区域是将栅极电极132与232硅化而形成。于其它实施例中,可先将栅极电极132与232蚀除,再将导电材料填入蚀除栅极电极132与232所形成的开口中。上述导电材料包括金属、金属硅化物、金属硅化物及其它导电材料。
图10显示根据本发明实施例形成接触蚀刻停止层(CESL)48的示意图,其包括通常使用的介电层,例如氮化硅、氮氧化硅、碳化硅、上述材料的组合、及上述材料的多层结构。除了作为停止蚀刻步骤的目的之外,CESL层48亦作为施予应力于相对MOS元件的信道区域。较佳者为,于NMOS元件区域100上的部分CESL层148具张应力(tensile stress),而位于PMOS元件区域200上的部分CESL层248具压应力(compressive stress)。应注意的是,为了有效地在对应的MOS元件的信道区域施予应力,较佳者为将CESL层48设置尽量靠近于信道区域。有鉴于此,保护层40的厚度宜尽量降低。
再者,如图11所示,一层间介电层(ILD)50沉积于CESL层48上。层间介电层50较佳者为低介电常数(low-k)介电层,例如,具有低的介电常数约低于3.5。接着,蚀刻层间介电层50以形成接触窗(未示出)于其中。通过CESL层48的帮助,可更精确的控制层间介电层50的蚀刻步骤。接着,移除在接触窗内的CESL层48与保护层40,露出下层的硅化物栅极与源极/漏极硅化物区域。接着,将一金属材料填入接触窗,较佳者为包括钨、钛、铝、铜及上述材料之组合,以形成接触栓(contact plug)154与254。
以上所述的仅为本发明的较佳可行实施例,所述实施例并非用以限制本发明的专利保护范围,因此凡是运用本发明的说明书及附图内容所作的等同结构变化,同理均应包含在本发明的专利保护范围。
Claims (16)
1.一种半导体结构,包括:
一基板;
一栅极堆栈于该基板上;
一源极/漏极区域邻近该栅极堆栈;
一源极/漏极硅化物区域于该一源极/漏极区域上;
一保护层于该源极/漏极硅化物区域上,其中位于该栅极堆栈上的一区域大致上无该保护层;以及
一接触蚀刻停止层于该保护层上。
2.如权利要求1所述的半导体结构,其特征在于,该保护层包括一部分直接形成于该栅极堆栈上。
3.如权利要求1所述的半导体结构,其特征在于,该保护层的厚度约小于400埃。
4.如权利要求1所述的半导体结构,其特征在于,该保护层包括一源极保护及一漏极保护,且该源极保护及该漏极保护彼此间不连接。
5.如权利要求1所述的半导体结构,其特征在于,该接触蚀刻停止层包括一源极部分及一漏极部分,且该源极部分及该漏极部分彼此间不连接。
6.如权利要求1所述的半导体结构,其特征在于,该栅极堆栈包括一栅极硅化物区域。
7.如权利要求6所述的半导体结构,其特征在于,该源极/漏极硅化物区域的厚度基本上与该栅极硅化物区域的厚度不同。
8.如权利要求6所述的半导体结构,其特征在于,该源极/漏极硅化物区域的组成基本上与该栅极硅化物区域的组成不同。
9.如权利要求1所述的半导体结构,其特征在于,该栅极堆栈包括一完全硅化物栅极。
10.如权利要求1所述的半导体结构,其特征在于,该栅极堆栈包括金属。
11.一种半导体结构的制造方法,包括:
提供一基板;
形成一栅极堆栈于该基板上;
形成一源极/漏极区域邻近该栅极堆栈;
形成一源极/漏极硅化物区域于该一源极/漏极区域上;
形成一保护层于该源极/漏极硅化物区域上,且大致上移除位于该栅极堆栈上的该保护层;以及
形成一接触蚀刻停止层于该保护层上。
12.如权利要求11所述的半导体结构的制造方法,其特征在于,该保护层步骤包括一部分直接形成于该栅极堆栈上。
13.如权利要求11所述的半导体结构的制造方法,其特征在于,形成该栅极堆栈步骤包括形成一栅极硅化物区域。
14.如权利要求13所述的半导体结构的制造方法,其特征在于,该源极/漏极硅化物区域的厚度基本上与该栅极硅化物区域的厚度不同。
15.如权利要求13所述的半导体结构的制造方法,其特征在于,该源极/漏极硅化物区域的组成基本上与该栅极硅化物区域的组成不同。
16.一种半导体结构的制造方法,包括:
提供一基板;
形成一栅极堆栈于该基板上;
形成一栅极硅化物区域于该栅极堆栈的一顶部中;
形成一源极区域邻近该栅极堆栈;
形成一源极硅化物区域于该一源极区域上;
形成一漏极区域邻近该栅极堆栈且位于该栅极堆栈的对侧;
形成一漏极硅化物区域于该一漏极区域上,其中该源极及该漏极硅化物区域与该栅极硅化物区具有实质上不同的厚度或具实质上不同的组成;
形成一保护层于该源极/漏极硅化物区域上,形成一可移除层于该保护层与该栅极堆栈上;
将该可移除层薄化以露出该栅极堆栈上的该保护层;
移除该栅极堆栈上的该保护层,将该栅极堆栈上的一栅极电极与一金属反应以成为硅化物栅极;
移除该可移除层;以及
形成一接触蚀刻停止层于该保护层上,且延伸于该栅极硅化物区域上。
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US11/583,634 US7732878B2 (en) | 2006-10-18 | 2006-10-18 | MOS devices with continuous contact etch stop layer |
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TWI340469B (en) | 2011-04-11 |
TW200820437A (en) | 2008-05-01 |
US7732878B2 (en) | 2010-06-08 |
US20080093675A1 (en) | 2008-04-24 |
CN101165917B (zh) | 2010-07-21 |
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