CN109075154B - 背侧钻孔嵌入式管芯衬底 - Google Patents

背侧钻孔嵌入式管芯衬底 Download PDF

Info

Publication number
CN109075154B
CN109075154B CN201780029547.6A CN201780029547A CN109075154B CN 109075154 B CN109075154 B CN 109075154B CN 201780029547 A CN201780029547 A CN 201780029547A CN 109075154 B CN109075154 B CN 109075154B
Authority
CN
China
Prior art keywords
die
conductive
layer
dielectric layer
substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN201780029547.6A
Other languages
English (en)
Chinese (zh)
Other versions
CN109075154A (zh
Inventor
D·金
J·付
C·云
C-K·金
M·阿尔德利特
C·左
M·韦莱兹
J·金
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Qualcomm Inc
Original Assignee
Qualcomm Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Qualcomm Inc filed Critical Qualcomm Inc
Publication of CN109075154A publication Critical patent/CN109075154A/zh
Application granted granted Critical
Publication of CN109075154B publication Critical patent/CN109075154B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/4853—Connection or disconnection of other leads to or from a metallisation, e.g. pins, wires, bumps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/4857—Multilayer substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/486—Via connections through the substrate with or without pins
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5383—Multilayer substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5384—Conductive vias through the substrate with or without pins, e.g. buried coaxial conductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5389—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/19—Manufacturing methods of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/20—Structure, shape, material or disposition of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L24/25—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of a plurality of high density interconnect connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/061—Disposition
    • H01L2224/0618—Disposition being disposed on at least two different sides of the body, e.g. dual array
    • H01L2224/06181—On opposite sides of the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/25—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of a plurality of high density interconnect connectors
    • H01L2224/251—Disposition
    • H01L2224/2518—Disposition being disposed on at least two different sides of the body, e.g. dual array
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/291—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/2919—Material with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73267—Layer and HDI connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
    • H01L2224/82009—Pre-treatment of the connector or the bonding area
    • H01L2224/8203—Reshaping, e.g. forming vias
    • H01L2224/82035—Reshaping, e.g. forming vias by heating means
    • H01L2224/82039—Reshaping, e.g. forming vias by heating means using a laser
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
    • H01L2224/82009—Pre-treatment of the connector or the bonding area
    • H01L2224/8203—Reshaping, e.g. forming vias
    • H01L2224/82047—Reshaping, e.g. forming vias by mechanical means, e.g. severing, pressing, stamping
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222—Sequential connecting processes
    • H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92244—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a build-up interconnect
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49822—Multilayer substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1515—Shape
    • H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Structure Of Printed Boards (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
CN201780029547.6A 2016-03-18 2017-03-16 背侧钻孔嵌入式管芯衬底 Active CN109075154B (zh)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US15/074,750 2016-03-18
US15/074,750 US10325855B2 (en) 2016-03-18 2016-03-18 Backside drill embedded die substrate
PCT/US2017/022829 WO2017161199A1 (en) 2016-03-18 2017-03-16 Backside drill embedded die substrate

Publications (2)

Publication Number Publication Date
CN109075154A CN109075154A (zh) 2018-12-21
CN109075154B true CN109075154B (zh) 2022-06-03

Family

ID=58455674

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201780029547.6A Active CN109075154B (zh) 2016-03-18 2017-03-16 背侧钻孔嵌入式管芯衬底

Country Status (9)

Country Link
US (1) US10325855B2 (enExample)
EP (1) EP3430644B1 (enExample)
JP (1) JP6679748B2 (enExample)
KR (1) KR102213034B1 (enExample)
CN (1) CN109075154B (enExample)
BR (1) BR112018068970B1 (enExample)
ES (1) ES2821728T3 (enExample)
TW (1) TWI692048B (enExample)
WO (1) WO2017161199A1 (enExample)

Families Citing this family (23)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10373893B2 (en) * 2017-06-30 2019-08-06 Intel Corporation Embedded bridge with through-silicon vias
US10504865B2 (en) * 2017-09-28 2019-12-10 Taiwan Semiconductor Manufacturing Co., Ltd. Package structure and method of manufacturing the same
EP3688798A4 (en) * 2017-09-29 2021-05-19 INTEL Corporation SEMI-CONDUCTOR ENCLOSURE WITH EMBEDDED CONNECTIONS
EP3732719A4 (en) * 2017-12-29 2021-11-17 Intel Corporation MICROELECTRONIC ARRANGEMENTS
TWI733056B (zh) * 2018-09-19 2021-07-11 矽品精密工業股份有限公司 電子封裝件及其製法
US11342243B2 (en) * 2018-09-25 2022-05-24 Intel Corporation Thermal management solutions for embedded integrated circuit devices
US11322428B2 (en) * 2019-12-02 2022-05-03 Advanced Semiconductor Engineering, Inc. Semiconductor device package and method of manufacturing the same
KR102762887B1 (ko) * 2019-12-10 2025-02-07 삼성전기주식회사 전자부품 내장기판
US11289404B2 (en) 2020-01-17 2022-03-29 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device and method
US11715699B2 (en) 2020-03-17 2023-08-01 Amkor Technology Singapore Holding Pte. Ltd. Semiconductor devices and methods of manufacturing semiconductor devices
TWI891722B (zh) * 2020-03-17 2025-08-01 新加坡商安靠科技新加坡控股私人有限公司 半導體裝置和製造半導體裝置的方法
US11302643B2 (en) * 2020-03-25 2022-04-12 Intel Corporation Microelectronic component having molded regions with through-mold vias
US11824031B2 (en) * 2020-06-10 2023-11-21 Advanced Semiconductor Engineering, Inc. Semiconductor package structure with dielectric structure covering upper surface of chip
TWI731745B (zh) * 2020-07-15 2021-06-21 欣興電子股份有限公司 內埋式元件結構及其製造方法
KR102854180B1 (ko) * 2020-07-27 2025-09-03 삼성전기주식회사 전자부품 내장기판
US11367673B2 (en) * 2020-09-02 2022-06-21 Intel Corporation Semiconductor package with hybrid through-silicon-vias
US12230615B2 (en) * 2020-12-30 2025-02-18 UTAC Headquarters Pte. Ltd. Semiconductor packages with vertical passive components
TWI759095B (zh) * 2021-02-04 2022-03-21 欣興電子股份有限公司 封裝結構及其製作方法
WO2022190952A1 (ja) * 2021-03-09 2022-09-15 ソニーセミコンダクタソリューションズ株式会社 半導体装置、半導体装置の製造方法及び電子機器
EP4430663A4 (en) * 2021-11-11 2025-11-05 Applied Materials Inc SEMICONDUCTOR DEVICE HOUSINGS
US12230552B2 (en) 2021-11-18 2025-02-18 Qualcomm Incorporated Recess structure for padless stack via
US20250140748A1 (en) * 2023-10-31 2025-05-01 Intel Corporation Double-sided conductive via
TWI879344B (zh) * 2023-12-25 2025-04-01 友達光電股份有限公司 半導體結構及其製造方法

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104851847A (zh) * 2014-02-14 2015-08-19 恒劲科技股份有限公司 封装装置及其制作方法

Family Cites Families (21)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20020020898A1 (en) * 2000-08-16 2002-02-21 Vu Quat T. Microelectronic substrates with integrated devices
US6744135B2 (en) * 2001-05-22 2004-06-01 Hitachi, Ltd. Electronic apparatus
JP2004186422A (ja) 2002-12-03 2004-07-02 Shinko Electric Ind Co Ltd 電子部品実装構造及びその製造方法
KR100716815B1 (ko) * 2005-02-28 2007-05-09 삼성전기주식회사 칩 내장형 인쇄회로기판 및 그 제조방법
US20080048310A1 (en) 2006-08-25 2008-02-28 Phoenix Precision Technology Corporation Carrier Board Structure Embedded with Semiconductor Component and Method for Fabricating the Carrier Board Structure
US8110899B2 (en) * 2006-12-20 2012-02-07 Intel Corporation Method for incorporating existing silicon die into 3D integrated stack
KR101486420B1 (ko) 2008-07-25 2015-01-26 삼성전자주식회사 칩 패키지, 이를 이용한 적층형 패키지 및 그 제조 방법
KR101484786B1 (ko) * 2008-12-08 2015-01-21 삼성전자주식회사 집적회로 패키지 내장 인쇄회로기판 및 그 제조방법
US8822281B2 (en) 2010-02-23 2014-09-02 Stats Chippac, Ltd. Semiconductor device and method of forming TMV and TSV in WLCSP using same carrier
US9406658B2 (en) 2010-12-17 2016-08-02 Advanced Semiconductor Engineering, Inc. Embedded component device and manufacturing methods thereof
EP2610269A1 (en) * 2011-12-28 2013-07-03 Saudi Basic Industries Corporation Catalyst composition and method for preparing the same
JP5955023B2 (ja) * 2012-02-23 2016-07-20 京セラ株式会社 部品内蔵印刷配線板及びその製造方法
US10049964B2 (en) * 2012-03-23 2018-08-14 STATS ChipPAC Pte. Ltd. Semiconductor device and method of forming a fan-out PoP device with PWB vertical interconnect units
US8786060B2 (en) 2012-05-04 2014-07-22 Advanced Semiconductor Engineering, Inc. Semiconductor package integrated with conformal shield and antenna
US20130337648A1 (en) 2012-06-14 2013-12-19 Bridge Semiconductor Corporation Method of making cavity substrate with built-in stiffener and cavity
US9147663B2 (en) * 2013-05-28 2015-09-29 Intel Corporation Bridge interconnection with layered interconnect structures
US9202803B2 (en) * 2014-03-28 2015-12-01 Intel Corporation Laser cavity formation for embedded dies or components in substrate build-up layers
US9331021B2 (en) * 2014-04-30 2016-05-03 Taiwan Semiconductor Manufacturing Company, Ltd. Chip-on-wafer package and method of forming same
DE102014112407B4 (de) 2014-04-30 2016-12-29 Taiwan Semiconductor Manufacturing Company, Ltd. 3D-Gehäuse mit gestapelten Chips und Verfahren zu dessen Herstellung
US9252127B1 (en) * 2014-07-10 2016-02-02 Invensas Corporation Microelectronic assemblies with integrated circuits and interposers with cavities, and methods of manufacture
US9653438B2 (en) * 2014-08-21 2017-05-16 General Electric Company Electrical interconnect structure for an embedded semiconductor device package and method of manufacturing thereof

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104851847A (zh) * 2014-02-14 2015-08-19 恒劲科技股份有限公司 封装装置及其制作方法

Also Published As

Publication number Publication date
JP6679748B2 (ja) 2020-04-15
EP3430644B1 (en) 2020-07-01
JP2019511120A (ja) 2019-04-18
BR112018068970B1 (pt) 2023-01-31
KR20180124932A (ko) 2018-11-21
KR102213034B1 (ko) 2021-02-04
TW201737394A (zh) 2017-10-16
CN109075154A (zh) 2018-12-21
US20170271266A1 (en) 2017-09-21
WO2017161199A1 (en) 2017-09-21
ES2821728T3 (es) 2021-04-27
US10325855B2 (en) 2019-06-18
EP3430644A1 (en) 2019-01-23
BR112018068970A2 (pt) 2019-03-06
TWI692048B (zh) 2020-04-21

Similar Documents

Publication Publication Date Title
CN109075154B (zh) 背侧钻孔嵌入式管芯衬底
EP2596689B1 (en) Microelectronic elements with post-assembly planarization
CN106489201B (zh) 具有冗余电连接器的互连结构及相关系统与方法
KR101277429B1 (ko) 스택 다이 ｂｇａ 또는 ｌｇａ 컴포넌트 어셈블리
US8810008B2 (en) Semiconductor element-embedded substrate, and method of manufacturing the substrate
KR20140057979A (ko) 반도체 패키지 및 반도체 패키지의 제조 방법
CN111933590B (zh) 封装结构和封装结构制作方法
JP6377178B2 (ja) 埋込型パッケージ基板コンデンサ
US10306770B2 (en) Thin-film capacitor manufacturing method, integrated circuit mounting substrate, and semiconductor device equipped with the substrate
KR101917247B1 (ko) 적층 반도체 패키지 및 그 제조방법
CN115812251A (zh) 包括被配置为电磁干扰屏蔽件的无源设备的封装件
JPWO2005122257A1 (ja) コンデンサを内蔵した半導体装置及びその製造方法
EP2880684B1 (en) Microelectronic assembly
US9728507B2 (en) Cap chip and reroute layer for stacked microelectronic module
CN117223099A (zh) 具有竖直热引脚的高功率裸片散热器
KR20180111840A (ko) 집적 회로(ic) 패키지들 사이의 플렉시블 커넥터를 포함하는 통합 디바이스
US20140167251A1 (en) Semiconductor device, semiconductor module, and manufacturing method for semiconductor device
JP2016219535A (ja) 電子回路装置
TWI615933B (zh) 半導體裝置及其製造方法
US8558353B2 (en) Integrated circuit having an uppermost layer comprising landing pads that are distributed thoughout one side of the integrated circuit
CN117642854A (zh) 玻璃贴片集成到电子装置封装中
US20210057397A1 (en) Electrodeless passive embedded substrate
US20240363503A1 (en) Semiconductor devices with double-sided fanout chip packages
KR20130068485A (ko) 관통 전극을 구비하는 반도체 디바이스, 그것의 제조방법, 반도체 디바이스를 구비한 적층형 패키지 및 적층형 패키지의 제조방법
JP2001298118A (ja) 半導体装置およびその製造方法

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant