BR112018068970A2 - substrato de pastilha embutido em perfuração traseira - Google Patents

substrato de pastilha embutido em perfuração traseira

Info

Publication number
BR112018068970A2
BR112018068970A2 BR112018068970-0A BR112018068970A BR112018068970A2 BR 112018068970 A2 BR112018068970 A2 BR 112018068970A2 BR 112018068970 A BR112018068970 A BR 112018068970A BR 112018068970 A2 BR112018068970 A2 BR 112018068970A2
Authority
BR
Brazil
Prior art keywords
tablet
substrate
conductive pad
back hole
substrate embedded
Prior art date
Application number
BR112018068970-0A
Other languages
English (en)
Other versions
BR112018068970B1 (pt
Inventor
Kim Daeik
Fu Jie
Yun Changhan
Kim Chin-Kwan
Aldrete Manuel
Zuo Chengjie
Velez Mario
Kim Jonghae
Original Assignee
Qualcomm Incorporated
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Qualcomm Incorporated filed Critical Qualcomm Incorporated
Publication of BR112018068970A2 publication Critical patent/BR112018068970A2/pt
Publication of BR112018068970B1 publication Critical patent/BR112018068970B1/pt

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    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5383—Multilayer substrates
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    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/4853—Connection or disconnection of other leads to or from a metallisation, e.g. pins, wires, bumps
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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Structure Of Printed Boards (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)

Abstract

um dispositivo e método de fabricação são fornecidos. o dispositivo inclui um substrato tendo um primeiro lado e um segundo lado oposto, uma cavidade definida dentro do substrato a partir do primeiro lado, uma pastilha acoplada a um piso da cavidade e tendo uma almofada condutora em um lado da pastilha distal ao piso da cavidade. uma camada laminada acoplada ao segundo lado do substrato pode ser incluída. um furo pode ser perfurado, de uma só vez, através de camadas do dispositivo, através da pastilha e através da almofada condutora. o furo se estende através de e é definido dentro da camada laminada (se presente), do segundo lado do substrato, da pastilha e da almofada condutora. um material condutor é fornecido dentro do furo e se estende entre e através da camada laminada (se fornecida), do segundo lado do substrato, da pastilha e da almofada condutora.
BR112018068970-0A 2016-03-18 2017-03-16 Dispositivo e método para fabricação de um substrato de pastilha embutida BR112018068970B1 (pt)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US15/074,750 US10325855B2 (en) 2016-03-18 2016-03-18 Backside drill embedded die substrate
US15/074,750 2016-03-18
PCT/US2017/022829 WO2017161199A1 (en) 2016-03-18 2017-03-16 Backside drill embedded die substrate

Publications (2)

Publication Number Publication Date
BR112018068970A2 true BR112018068970A2 (pt) 2019-03-06
BR112018068970B1 BR112018068970B1 (pt) 2023-01-31

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BR112018068970-0A BR112018068970B1 (pt) 2016-03-18 2017-03-16 Dispositivo e método para fabricação de um substrato de pastilha embutida

Country Status (9)

Country Link
US (1) US10325855B2 (pt)
EP (1) EP3430644B1 (pt)
JP (1) JP6679748B2 (pt)
KR (1) KR102213034B1 (pt)
CN (1) CN109075154B (pt)
BR (1) BR112018068970B1 (pt)
ES (1) ES2821728T3 (pt)
TW (1) TWI692048B (pt)
WO (1) WO2017161199A1 (pt)

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US10373893B2 (en) 2017-06-30 2019-08-06 Intel Corporation Embedded bridge with through-silicon vias
US10504865B2 (en) * 2017-09-28 2019-12-10 Taiwan Semiconductor Manufacturing Co., Ltd. Package structure and method of manufacturing the same
EP3688798A4 (en) * 2017-09-29 2021-05-19 INTEL Corporation SEMI-CONDUCTOR ENCLOSURE WITH EMBEDDED CONNECTIONS
EP3732719A4 (en) * 2017-12-29 2021-11-17 Intel Corporation MICROELECTRONIC ARRANGEMENTS
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JP2019511120A (ja) 2019-04-18
TWI692048B (zh) 2020-04-21
US20170271266A1 (en) 2017-09-21
CN109075154B (zh) 2022-06-03
ES2821728T3 (es) 2021-04-27
JP6679748B2 (ja) 2020-04-15
US10325855B2 (en) 2019-06-18
EP3430644B1 (en) 2020-07-01
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CN109075154A (zh) 2018-12-21

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