TWI692048B - 背側鑽孔嵌入晶粒式基板 - Google Patents
背側鑽孔嵌入晶粒式基板 Download PDFInfo
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- TWI692048B TWI692048B TW106108653A TW106108653A TWI692048B TW I692048 B TWI692048 B TW I692048B TW 106108653 A TW106108653 A TW 106108653A TW 106108653 A TW106108653 A TW 106108653A TW I692048 B TWI692048 B TW I692048B
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- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07
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- H01L21/4853—Connection or disconnection of other leads to or from a metallisation, e.g. pins, wires, bumps
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- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Ceramic Engineering (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
- Structure Of Printed Boards (AREA)
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US15/074,750 | 2016-03-18 | ||
| US15/074,750 US10325855B2 (en) | 2016-03-18 | 2016-03-18 | Backside drill embedded die substrate |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| TW201737394A TW201737394A (zh) | 2017-10-16 |
| TWI692048B true TWI692048B (zh) | 2020-04-21 |
Family
ID=58455674
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| TW106108653A TWI692048B (zh) | 2016-03-18 | 2017-03-16 | 背側鑽孔嵌入晶粒式基板 |
Country Status (9)
| Country | Link |
|---|---|
| US (1) | US10325855B2 (enExample) |
| EP (1) | EP3430644B1 (enExample) |
| JP (1) | JP6679748B2 (enExample) |
| KR (1) | KR102213034B1 (enExample) |
| CN (1) | CN109075154B (enExample) |
| BR (1) | BR112018068970B1 (enExample) |
| ES (1) | ES2821728T3 (enExample) |
| TW (1) | TWI692048B (enExample) |
| WO (1) | WO2017161199A1 (enExample) |
Families Citing this family (23)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US10373893B2 (en) * | 2017-06-30 | 2019-08-06 | Intel Corporation | Embedded bridge with through-silicon vias |
| US10504865B2 (en) * | 2017-09-28 | 2019-12-10 | Taiwan Semiconductor Manufacturing Co., Ltd. | Package structure and method of manufacturing the same |
| EP3688798A4 (en) * | 2017-09-29 | 2021-05-19 | INTEL Corporation | SEMI-CONDUCTOR ENCLOSURE WITH EMBEDDED CONNECTIONS |
| EP3732719A4 (en) * | 2017-12-29 | 2021-11-17 | Intel Corporation | MICROELECTRONIC ARRANGEMENTS |
| TWI733056B (zh) * | 2018-09-19 | 2021-07-11 | 矽品精密工業股份有限公司 | 電子封裝件及其製法 |
| US11342243B2 (en) * | 2018-09-25 | 2022-05-24 | Intel Corporation | Thermal management solutions for embedded integrated circuit devices |
| US11322428B2 (en) * | 2019-12-02 | 2022-05-03 | Advanced Semiconductor Engineering, Inc. | Semiconductor device package and method of manufacturing the same |
| KR102762887B1 (ko) * | 2019-12-10 | 2025-02-07 | 삼성전기주식회사 | 전자부품 내장기판 |
| US11289404B2 (en) | 2020-01-17 | 2022-03-29 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor device and method |
| US11715699B2 (en) | 2020-03-17 | 2023-08-01 | Amkor Technology Singapore Holding Pte. Ltd. | Semiconductor devices and methods of manufacturing semiconductor devices |
| TWI891722B (zh) * | 2020-03-17 | 2025-08-01 | 新加坡商安靠科技新加坡控股私人有限公司 | 半導體裝置和製造半導體裝置的方法 |
| US11302643B2 (en) * | 2020-03-25 | 2022-04-12 | Intel Corporation | Microelectronic component having molded regions with through-mold vias |
| US11824031B2 (en) * | 2020-06-10 | 2023-11-21 | Advanced Semiconductor Engineering, Inc. | Semiconductor package structure with dielectric structure covering upper surface of chip |
| TWI731745B (zh) * | 2020-07-15 | 2021-06-21 | 欣興電子股份有限公司 | 內埋式元件結構及其製造方法 |
| KR102854180B1 (ko) * | 2020-07-27 | 2025-09-03 | 삼성전기주식회사 | 전자부품 내장기판 |
| US11367673B2 (en) * | 2020-09-02 | 2022-06-21 | Intel Corporation | Semiconductor package with hybrid through-silicon-vias |
| US12230615B2 (en) * | 2020-12-30 | 2025-02-18 | UTAC Headquarters Pte. Ltd. | Semiconductor packages with vertical passive components |
| TWI759095B (zh) * | 2021-02-04 | 2022-03-21 | 欣興電子股份有限公司 | 封裝結構及其製作方法 |
| WO2022190952A1 (ja) * | 2021-03-09 | 2022-09-15 | ソニーセミコンダクタソリューションズ株式会社 | 半導体装置、半導体装置の製造方法及び電子機器 |
| EP4430663A4 (en) * | 2021-11-11 | 2025-11-05 | Applied Materials Inc | SEMICONDUCTOR DEVICE HOUSINGS |
| US12230552B2 (en) | 2021-11-18 | 2025-02-18 | Qualcomm Incorporated | Recess structure for padless stack via |
| US20250140748A1 (en) * | 2023-10-31 | 2025-05-01 | Intel Corporation | Double-sided conductive via |
| TWI879344B (zh) * | 2023-12-25 | 2025-04-01 | 友達光電股份有限公司 | 半導體結構及其製造方法 |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20020020898A1 (en) * | 2000-08-16 | 2002-02-21 | Vu Quat T. | Microelectronic substrates with integrated devices |
| US20030002260A1 (en) * | 2001-05-22 | 2003-01-02 | Takehiko Hasebe | Electronic apparatus |
| US20060191711A1 (en) * | 2005-02-28 | 2006-08-31 | Samsung Electro-Mechanics Co., Ltd. | Embedded chip printed circuit board and method of manufacturing the same |
| US20150318246A1 (en) * | 2014-04-30 | 2015-11-05 | Taiwan Semiconductor Manufacturing Company, Ltd. | Chip-on-wafer package and method of forming same |
| US20160013151A1 (en) * | 2014-07-10 | 2016-01-14 | Invensas Corporation | Microelectronic assemblies with integrated circuits and interposers with cavities, and methods of manufacture |
Family Cites Families (17)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2004186422A (ja) | 2002-12-03 | 2004-07-02 | Shinko Electric Ind Co Ltd | 電子部品実装構造及びその製造方法 |
| US20080048310A1 (en) | 2006-08-25 | 2008-02-28 | Phoenix Precision Technology Corporation | Carrier Board Structure Embedded with Semiconductor Component and Method for Fabricating the Carrier Board Structure |
| US8110899B2 (en) * | 2006-12-20 | 2012-02-07 | Intel Corporation | Method for incorporating existing silicon die into 3D integrated stack |
| KR101486420B1 (ko) | 2008-07-25 | 2015-01-26 | 삼성전자주식회사 | 칩 패키지, 이를 이용한 적층형 패키지 및 그 제조 방법 |
| KR101484786B1 (ko) * | 2008-12-08 | 2015-01-21 | 삼성전자주식회사 | 집적회로 패키지 내장 인쇄회로기판 및 그 제조방법 |
| US8822281B2 (en) | 2010-02-23 | 2014-09-02 | Stats Chippac, Ltd. | Semiconductor device and method of forming TMV and TSV in WLCSP using same carrier |
| US9406658B2 (en) | 2010-12-17 | 2016-08-02 | Advanced Semiconductor Engineering, Inc. | Embedded component device and manufacturing methods thereof |
| EP2610269A1 (en) * | 2011-12-28 | 2013-07-03 | Saudi Basic Industries Corporation | Catalyst composition and method for preparing the same |
| JP5955023B2 (ja) * | 2012-02-23 | 2016-07-20 | 京セラ株式会社 | 部品内蔵印刷配線板及びその製造方法 |
| US10049964B2 (en) * | 2012-03-23 | 2018-08-14 | STATS ChipPAC Pte. Ltd. | Semiconductor device and method of forming a fan-out PoP device with PWB vertical interconnect units |
| US8786060B2 (en) | 2012-05-04 | 2014-07-22 | Advanced Semiconductor Engineering, Inc. | Semiconductor package integrated with conformal shield and antenna |
| US20130337648A1 (en) | 2012-06-14 | 2013-12-19 | Bridge Semiconductor Corporation | Method of making cavity substrate with built-in stiffener and cavity |
| US9147663B2 (en) * | 2013-05-28 | 2015-09-29 | Intel Corporation | Bridge interconnection with layered interconnect structures |
| CN104851847B (zh) * | 2014-02-14 | 2017-09-08 | 恒劲科技股份有限公司 | 封装装置及其制作方法 |
| US9202803B2 (en) * | 2014-03-28 | 2015-12-01 | Intel Corporation | Laser cavity formation for embedded dies or components in substrate build-up layers |
| DE102014112407B4 (de) | 2014-04-30 | 2016-12-29 | Taiwan Semiconductor Manufacturing Company, Ltd. | 3D-Gehäuse mit gestapelten Chips und Verfahren zu dessen Herstellung |
| US9653438B2 (en) * | 2014-08-21 | 2017-05-16 | General Electric Company | Electrical interconnect structure for an embedded semiconductor device package and method of manufacturing thereof |
-
2016
- 2016-03-18 US US15/074,750 patent/US10325855B2/en active Active
-
2017
- 2017-03-16 CN CN201780029547.6A patent/CN109075154B/zh active Active
- 2017-03-16 KR KR1020187029732A patent/KR102213034B1/ko active Active
- 2017-03-16 ES ES17714617T patent/ES2821728T3/es active Active
- 2017-03-16 JP JP2018549181A patent/JP6679748B2/ja active Active
- 2017-03-16 BR BR112018068970-0A patent/BR112018068970B1/pt active IP Right Grant
- 2017-03-16 WO PCT/US2017/022829 patent/WO2017161199A1/en not_active Ceased
- 2017-03-16 EP EP17714617.2A patent/EP3430644B1/en active Active
- 2017-03-16 TW TW106108653A patent/TWI692048B/zh active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20020020898A1 (en) * | 2000-08-16 | 2002-02-21 | Vu Quat T. | Microelectronic substrates with integrated devices |
| US20030002260A1 (en) * | 2001-05-22 | 2003-01-02 | Takehiko Hasebe | Electronic apparatus |
| US20060191711A1 (en) * | 2005-02-28 | 2006-08-31 | Samsung Electro-Mechanics Co., Ltd. | Embedded chip printed circuit board and method of manufacturing the same |
| US20150318246A1 (en) * | 2014-04-30 | 2015-11-05 | Taiwan Semiconductor Manufacturing Company, Ltd. | Chip-on-wafer package and method of forming same |
| US20160013151A1 (en) * | 2014-07-10 | 2016-01-14 | Invensas Corporation | Microelectronic assemblies with integrated circuits and interposers with cavities, and methods of manufacture |
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| JP6679748B2 (ja) | 2020-04-15 |
| EP3430644B1 (en) | 2020-07-01 |
| JP2019511120A (ja) | 2019-04-18 |
| BR112018068970B1 (pt) | 2023-01-31 |
| KR20180124932A (ko) | 2018-11-21 |
| KR102213034B1 (ko) | 2021-02-04 |
| TW201737394A (zh) | 2017-10-16 |
| CN109075154A (zh) | 2018-12-21 |
| CN109075154B (zh) | 2022-06-03 |
| US20170271266A1 (en) | 2017-09-21 |
| WO2017161199A1 (en) | 2017-09-21 |
| ES2821728T3 (es) | 2021-04-27 |
| US10325855B2 (en) | 2019-06-18 |
| EP3430644A1 (en) | 2019-01-23 |
| BR112018068970A2 (pt) | 2019-03-06 |
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