CN108987457B - 高电压半导体装置 - Google Patents

高电压半导体装置 Download PDF

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CN108987457B
CN108987457B CN201810161000.8A CN201810161000A CN108987457B CN 108987457 B CN108987457 B CN 108987457B CN 201810161000 A CN201810161000 A CN 201810161000A CN 108987457 B CN108987457 B CN 108987457B
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high voltage
semiconductor device
semiconductor
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CN108987457A (zh
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金宁培
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Aisi Kaifang Semiconductor Co ltd
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Key Foundry Co Ltd
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  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
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Abstract

本发明提供一种高电压半导体装置。所述高电压半导体装置包括第一区、第二区和互连区。第一区包括横向扩散金属氧化物半导体(LDMOS)装置。LDMOS装置包括：N型高浓度源极区；P型高浓度拾取区，其中，N型高浓度源极区和P型高浓度拾取区形成在P型第一主体区中；漏极区；P型掩埋掺杂层，形成在绝缘层的底表面下面。第二区包括：第二主体区；P型第一高掺杂区和P型第二高掺杂区，其中，P型第一高掺杂区和P型第二高掺杂区形成在第二主体区中；N型第三高掺杂区；第二掩埋掺杂区。互连区将第一区连接到第二区。

Description

高电压半导体装置
本申请要求于2017年5月31日提交到韩国知识产权局的第 10-2017-0067955号韩国专利申请的权益，该韩国专利申请的全部公开出于所有目的通过引用包含于此。
技术领域
本公开涉及一种高电压半导体装置。本公开也涉及一种用于阻止包括在高电压半导体装置中的低电压区与高电压区二者之间的漏电流以及用于约束可易于在高电压区中发生的寄生晶体管的操作的高电压半导体装置。
背景技术
通常，互补金属氧化物半导体(CMOS)装置的高电压晶体管在高电压下操作，并广泛用于诸如非易失性存储器装置或易失性存储器装置的半导体装置的操作电路。高电压晶体管包括足够厚以具有高电压的击穿电压的栅极绝缘层。
作为针对高电压的功率装置的横向扩散金属氧化物半导体(LDMOS)晶体管具有诸如快切换速度、高输入阻抗、低功耗以及与COMS处理的兼容性的一些优势。LDMOS晶体管广泛用于诸如汽车的显示驱动集成电路、功率转换器、电机控制器或电源的各种功率装置。对于功率装置，特定的导通电阻和击穿电压是对装置的性能起主要影响的重要因素。
相反，低电压晶体管是在低电压下操作的装置，并广泛用于诸如逻辑装置的半导体装置的操作电路。由于低电压晶体管在比较低的电压下操作，因此低电压晶体管它的栅极绝缘层的厚度比高电压晶体管的栅极绝缘层的厚度薄。
典型地，对于以显示驱动集成电路或闪存闻名的非易失性半导体的制造，低电压晶体管和高电压晶体管二者必须形成在同一半导体基底中。针对每个半导体装置所需的高电压的电平被确定为从10伏特V至数十伏特，然而低电压的电平为了高性能和减小的芯片尺寸而快速减小。出于这种原因，当半导体装置的高密度集成被实现时，高电压需求与低电压需求之间的差异变得更大。因此，在同一半导体基底中形成低电压晶体管和高电压晶体管变得更加困难。
具有大于或等于600V的电压的高电压半导体装置可用于具有高电压需求的电机驱动或发光二极管照明。高电压半导体装置被划分为高电压区和低电压区，并且可能有必要在高电压区与低电压区之间形成隔离区。具体地讲，高电压区使用具有低掺杂浓度的阱区，这可引起晶体管中的寄生损失，造成设计缺陷和在完成的产品操作时的错误。
发明内容
提供本发明内容从而以简化的形式介绍构思的选择，其将在下面的具体实施方式中被进一步描述。本发明内容不意在确定所要求保护的主题的关键特征或必要特征，也不意在用于辅助确定所要求保护的主题的范围。
在一个总体方面，一种高电压半导体装置包括包含第一区和第二区以及连接第一区和第二区的互连区的半导体基底。第一区包括：N型第一半导体区，形成在半导体基底上；N型漏极区，形成在N型第一半导体区中；P型第一主体区，形成在半导体基底上；N型源极区，形成在P型第一主体区中；栅电极，形成在N型源极区与N型漏极区之间。第二区包括：N型第二半导体区，形成在半导体基底上；P型第二主体区，形成在N型第二半导体区中。互连区形成在半导体基底的表面上并包括：第一绝缘层，形成在N型第一半导体区与N型第二半导体区之间；金属互连部，形成在第一绝缘层上；隔离区，形成为直接接触第一绝缘层。
隔离区可包括P型结隔离区。P型结隔离区可形成为与半导体基底一样的导电性，并使用比半导体基底的掺杂浓度高的浓度被掺杂。
P型结隔离区可具有比半导体基底的浓度大2个数量级以上的浓度。
所述高电压半导体装置还可包括：N型第一掩埋掺杂层，形成在N型第一半导体区与半导体基底之间；N型第二掩埋掺杂层，形成在N型第二半导体区与半导体基底之间。
金属互连部可将N型漏极区电连接到P型第二主体区。
第二区形成在半导体基底的表面上并还可包括：P型第一高掺杂区和P 型第二高掺杂区，形成在P型第二主体区中；第二绝缘层，形成在P型第一高掺杂区与P型第二高掺杂区之间；N型第三高掺杂区，形成在N型第二半导体区中；第三绝缘层，形成在P型第二高掺杂区与N型第三高掺杂区之间。
所述高电压半导体装置在第二区的N型第二半导体区中还可包括：N型第二阱区，形成为直接连接到第一绝缘层。
金属互连部可将N型漏极区电连接到P型第一高掺杂区。
第一区还可包括形成为靠近P型第一主体区的第一深沟槽。隔离区还可包括从第一绝缘层延伸到半导体基底的多个第二深沟槽。
第一深沟槽可连接到多个第二深沟槽。
第一深沟槽和多个第二深沟槽的内部可使用氧化膜填充。
所述高电压半导体装置还可包括环绕第一深沟槽的P型阱区。
在另一总体方面，一种高电压半导体装置包括第一区、第二区和互连区。第一区包括横向扩散金属氧化物半导体(LDMOS)装置。LDMOS装置包括： N型高浓度源极区；P型高浓度拾取区，其中，N型高浓度源极区和P型高浓度拾取区形成在第一P型主体区中；漏极区；P型掩埋掺杂层，形成在绝缘层的底表面下面。第二区包括：第二主体区；P型第一高掺杂区和P型第二高掺杂区，其中，P型第一高掺杂区和P型第二高掺杂区形成在第二主体区中；N型第三高掺杂区；第二掩埋掺杂区。互连区将第一区连接到第二区。
第一区还可包括第一深沟槽，互连区可包括第二深沟槽。
第一深沟槽和第二深沟槽可包围LDMOS装置。
P型阱区可环绕第一深沟槽。
第二深沟槽可包括多个深沟槽。
所述多个深沟槽可形成在第一外延层和第二外延层上方。
金属互连部可连接第一区和第二区。
其他特征和方面从下面的具体实施方式、附图和权利要求将是清楚的。
附图说明
图1A和图1B是高电压半导体装置的示例的俯视图。
图2是高电压半导体装置的示例的截面图。
图3A和图3B是根据示例的具有附加特征的在图2中所示的高电压半导体装置的截面图。
图4是高电压半导体装置的另一示例的俯视图。
图5A和图5B是高电压半导体装置的另一示例的截面图。
图6是根据另一示例的高电压半导体装置的俯视图。
图7A和图7B是根据另一示例的高电压半导体装置的截面图。
贯穿附图和具体实施方式，相同的参考标号表示相同的元件。为了清楚、说明和便利，附图可不按比例，并且附图中的元件的相对大小、比例和描写可被夸大。
具体实施方式
提供下面的详细描述以帮助读者获得对在此描述的方法、设备和/或系统的全面理解。然而，在理解本申请的公开后，在此描述的方法、设备和/或系统的各种变化、修改和等同物将是清楚的。例如，在此描述的操作的顺序仅是示例，操作的顺序不被局限于在此阐述的顺序，除了必须按特定次序发生的操作之外，在此描述的操作的顺序可如在理解本申请的公开后将清楚的那样进行改变。此外，为了更加清楚和简洁，本领域中已知的特征的描述可被省略。
在此描述的特征可以以不同的形式来实现，并且不被解释为受限于在此描述的示例。相反，在此描述的示例仅被提供以示出在理解本申请的公开之后将是清楚的实施在此描述的方法、设备和/或系统的许多可行方式中的一些方式。
本公开的示例可描述一种能够通过在基底与外延层之间使用高度掺杂层来阻止寄生晶体管进行操作的高电压半导体装置。
本公开的示例可描述一种能够通过在高电压区与低电压区之间添加高浓度阱区来稳定地操作低电压区而不管高电压区如何的高电压半导体装置。
提供本公开的示例以介绍一种能够通过在高电压区与低电压区之间使用深沟槽结构位于其中的隔离结构来有效地将高电压区与低电压区彼此分开的高电压半导体装置。
贯穿说明书，当诸如层、区域或基底的元件被描述为在另一元件“之上”、“连接到”或“结合到”另一元件时，它可直接在所述另一元件“之上”、“连接到”或“结合到”所述另一元件，或者可存在位于它们中间的一个或多个其他元件。相反，当元件被描述为“直接”在另一元件“之上”、“直接连接到”或“直接结合到”另一元件时，不存在位于它们中间的其他元件。
尽管在此可使用诸如“第一”、“第二”和“第三”的术语，以描述各种构件、组件、区域、层或部分，但是这些构件、组件、区域、层或部分不受这些术语的限制。相反，这些术语仅用于将一个构件、组件、区域、层或部分与另一构件、组件、区域、层或部分区分开来。因此，在不脱离示例的教导的情况下，在此描述的示例中所称的第一构件、组件、区域、层或部分也可被称为第二构件、组件、区域、层或部分。
为了便于描述，可在此使用诸如“在…之上”、“上面的”、“在…之下”和“下面的”的空间相对术语，以描述在附图中所示的一个元件与另一元件的关系。空间相对术语意在包含除了在附图中描述的方位之外的使用或操作中的装置的不同方位。例如，如果在附图中的装置被翻转，则被描述为在另一元件“之上”或“上面”的元件其后将位于所述另一元件“之下”和“下面”。因此，术语“在…之上”根据装置的空间方向包括之上和之下两种方向。装置可被不同地定向(旋转90度或朝向其他方向)，并相应地解释在此使用的空间相对术语。
在此使用的术语仅用于描述各个示例，但不用于限制本公开。除非上下文另外清楚地指示，否则单数形式也意在包括复数形式。术语“包括”、“包含”和“具有”指定存在叙述的特征、数量、操作、构件、元件和/或它们的组合，但不排除存在或添加一个或多个其他特征、数量、操作、构件、元件和/或它们的组合。
由于制造技术和/或公差，在附图中所示的形状的变化可能出现。因此，在此描述的示例不限于在附图中所示的特定形状，而是包括在制造期间出现的形状的改变。
在此描述的示例的特征可以以在理解本申请的公开后将清楚的各种方式组合。此外，尽管在此描述的示例具有多种配置，但是在理解本申请的公开后将清楚的其他配置是可行的。
图1A和图1B是高电压半导体装置的示例的俯视图。
如在图1A和图1B中所示，高电压半导体装置包括：第一区100、第二区200、横向扩散金属氧化物半导体(LDMOS)装置300、N型结隔离区105 和P型结隔离区410。第一区100表示在低电压条件下发生操作的区域。第二区200表示在高电压条件下发生操作的区域。低电压可表示小于或等于20V 的电压，高电压可表示在200V至1000V的范围内的电压。这里，LDMOS 装置300被N型结隔离区105和P型结隔离区410包围，因此低电压区(即，第一区100)和高电压区(即，第二区200)彼此被区分。图1A示出LDMOS 装置300被包括在高电压区(即，第二区200)中的情况。图1B示出LDMOS 装置300被包括在低电压区(即，第一区100)中的情况。这里，LDMOS装置300起到将第一区100的信号传递到第二区200以及反之亦然的作用。LDMOS装置300表示横向扩散金属氧化物半导体装置，但是扩展漏极金属氧化物半导体(EDMOS)装置、双扩散金属氧化物半导体(DMOS)装置或高电压装置可被包括来代替LDMOS装置300。LDMOS装置300可起到电平移位器的作用。因为从大约200V至大约1000V的范围内的高电压可被施加到LDMOS装置300的漏极区，所以LDMOS装置300是能够经受相对高的电压的结构。
在下文中，参照作为通过沿图1A或图1B中的线X-X剖开而做出的截面图的图2、图3A和图3B，来描述高电压半导体装置的每个组件的详细特征。
图2是根据示例的高电压半导体装置的截面图。
如在图2中所示，高电压半导体装置包括在低电压条件下发生操作的第一区100和在高电压条件下发生操作的第二区200。低电压可小于或等于 20V，高电压的范围可以是从大约200V至1000V。高电压半导体装置可以是低电压与高电压的间隙非常大的半导体装置。这里，LDMOS装置300被包括在第一区100中。LDMOS装置300是能够经受相对高的电压的结构。换言之，从大约200至大约1000V的范围内的高电压可被施加到LDMOS装置 300的漏极区140。LDMOS装置300起到将第一区100的信号传递到第二区 200的作用。存在进行第一区100与第二区200之间的电连接的互连区400。
第一区100形成在在P型基底10上形成的P型外延层20中。由于P型外延层20具有与P型基底10相同的导电类型，因此将它们认作一个半导体基底是合理的。第一区100包括N型结隔离区105。N型结隔离区105形成在绝缘层125下面，以将LDMOS装置300与第一区100分开。为了简化该工艺，可在与制造N型第一半导体区110的条件相同的条件下制造N型结隔离区105。因此，N型结隔离区105的深度与N型第一半导体区110的深度相同。
LDMOS装置300形成在P型外延层20中，并将第一区100的信号传递到第二区200。这里，LDMOS装置300表示横向扩散金属氧化物半导体装置。可使用EDMOS装置、DMOS装置或高电压装置来代替LDMOS装置300。 LDMOS装置300可起到电平移位器的作用。
LDMOS装置300包括均形成在P型第一主体区120中的N型高浓度源极区190和P型高浓度拾取区195。P型高浓度拾取区195是关于P型第一主体区120的拾取区。由于N型高浓度源极区190和P型高浓度拾取区195彼此接触，所以偏置电压被同时施加到该两个区域。地电压可被同时施加到该两个区域。LDMOS装置300包括形成在N型第一半导体区110中的具有高浓度的漏极区140。
N型第一半导体区110被视为漂移区。在这种情况下，N型第一半导体区110在N型掺杂剂被离子注入到P型外延层20中并且该掺杂剂通过高温退火被扩散和被生成之后被形成。另外，N型第一半导体区110可被生成为倒阱(retrograde well)区。
另外，LDMOS装置300还包括形成在具有高浓度的源极区190与漏极区140之间并部分在绝缘层170之上的栅电极180。绝缘层170相对厚。绝缘层170(诸如，硅的局部氧化(LOCOS)绝缘层)位于栅电极180与漏极区140之间。绝缘层170可起到用于降低漏极区140的高的电场的降低表面场(RESURF)的作用，以使高的电场不施加到栅电极180下面的栅极绝缘层(未示出)。
另外，LDMOS装置300还包括在N型第一半导体区110中形成为与绝缘层170的底表面分开的P型掩埋掺杂层130。在一个示例中，P型掩埋掺杂层130存在于绝缘层170的下面。P型掩埋掺杂层130可与LOCOS绝缘层分开或与LOCOS绝缘层紧邻。也就是说，LDMOS装置300中的P型掩埋掺杂层130不必附连于表面。根据本公开的另一示例，存在与作为第一P型掩埋掺杂层130的P型掩埋掺杂层分开的另一P型掩埋掺杂层(例如，第二P型掩埋掺杂层)。P型掩埋掺杂层130可包括彼此分开的多个P型掩埋层。存在 P型掩埋掺杂层130可使耗尽区能够以反向偏置条件容易地形成在N型第一半导体区110中的效果。
第二区200形成在P型外延层20中。第二区200包括N型第二半导体区210、P型第二主体区220、P型第一高掺杂区250、P型第二高掺杂区270 和N型第三高掺杂区280。P型第一高掺杂区250和P型第二高掺杂区270 形成在P型第二主体区220中。另一方面，N型第三高掺杂区280形成在N 型第二半导体区210中，并且如果偏置电压被施加到N型第二半导体区210，则N型第三高掺杂区280充当路径。这里，P型第一高掺杂区250使用金属互连部430连接到LDMOS装置300的漏极区140。P型第一高掺杂区250和 P型第二高掺杂区270二者形成在P型第二主体区220中。
第二绝缘层260形成在P型第一高掺杂区250与P型第二高掺杂区270 之间。第三绝缘层290还形成在P型第二高掺杂区270与N型第三高掺杂区 280之间。需要另一绝缘层295来将N型第三高掺杂区280与它的外围装置电分开。
如果大于或等于阈值电压的电压被施加到LDMOS装置300的栅电极 180，因此LDMOS装置300被导通，则电流被施加到LDMOS装置300。因此，LDMOS装置300的漏极区140的电势变低。LDMOS装置300的漏极区 140使用金属互连部430电连接到P型第二主体区220内的P型第一高掺杂区250。因此，如果漏极区140的电势变低，则P型第二主体区220中的P 型第一高掺杂区250的电势也变低。最后，在同一P型第二主体区220中的 P型第一高掺杂区250和P型第二高掺杂区270可具有不同的电势。也就是说，在P型第二主体区220的P型第二高掺杂区270与LDMOS装置300的漏极区140之间出现电势差。由于该电势差，导通LDMOS装置300的低电压的第一信号表现为在第二区200中势电平改变的第二信号。如上所述，为了该电势差，P型第一高掺杂区250和P型第二高掺杂区270在第二区200 中通过第二绝缘层260而在P型第二主体区220中彼此分开。
除了P型第二主体区220之外，其他装置(诸如，低电压/高电压装置、电容器和双极结型晶体管)可被包括在第二区200中。
第一互连区400(即，互连区400)形成在外延层20上方，并包括电连接第一区100和第二区200的金属互连部430。具有高的击穿电压的第一互连区400还包括第一绝缘层420。第一绝缘层420可具有LOCOS氧化层或沟槽结构，LOCOS氧化层可以是厚的。第一互连区400还包括形成在N型第一半导体区110与N型第二半导体区210之间的P型结隔离区410，因此LDMOS装置300与第二区200电分开。浓度高于P型外延层20的浓度的P 型结隔离区410被插入。例如，如果P型外延层20的掺杂浓度在1E13/cm3至1.5E14/cm3的范围内，则P型结隔离区410的掺杂浓度在1E15/cm3至 1E17/cm3的范围内，以具有比P型外延层20或P型基底10的浓度大2个数量级或2个数量级以上的浓度。P型结隔离区410能够更容易地将N型第一半导体区110与N型第二半导体区210分开，以减少漏电流的出现。也就是说，第一互连区400阻止电流从LDMOS装置300泄漏到第二区200。另外，存在使第二区200的N型第二半导体区210与LDMOS装置300的N型第一半导体区110之间的距离减小的效果。
金属互连部430形成在具有LOCOS氧化层的第一绝缘层420上。金属互连部430用于在LDMOS装置300的漏极区140与在高的击穿电压(或者，高电压)的条件下发生操作的第二区200之间传递和接收信号。这里，LOCOS 氧化层可使用沟槽层来代替，而不使用LOCOS氧化层。在图2中，由于多个绝缘层125、170、420、260、290、295中的所有绝缘层在同一阶段中同时形成，因此，它们由相同的材料制作并具有相同的厚度。绝缘层125、170、 260、290、295、420的结构可以是LOCOS或沟槽形状。
图3A和图3B是基于在图2中所示的高电压半导体装置的具有附加特征的高电压半导体装置的示例的截面图。
使用图3A和图3B来描述添加到图2的高电压半导体装置的附加特征。
如在图3A中所示，在根据本公开的示例的高电压半导体装置中，LDMOS 装置300还包括设置在漏极区140下面的N型第一阱区150。N型第一阱区 150阻止水平寄生晶体管。另外，N型第一阱区150具有环绕漏极区140的结构，并可被形成为导向环。在LDMOS装置300中，N型第一半导体区110、第一阱区150和漏极区140的浓度从最低至最高被排序。漏极区140的电阻成为总体上最低的，也成为导通电阻(Ron)。
第二区200还包括形成在N型第二半导体区210中的N型第二阱区230 和形成在N型第二半导体区210与P型基底10之间的N型第二掩埋掺杂层 240。这里，N型第二阱区230形成在第一互连区400的第一绝缘层420下面，以阻止横向漏电流。例如，寄生晶体管的操作可通过横向的P型第二主体区 220、N型第二半导体区210和P型结隔离区410在基于基底表面的横向方向上出现。N型第二阱区230被生成，以阻止寄生晶体管。因此，作为寄生晶体管出现的横向漏电流被阻止。
另外，寄生晶体管的操作可在基于基底的表面的垂直方向上出现。垂直方向上的寄生晶体管的操作可在从P型第二主体区220至N型第二半导体区 210和P型基底10的方向上出现。为了阻止种情况，N型第二掩埋掺杂层240 形成在第二区200的N型第二半导体区210与P型基底10之间。具有高浓度的N型第二掩埋掺杂层240具有在1E18/cm3至1E20/cm3的范围内的比N 型第二半导体区210的掺杂浓度高得多的掺杂浓度。
如在图3B中所示，LDMOS装置300还包括形成在N型第一半导体区 110与P型基底10之间的N型第一掩埋掺杂层160。在LDMOS装置300的漏极区140下面的第一掩埋掺杂层160被布置为经受隔离区的高的击穿电压。也就是说，具有高浓度的第一掩埋掺杂层160阻止寄生电容的产生。高浓度第一掩埋掺杂层160的浓度具有1E18cm3至1E20/cm3的掺杂浓度。
根据本公开的示例的高电压半导体装置显著提高了在装置的大批量生产期间的生产力。半导体制造工艺大多数使用P型基底10，因此，P型外延层 20是被最多开发和使用的。如果使用N型外延层，则可由于改变了所使用的设备而在制造工艺中导致延误。
为了改善以上缺点，根据本公开的示例的高电压半导体装置通过在P型基底10上形成第一掩埋掺杂层160和第二掩埋掺杂层240并将外延层开发为 P型层，来减少制造时间。因此，高电压半导体装置电保护位于第二区200 中的装置，并且整个电路的尺寸也被减小。本公开使用P型外延层20而不是使用N型外延层来提高生产装置的能力。
描述本公开的另一示例(未示出)。
在第一互连区400中，外延层20形成在第一绝缘层420的底表面下面，而不形成P型结隔离区410。在这个示例中，为了获得必要的耗尽区，需要扩大第二区200的N型第二半导体区210与LDMOS装置300的N型第一半导体区110之间的距离。在这种情况下，不形成N型第二半导体区210中的 N型第二阱区230和N型第一半导体区110中的N型第一阱区150。
图4是另一高电压半导体装置的示例的俯视图。
如在图4中所示，根据示例的高电压半导体装置包括：第一区100、第二区200、横向扩散金属氧化物半导体(LDMOS)装置300、第一深沟槽510 和第二深沟槽520。这里，LDMOS装置300由第一深沟槽510和第二深沟槽 520包围，因此，LDMOS装置300与第一区100和第二区200分开。
在下文中，参照作为通过沿图4中的Y与Y之间的线剖开而做出的截面图的图5A和图5B，来描述高电压半导体装置的每个组件的详细特征。
图5A和图5B是根据另一示例的高电压半导体装置的截面图。
如在图5A和图5B中所示，高电压半导体装置包括：第一区100、第二区200、横向扩散金属氧化物半导体(LDMOS)装置300和第二互连区500。图5A和图5B示出使用N型第一外延层30和N型第二外延层40而不是使用P型外延层20的示例。N型第一外延层30和N型第二外延层40形成在P 型基底10上。N型第一外延层30和N型第二外延层40可同时形成在P型基底10上。N型第一外延层30和N型第二外延层40可成为N型半导体基底。
第一区100形成在在P型基底10上形成的N型第一外延层30中。第一区100包括第一深沟槽510。第一深沟槽510将靠近LDMOS装置300形成的晶体管与LDMOS装置300电分开。
LDMOS装置300形成在N型第一外延层30中，并将第一区100的信号传递到第二区200。LDMOS装置300包括形成在P型第一主体区120中的源极区190和形成在N型第一外延层30中的漏极区140。另外，LDMOS装置 300还包括形成在源极区190与漏极区140之间并部分地形成在绝缘层170 上的栅电极180。另外，LDMOS装置300还包括与位于N型第一外延层30中的绝缘层170的底表面分开的P型掩埋掺杂层130。
第二区200形成在N型第二外延层40中。第二区200包括：N型第二外延层40、第二主体区220、P型第一高掺杂区250和P型第二高掺杂区270、以及N型第三高掺杂区280。P型第一高掺杂区250和P型第二高掺杂区270 形成在第二主体区220中。第二绝缘层260形成在P型第一高掺杂区250与 P型第二高掺杂区270之间。第三绝缘层290形成在P型第二高掺杂区270 与N型第三高掺杂区280之间。还可需要绝缘层295来将N型第三高掺杂区 280与它的外围装置分开。
第二互连区500形成在N型第一外延层30与N型第二外延层40之间，并使用金属互连部430来电连接第一区100和第二区200。第二互连区500 包括形成在N型第一外延层30与N型第二外延层40之间的第二深沟槽520。 N型外延层由第二深沟槽520划分为N型第一外延层30和N型第二外延层 40。第二深沟槽520代替P型结隔离区410被包括，并减少第二互连区500 的宽度。与使用P型结隔离区410相比，使用第二深沟槽520提高了击穿电压。第二深沟槽520的深度表示从LOCOS氧化层的底表面至P型基底10的距离。
这里，为了增强隔离功能，第一深沟槽510和第二深沟槽520的内部可使用绝缘膜填充。例如，绝缘膜可以是多个氧化层。对于氧化层，可使用低电压化学气相沉淀(LPCVD)氧化层和其他材料(诸如，磷硅酸盐玻璃(PSG)、硼磷硅酸盐玻璃(BPSG))。LPCVD氧化层或四乙基原硅酸盐(TEOS)材料可先被蒸发，然后PSG或BPSG材料可在LPCVD氧化层或TEOS材料上被蒸发。PSG或BPSG材料可通过化学气相沉淀(CVD)方法来填充深沟槽的内部，因此各个深沟槽的内部的中间部分彼此不接触，从而在多个深沟槽的中部存在气隙。另外，第一深沟槽510和第二深沟槽520通过蒸发绝缘层的第一工艺和使用导电材料(诸如，多晶硅)填充它们的第二工艺被生成。第一深沟槽510和第二深沟槽520的深度可以是10μm至30μm。第一深沟槽510 和第二深沟槽520可在同一阶段中同时形成。第一深沟槽510和第二深沟槽 520彼此接触。
高电压半导体装置还包括环绕第一深沟槽510的P型阱区115。这种结构可提高击穿电压。
图6是高电压半导体装置的另一示例的俯视图。
如在图6中所示，根据另一示例的高电压半导体装置包括：第一区100、第二区200、横向扩散金属氧化物半导体(LDMOS)装置300、以及第一深沟槽510和多个第二深沟槽520。这里，LDMOS装置300被第一深沟槽510 和多个第二深沟槽520围绕。因此，第一区100和第二区200彼此分开。与图5A和图5B不同，图6的第二深沟槽520被建造为包括多个沟槽，这增强了隔离功能。
在下文中，参照作为通过沿图6中的Z与Z之间的线剖开而做出的截面图的图7A和图7B，来描述高电压半导体装置的每个组件的详细特征。
图7A和图7B是根据另一示例的高电压半导体装置的另一示例的截面图。
如在图7A和图7B中所示，高电压半导体装置包括：第一区100、第二区200、横向扩散金属氧化物半导体(LDMOS)装置300和第二互连区500。
第二互连区500形成在第一外延层30和第二外延层40上方，并使用金属互连部430电连接第一区100和第二区200。第二互连区500包括形成在 LDMOS装置300与第二区200之间的第二深沟槽520。在一个示例中，包括在第二深沟槽520中的深沟槽的数量可比深沟槽521至523的数量更多或更少。第二深沟槽520的数量越多，击穿电压提高得越高。在这种情况下，第二深沟槽520可需要至少两个沟槽。简言之，在LDMOS装置300与第一区 100之间，单个深沟槽形成为如在图5A和图5B中所示，或者两个或更多个深沟槽可形成为如在图7A和图7B中所示。
另外，靠近第一深沟槽510形成的P型阱区115还被包括，这有助于提高击穿电压。
如在图5A、图5B、图7A和图7B 中所示，在具有高的击穿电压的隔离区中，第一掩埋掺杂层160可不形成在LDMOS装置300的漏极区140下面。然而，需要形成在第二区200下面的第二掩埋掺杂区240，以阻止垂直寄生晶体管。
第二互连区500在高的内部压力隔离的内部使用深沟槽代替使用结端子的结构，使得LDMOS装置300与第二区200之间的漏电流完全被阻断。根据本公开的示例的高电压半导体装置具有能够基于深沟槽的深度、距离和数量而不基于结的耗尽来控制具有高的击穿电压的隔离区的结构，因此能够推广到更高的击穿电压。
虽然本公开包括特定示例，但是在不脱离权利要求和它们的等同物的精神和范围的情况下，可在这些示例中做出形式上和细节上的各种改变，这在理解本申请的公开之后将是清楚的。在此描述的示例将被认为仅是描述性意义，而不是用于限制的目的。在每个示例中的特征和方面的描述将被认为可适用于其他示例中的相似特征或方面。如果描述的技术以不同的顺序被执行，和/或如果描述的系统、构架、装置或电路中的组件以不同的方式被组合和/ 或被其他组件或它们的等同物替换或补充，则可获得合适的结果。因此，本公开的范围不是由具体实施方式来限定，而是由权利要求和它们的等同物来限定，在权利要求和它们的等同物的范围内的所有改变将被解释为包括在本公开中。

Claims (12)

1.一种高电压半导体装置，包括：
半导体基底；
第一区，形成在半导体基底中，第一区包括：
N型第一半导体区；
N型漏极区，形成在N型第一半导体区中；
P型第一主体区；
N型源极区，形成在P型第一主体区中；和
栅电极，形成在N型源极区与N型漏极区之间；
第二区，形成在半导体基底中，第二区包括：
N型第二半导体区；
N型第二阱区，形成在N型第二半导体区中；
P型第二主体区，形成在N型第二半导体区中；以及
互连区，设置在第一区与第二区之间，互连区包括：
第一绝缘层，形成在N型第一半导体区与N型第二半导体区之间；
金属互连部，形成在第一绝缘层上；和
P型结隔离区，形成并设置在第一绝缘层下面，
其中，N型第二阱区与第一绝缘层接触。
2.如权利要求1所述的高电压半导体装置，其中，P型结隔离区具有与半导体基底相同的导电类型和比半导体基底的掺杂浓度高的掺杂浓度。
3.如权利要求2所述的高电压半导体装置，其中，P型结隔离区具有比半导体基底的浓度大两个数量级或两个数量级以上的浓度。
4.如权利要求1所述的高电压半导体装置，还包括：
N型第一掩埋掺杂层，形成在N型第一半导体区与半导体基底之间；以及
N型第二掩埋掺杂层，形成在N型第二半导体区与半导体基底之间。
5.如权利要求1所述的高电压半导体装置，其中，金属互连部将N型漏极区连接到P型第二主体区。
6.如权利要求1所述的高电压半导体装置，其中，第二区还包括：
P型第一高掺杂区和P型第二高掺杂区，二者形成在P型第二主体区中；
第二绝缘层，形成在P型第一高掺杂区与P型第二高掺杂区之间；
N型第三高掺杂区，形成在N型第二半导体区中；以及
第三绝缘层，形成在P型第二高掺杂区与N型第三高掺杂区之间。
7.如权利要求1所述的高电压半导体装置，其中，N型第二阱区设置在P型结隔离区与P型第二主体区之间。
8.如权利要求6所述的高电压半导体装置，其中，金属互连部将N型漏极区连接到P型第一高掺杂区。
9.如权利要求1所述的高电压半导体装置，其中，第一区还包括邻近于P型第一主体区形成的N型结隔离区。
10.如权利要求9所述的高电压半导体装置，其中，第一深沟槽接触第二深沟槽。
11.如权利要求9所述的高电压半导体装置，其中，第一深沟槽和第二深沟槽使用绝缘膜填充。
12.如权利要求9所述的高电压半导体装置，还包括：P型阱区，环绕第一深沟槽。
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