CN105911126A - 匹配的晶体管对电路 - Google Patents
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Abstract
一种布置在匹配的晶体管对中的传感器阵列，其具有形成在第一晶体管上的输出端和形成在匹配对的第二晶体管上的传感器。匹配对布置成使得通过匹配对中的第一晶体管的输出来读匹配对中的第二晶体管。匹配对中的第一晶体管被迫进入到饱和(有源)区域中以防止第二晶体管对第一晶体管的输出的干扰。获取输出端的样本。然后，第一晶体管置于线性区域中，以允许形成在第二晶体管上的传感器通过第一晶体管的输出端来读。样本从第二晶体管的传感器读数的输出来获得。两个样本的差异被形成。
Description
本案为分案申请。其母案的发明名称为“匹配的晶体管对电路”，申请日为2011年06月30日，申请号为201180056701.1。
相关申请
该申请请求享有2010年9月24日提交的美国临时专利申请序列第61/386,403号的权益，该申请的内容通过引用以其整体并入本文中。
背景技术
当前公开的实施例涉及像素阵列，并且更具体地涉及像素阵列和读出电路内的部件的失配抑制和偏移消除。
电子装置和部件已经在化学和生物(更普遍称为"生命科学")中得到大量应用，尤其是用于探测和测量各种化学和生物反应以及识别，探测和测量各种化合物。一种此类电子装置称为离子敏感场效应晶体管，其在相关文献中常表示为"ISFET"(或pHFET)。ISFET通常主要在学术和研究团体中开发成便于测量溶液的氢离子浓度(通常表示为"pH")。ISFET在这里更普遍地称为化学敏感传感器。
更具体而言，ISFET为阻抗变换装置，其以类似于MOSFET(金属氧化物半导体场效应晶体管)的方式工作，且被具体配置成用有选择地测量溶液中的离子活性(例如，溶液中的氢离子为"分析物")。ISFET的详细工作原理在Sens. Actuators,
88(2003)的1至20页的P. Bergveld所著"Thirty years of ISFETOLOGY: what happened in the
past 30 years and what may happen in the next 30 years"("Bergveld ")一文中给出，该公开物通过引用以其整体并入本文中。
在Rothberg等人的美国专利公开第2010/0301398号、Rothberg等人的美国专利公布第2010/0282617号、和Rothberg等人的美国专利公布2009/0026082中可以找到使用常规CMOS(互补金属氧化物半导体)工艺制造ISFET的细节；这些专利公开共同称为"
Rothberg"，且它们全部都通过引用以其整体并入本文中。然而，除CMOS之外，还可使用双CMOS(即，双极型和CMOS)处理，诸如将包括具有外围上的双极结构的PMOS或NMOS
FET阵列的处理。可替代地，可采用其它技术，其中传感元件可以三端子装置制成，其中感测的离子导致控制该三个端子之一的信号的形成；例如，此类技术还可包括GaAs和碳纳米管技术。
以CMOS为例，P型ISFET制造基于P型或N型硅基底，其中形成晶体管"本体"的n型阱被形成。构成ISFET的源极和漏极的高度掺杂的P型(P+)区域S和D形成在n型阱内。高度掺杂的N型(N+)区域B也可形成在n型阱内，以提供与n型阱的传输本体(或"体")连接。氧化层可设置在源极、漏极和本体连接区域之上，通过本体连接区域制作开口以(通过电导体)提供与这些区域的电连接。多晶硅栅（gate）可被形成在源极与漏极之间的N型阱的区域之上的位置处的氧化层之上。由于其设置在多晶硅栅和晶体管本体(即，N型阱)之间，故氧化层通常称为"栅氧化层"。
另以CMOS为例，N型ISFET制造基于具有通常几微米厚的P外延区域的P+晶圆基底，其中产生晶体管"本体"的P型阱被形成。在阵列中的所有装置间分享P型阱，且P+基底用作体接触，使得在像素阵列处不需要其它接触。构成ISFET的源极和漏极的高度掺杂的N型(N+)区域S和D形成在P型阱内。氧化层可设置在源极、漏极和本体连接区域之上，通过该本体连接区域制作开口来(通过电导体)提供与这些区域的电连接。多晶硅栅可被形成在源极与漏极之间的N型阱的区域之上的位置处的氧化层之上。由于其设置在多晶硅栅和晶体管本体(即，P型阱)之间，故氧化层通常称为"栅氧化层"。
类似于MOSFET，ISFET的工作基于对由MOS(金氧半导体)电容引起的电荷浓度(且因此沟道电导)的调制。该电容由多晶硅栅、栅氧化层和源极与漏极之间的阱(例如，N型阱)的区域构成。当横跨栅和源极区域施加负电压时，通过耗尽该区域的电子而在该区域与栅氧化层之间的界面处形成沟道。对于N型阱，沟道将为P沟道(且反之亦然)。在N型阱的情况下，P沟道将在源极与漏极之间延伸，且当栅源极电势为负足以将空穴从源极吸引到沟道时，电流传导穿过P沟道。沟道开始传导电流所处的栅源极电势称为晶体管的阈值电压VTH(当VGS具有大于阈值电压VTH的绝对值时晶体管进行传导)。源极如此命名是因为其为流过沟道的电荷载流子源(对于P沟道为空穴)；同样，漏极为电荷载流子离开沟道的位置。
如在Rothberg中所述的那样，ISFET可制造成具有浮动栅结构，该浮动栅结构通过将多晶硅栅联接到设置在一个或多个附加氧化层内的多个金属层而形成，该一个或多个附加氧化层设置在栅氧化层之上。浮动栅结构如此命名是因为其与同ISFET相关联的其它导体电隔离；即，其夹在栅氧化层与钝化层之间，该钝化层设置在浮规（floating gage）的金属层(例如，顶部金属层)上。
如在Rothberg中进一步描述的那样，ISFET钝化层构成离子敏感膜，其引起装置的离子灵敏度。与钝化层(特别是在可位于浮动栅结构之上的敏感区域中)接触的诸如分析物溶液(即，含有关注的分析物(包括离子)或测试关注的分析物的存在的溶液)中的离子的分析物的存在改变ISFET的电特性，从而调制流过ISFET的源极与漏极之间的沟道的电流。钝化层可包括多种不同材料中的任一种以便于对特定离子敏感；例如，包括氮化硅或氮氧化硅、以及如氧化硅、氧化铝或氧化钽的金属氧化物的钝化层一般提供对分析物溶液中的氢离子浓度(pH)的灵敏度，而包括含有缬氨霉素的聚氯乙烯的钝化层提供对分析物溶液中的钾离子浓度的灵敏度。适用于钝化层且对其它离子(诸如钠、银、铁、溴、碘、钙和硝酸盐)敏感的材料是已知的，且钝化层可包括各种材料(例如，金属氧化物、金属氮化物、金属氮氧化物)。至于分析物溶液/钝化层界面处的化学反应，对于ISFET的钝化层所采用的给定材料的表面可包括可贡献出质子至分析物溶液或从分析物溶液接收质子的化学基团，在任何给定时间，在与分析物溶液的界面处的钝化层的表面上留下带负电荷的地点、带正电荷的地点和中性地点。
关于离子灵敏度，通常称为"表面电势"的静电电势差作为由于化学反应(例如，通常涉及接近敏感区域的分析物溶液中的离子分解氧化物表面组合)引起的敏感区域中的离子浓度的函数而出现在钝化层与分析物溶液的固体/液体界面处。该表面电势继而又影响ISFET的阈值电压；因此，ISFET的阈值电压随接近敏感区域的分析物溶液中的离子浓度的变化而改变。如Rothberg中所述，由于ISFET的阈值电压VTH对离子浓度敏感，故源电压VS提供信号，该信号与接近ISFET的敏感区域的分析物溶液中的离子浓度直接相关。
化学敏感FET("chemFET")或更具体是ISFET的阵列可用于基于监测分析物在反应期间的存在、生成或使用来监测反应——例如，包括核酸(例如，DNA)测序反应。更具体而言，包括较大chemFET阵列的阵列可用于探测和测量多种化学和/或生物过程(例如，生物或化学反应、细胞或组织培养或监测、神经活动、核酸测序等)中的多种分析物(例如，氢离子、其它离子、非离子分子或化合物等)的静态和/或动态量或浓度，其中可基于此类分析物测量结果来获得有价值的信息。这样的chemFET阵列可在探测分析物的方法中使用和/或在通过chemFET表面处的电荷的变化来监测生物或化学过程的方法中使用。ChemFET(或ISFET)阵列的这样的使用涉及探测溶液中的分析物和/或探测束缚于chemFET表面(例如，ISFET钝化层)的电荷的变化。
以下出版物报道了涉及到ISFET阵列制造的研究：Sensors
and Actuators, B: Chemical，111-112(2005)第347-353页的M. J. Milgrew、M. O. Riehle和D. R. S. Cumming所著的"A large transistor-based sensor array chip for
direct extracellular imaging"和Sensors
and Actuators, B: Chemical，103，(2004)的第37-42页的M. J. Milgrew、P. A. Hammond和D. R.
S. Cumming所著的"The development of scalable sensor
arrays using standard CMOS technology"，这些出版物通过引用并入本文中且在下文中共同称为"Milgrew等人"。Rothberg中包含了制造和使用ChemFET或ISFET阵列来用于化学探测(包括与DNA测序相关的离子的探测)的描述。更具体而言，Rothberg描述了将chemFET阵列(具体是ISFET)用于对核酸进行测序，其涉及在与chemFET接触或电容性地联接到chemFET的反应室中将已知的核苷酸并入到多种相同的核酸中，其中核酸束缚于反应室中的单个小珠，并且Rothberg描述了在chemFET探测信号，其中信号的探测指出由已知的核苷酸三磷酸盐并入到合成核酸中产生的一个或多个氢离子的释放。
存在于许多这些电路和阵列内的一个问题涉及电路制造过程中的公差。由于电路部件及其相对结构中出现于制造公差的固有差异，相同类型的电路可具有与彼此略微不同的特性。旨在为相同电路的电路中的这些差异通常称为失配。
偏移和失配的示例可为放大器失配，其由于旨在为相同的输入差分对的装置之间的阈值失配而出现在电路中。具有旨在为相同的但并不相同的许多放大器的阵列为可呈现出失配的典型电路。有源像素传感器是在其中该失配和偏移可能关键的装置的示例。有源像素传感器是具有一定数目的像素的图像传感阵列，且各个像素与放大器相关联以输出由该像素感测到的光。用以对有源像素传感器内的放大器失配做校正的常用途径是相关双采样。在相关双采样中，一个样本获取自复位像素值而另一个样本获取自具有来自于所感测的光的信号的像素。在两个样本之间获取差异。如果样本为时间相关的，则样本中的差异将代表没有偏移的包括热噪音的减小的实际信号。为了获得两个样本，需要复位值。相关双采样在消除各种类型的偏移和晶体管失配问题中可能是有效的。
然而，存在具有在一定时间段内被不断地读传感元件的传感阵列可以能够不让复位电路被用在那些传感元件内。在没有采样该复位值的情况下，相关双采样就不是可用的技术，因为缺少与传感装置相关的复位值或参考值。因此，本领域中需要提供可不使用相关双采样技术的双采样电路。
此外，CMOS电路中的晶体管失配可对传感器阵列施加严重限制。这可能对于具有小输出电平的传感器尤其真实。在制造过程期间本来就产生的总偏差造成传感器的阵列内的晶体管中的不一致，导致由这些晶体管产生的信号内的不一致和信号偏移。因此，所期望的是消除或减少此类不一致和偏移，尤其是在A/D转换之前。根据以上论述，本领域内仍需要可消除电路(甚至没有复位能力的那些电路)内的偏移和失配的电路。
附图说明
图1为可呈现出晶体管失配的示例性电路。
图2为结合根据本发明的实施例的部件的示例性框图。
图3为根据本发明的实施例的用于采样的匹配的晶体管对的示例。
图4为根据本发明的实施例的使用用于采样的匹配的晶体管对的采样电路的示例。
图5为根据本发明的实施例的用于操作图4中的采样电路的示例性时间图。
图6示出了根据本发明实施例的使用用于采样的匹配的晶体管对的采样电路的另一个示例。
具体实施方式
本文可讨论多个实施例，这些实施例应用不需要复位电路以便正确地起作用的采样技术。在一个实施例中，电路可提供用于克服电路部件的失配和偏移。电路可包括化学敏感传感器、行选择晶体管、采样电路和差分电路。化学敏感传感器可由晶体管形成。行选择晶体管可在化学敏感传感器形成在基底上的位置附近，且行选择晶体管和化学敏感传感器分享共同的性质组。采样电路可配置成从行选择晶体管获取基准样本，且通过行选择晶体管从化学敏感传感器获取信号样本。差分电路可确定基准样本与信号样本之间的差异。尽管信号是在每个样本期间从相同端口被读出，但通过迫使晶体管在饱和区域与三极管区域之间来实现关注的装置的选择。
另一个实施例提供布置在匹配的晶体管对中的传感器阵列，其中选择装置形成在第一晶体管上而传感器形成在匹配的对中的第二晶体管上。匹配对可布置成使得可通过匹配对中的第一晶体管的输出来读匹配对中的传感器晶体管。选择晶体管的源极可用于输出，因为其被偏置到源极跟随器构造中。匹配对中的选择晶体管可被迫进入到饱和(有源)区域中，以防止传感器晶体管对选择晶体管的输出的干扰。当传感器晶体管具有处于比选择晶体管的栅极电压高的电势处的栅极电压时，发生选择晶体管被迫进入到饱和区域中。选择晶体管的漏极的输出电阻由于最小沟道长度调制而高些，这导致可忽略的信号从传感器晶体管通过，因为其执行开关的近似功能。可获取输出电压的样本。然后，选择晶体管可放置到线性(也称为三极管)区域中，从而允许通过选择晶体管的输出来读包括传感器晶体管的化学传感器。当选择晶体管的栅极电压超过传感器晶体管的栅极电压时，发生选择晶体管被迫进入到三极管区域中。可从输出电压获取样本。可获取到两个样本的差异。
另一个实施例提供包括布置成行和列的单晶体管像素的传感器阵列。可按行选择像素且对于所选的行根据一列接一列读出。诸如比较器的装置内的偏移和列电路之间的失配可通过被双采样的各列内的匹配晶体管和用于关联来自于所选行的各列的信号的样本之间的差异消除。另一个实施例提供具有布置成具有列级电路的行和列的像素阵列，其可获取所选像素的多个样本且提供列级复位功能而不会损失之前获取的样本。
图1为呈现出晶体管和放大器的失配的电路的示例。电路100可具有像素110中的偏移和失配，晶体管105,125,127和缓冲器130可组合从而产生信号不一致。 像素110可为不具有复位功能的两个晶体管112和114像素。晶体管112之一可为化学敏感传感器，该传感器探测由以此生成信号的化学反应引起的小信号。模数转换器(ADC)(未示出)可连接到缓冲器130的输出端，以将模拟输出信号转换成数字信号。然而，如果模拟输出信号是不一致的，则为了将模拟输出信号准确地解析成数字信号，ADC将需要在宽动态范围内所分配的附加位——来自于缓冲器130的输出信号越不一致，将需要的位就越多。此外，如果包含在来自于缓冲器130的输出端的信号输出上的所期望的信号的振幅相比于整个输出信号为小，则信号不一致对整个信号的影响就越大，这导致位的低效率分配。因此，偏移和失配强加了较高的位深度要求。在一个实施例中，例如，芯片外（off-chip）的ADC的所需动态范围可为大约250mV。该动态范围可提供大的信号大小和高解析度。举例来说，包含在由于信号的不一致性质而振幅较大的信号上的小信号可具有达到l0uV的量化噪音电平的要求，且对于ADC需要12-14位分辨率，以便准确地进行解析。
图2示出了根据本发明的实施例的结合部件的示例性框图。系统200可包括像素210、偏压晶体管230、偏移消除框240和模数转换器250。像素210可包括匹配的晶体管对：化学敏感传感器211和行选择晶体管215，其中匹配的晶体管意思是晶体管211和215两者大小、形状和类型类似。为了具有作为匹配对的资格，并非装置的所有性质都需要相同。例如，两个晶体管可具有相同的宽度，且共用相同的扩散区域，但具有标称上不同的栅极长度。由于装置以最小距离间隔开，故它们的栅氧化层区域将良好地匹配。这使相比于进一步分开的装置，该装置的阈值将更好地匹配。具有不同的栅极长度的装置将产生输出电平中的测量差异，但所有匹配对将以相同的系统性方式表现且保留一致性。一个差异可为化学敏感传感器211可通过具有联接到提供输入信号的浮动栅的化学敏感阱而与行选择晶体管215不同。只要差异是系统性的且在匹配对之间仍然一致，则可存在其它差异。
大体上，紧密形成在一起的晶体管具有较少失配。在相同像素中使用匹配的晶体管211和215的益处在于，由于行选择晶体管邻近化学敏感传感器，则其将具有较少的晶体管失配。因此，可从与化学敏感传感器相同的像素中的行选择晶体管获取到基准电平来作为传感器晶体管的近似匹配基准。
然而，像素210中的所有部件和偏压晶体管230可具有可有助于输出信号不一致的某种形式的偏移和失配。像素210和偏压晶体管230中的组合的偏移和失配可被采样到偏移消除框240中，且在由ADC
250进行模数转换之前去除。当输入信号范围较小时，例如，ADC 250的动态范围要求可下降至8位电平，因为仅转换了实际信号电平。大体上，晶体管失配被去除或减少，且产生了一致的传感器响应。
将参照图2来阐释解决失配的方法。可以是FET的偏压晶体管230可作用为通过偏压晶体管230的栅极处的偏置电压vb来偏置像素210。ADC 250向来自于像素210的信号提供数字输出。偏移消除240可为列级电路，其提供双采样能力来分析像素210。偏移消除240的偏移功能可消除像素210、偏压晶体管230和信号路径内的任何其它部件内的组合的偏移和失配。偏移消除240可接收没有化学敏感传感器211上的感测信号的整个信号路径的第一样本。第一样本可包括整个信号路径中的所有部件的组合的偏移和失配，例如，像素210的化学敏感传感器211和晶体管215以及偏压晶体管230。信号路径的第二样本可与来自于包括在采样值中的化学敏感传感器211的感测信号值一起获取到。整个信号路径的第二样本可包括整个信号路径中的所有部件(例如，像素210的化学敏感传感器211和晶体管215以及偏压晶体管230)的组合的偏移和失配，以及化学敏感传感器211的感测信号值。偏移消除240可提供差分函数，差分函数从包括来自于化学敏感传感器21的感测信号值的第二样本减去第一样本，这留下感测信号值被提供给ADC
250。总之，偏移消除240可获取两个样本，可在两个样本上使用双采样技术，且可在由ADC
250进行模数转换之前使用两个样本来去除像素210、和偏压晶体管230的偏移和失配。由于仅化学敏感传感器的实际感测的信号电平被转换，故可减小ADC
250的动态范围要求。在特定的实施例中，由于仅实际信号电平被转换，故位长度将降至8位电平。结果，消除/减小了电路部件失配，且使传感器响应一致。
图3A和图3B示出了根据本发明的实施例的使用匹配的晶体管对的Δ双采样的示例。在图3A的电路300中，像素310可由电源I(例如，如图2中的晶体管230的晶体管)偏置。像素310可包括化学敏感传感器313和行选择晶体管315，两者都可为FET。为了清楚起见，匹配对包括化学敏感传感器313和行选择晶体管315。这些装置由于它们的紧密邻近以及图2的示例中的性质而被认为是匹配对。像素310可为在布置成行和列的阵列(未示出)内使用的多个像素中的一个。选择晶体管315可由用于选择像素310的行选择信号rs控制。在相关双采样算法中，在两个不同状态下，可获取装置的信号样本。在没有输入信号(已知或未知，或在复位模式中)的第一状态中可获取像素310的样本，所以装置的任何偏移或失配可特征化，且可在通常包括输入的信号的装置的第二状态中获取像素310的另一个样本。两个样本之间的差异被认作是在没有像素310偏移(例如，诸如电压阈值差异的晶体管制造差异)的情况下的输入信号的表示。然而，在本实施例中，可在正被监测的反应发生的同时连续地读出化学敏感传感器313。因此，不存在在没有输入信号或来自于化学敏感传感器313的已知输入信号的情况下获取样本的机会。
在示例中，在其出现时正被监测且被连续地读出的反应可以是氢离子(H+)在DNA测序事件期间被释放，这出现在核苷酸通过聚合酶合并到DNA链中时。当每个核苷酸合并时，释放氢离子(H+)。由于在生成合并信号的时间段期间连续地读取化学敏感传感器313，故化学敏感传感器313不可复位，这消除了使用相关双采样来去除和减轻偏移的可能性。由于实际化学敏感传感器313不可在没有其输入信号的情况下被测量到，故实际化学敏感传感器313被其最邻近的行选择晶体管315替代从而建立该相关。行选择晶体管315由于其局部地与化学敏感传感器313匹配，因此它可提供化学敏感传感器313的偏移和失配特征的最接近近似。由于行选择晶体管315与化学敏感传感器313一起制造且与化学敏感传感器313紧邻，故行选择晶体管315可能与化学敏感传感器313分享共同的失配和偏移。如图3A中所示，可通过电压V1来偏置行选择晶体管315，使得其工作在饱和区域中从而建立局部阈值电压相关(VTH1)。基本上，行选择晶体管315在其被迫进入饱和时隐藏输入信号。电压V1也小于VREF，电压V1可为传感器电极的有效DC偏置电平，因为它出现在传感器晶体管313的栅极处。V1的示例性电压可为大约1.5V，而VREF的示例性电压可为大约2.5V。该局部阈值电压相关(VTH1)可用于执行(Δ)双采样。通过将行选择晶体管315保持在饱和模式，传感器晶体管313处的可忽略信号或噪音可在第一基准样本期间穿过行选择晶体管315。第一信号样本(即，基准样本)S1为行选择晶体管315的特征，其由于它们的彼此邻近而是化学敏感传感器313的准确替代物。第一信号样本S1可等于V1-(VTH1+ΔV)，其中ΔV为在给定偏置电流电平处偏置晶体管的过驱动电压。该值可在像素内保持恒定，但可由于列级偏压电路中的偏置电流失配而在像素之间改变且从列至列较大地改变。第一样本S1可为在输出Sout处的来自于电路300的输出。图3B示出了对第二信号样本S2进行获取。
在图3B中，行选择晶体管315可由电压V2偏置，使得其工作在三极管区域中，以建立晶体管313(VTH2)的局部阈值电压相关。电压V2大于VREF，其可为有效供应电压。VREF可为恒定的偏置电压，其在基准样本与信号样本之间不会变化。该局部阈值电压相关(VTH2)可用于执行(Δ)双采样。通过将行选择晶体管315保持在三极管区域中，来自于化学敏感传感器313的离子信号(H+)可在第二信号样本期间穿过行选择晶体管315。化学敏感传感器313可工作在晶体管饱和区域中。第二信号样本S2可包括来自于化学敏感传感器313的输入信号VSig和VREF。第二信号样本S2可等于VREF + VSig -(VTH2 +ΔV)。第二样本S2也可为输出Sout处的来自于电路300的输出。
差分函数可产生大致等于VSig +
(VREF – V1) + ( VTHl – VTH2)的S2-S1的结果，注意恒定电压ΔV消除。电压(VREF – V1)可为设置成ADC基准电压的恒定电压，在此情况下，ADC可有效地去除(VREF
– V1)项。阈值电压VTH1和VTH2可大致相等，或差可为匹配对构造引起的系统常数。因此，产生自(VTHl - VTH2)的残余可为最小的，且横跨像素阵列一致。在该不同项中的任何恒定残余可被吸收在ADC基准中。更具体而言，当晶体管具有相同大小时，该不同项为零。当晶体管不具有相同大小或以任何其它方式不相似时，产生的残余可简单地与建立ADC基准的其它常数项加在一起。这使没有任何像素偏移伪像的信号电压VSig施加于ADC。取决于样本在信号路径中被收集的位置，附加信号偏移伪像可被收集在第一样本中，且在Δ双采样操作的差分函数期间减弱。这允许整个信号链在ADC之前的双采样。另外，ADC的部分还可变为偏移消除方案的一部分。例如，如果ADC具有遭受到偏移的输入级，则这些偏移可作为两个样本的一部分被消除，而不需要两个单独的数据转换。当然，采样的顺序可不同。此外，电压V1和V2可为可编程的，且可在读出和共阴共栅电平期间在相应像素的行选择之间接通。在备选实施例中，双采样算法可在ADC之后应用，由此ADC执行两个数据转换循环，且样本之间的不同在数字逻辑中执行。数字逻辑可实现为芯片内的硬件，或由芯片外的软件或硬件实现。这可认作是数字Δ双采样。这具有优点，其中多个ADC同时转换像素读出的列且其中ADC具有固有偏移。此外，可通过在ADC之前和在ADC之后应用差分函数来执行双Δ双采样。第一差分函数可建立用于输入到ADC中的较大程度一致的信号，从而减小所需的ADC的动态范围。第二差分函数可置于ADC之后以消除ADC中的偏移。第一差分函数和第二差分函数产生所有电路部件的完全偏移消除。利用此途径，归因于在下面的电路的传递函数中的非理想性的二阶效应可减小，因为一致性被保持在信号链中的所有点处。
上述配对的Δ双采样(MPDDS)通过对完整的信号路径第一次在没有输入信号的情况下采样且然后第二次在具有输入信号的情况下采样来工作。通过在A/D转换之前减去两个样本，仅样本之间的差(Δ)被转换。样本中的该差代表没有不一致的实际信号。由于信号电平相比于MPDDS过程中去除的偏移较小，故实现了ADC的分辨率(位深度)中的显著节省。此外，减少了清除样本之间的任何不一致的后续处理。举例来说，典型信号链中的偏移可大到200mV，而信号范围在1mV范围内。在没有偏移消除的情况下，即使信号范围为1mV，也需要建立至少200mV的动态范围。在偏移消除的情况下，假定不一致减小到信号电平的范围内，动态范围可减小到2mV。在该示例中，这代表ADC的动态范围中100倍的减小(大约7位的减小)。
图4示出了根据本发明的实施例的系统。系统400可包括四个电路块：像素410、列采样电路420、比较器406和列锁存器430。偏压晶体管405可基于偏置信号vb来对像素410偏置。晶体管408可基于控制输入sw来提供预充电信号。该晶体管408可以是取决于列是否被预充电至供应电压、基底电压的类型或是取决于列是否被预充电到供应电压与基底电压之间的某其它基准电压的类型。像素410可为两个晶体管设计，其具有连接到化学敏感传感器412的源极的行选择晶体管414。化学敏感传感器412的漏极可耦合到供应电压Vdda上。实际上，这可为列线，其切换至Vdda供应电压。行选择晶体管414的源极可从像素410输出并耦合到列采样电路420和偏压晶体管405。列样本420可提供用于读出像素410的读出电路。列样本420可包括包括晶体管421,423和427(其形成电流源)和晶体管425和420(其形成使能电流源的开关)的双共阴共栅的电流源，采样电容器C1，复位晶体管422和电流导引晶体管424。输入信号Vbp,Vbpc和Vbpcc提供相应的偏置信号，以偏置由相应的晶体管421,423和427提供的电流。比较器406可向从列采样电路420接收的输入和基准电压Vramp提供比较函数。比较器406可具有反相输入和非反相输入，控制输入和输出，且可为具有低输入基准噪音电平的高增益放大器。比较器406的带宽可由来自于控制电路的内部控制信号或外部控制信号(未示出)控制，以改变比较器的带宽，使得比较器的带宽可取决于根据比较器406所期望的功能从一个相变至另一个。比较器406可连接到列锁存器430上。列锁存器430可为SR锁存器。锁存器430可利用'latch_rst'复位，且以'latch_set'或比较器的输出设置。锁存器电路430的输出反馈至列样本420。
在运行中，比较器406和列锁存器电路430可用于第一样本阶段期间的偏移消除，且然后在第二阶段中用于A/D转换。因此，MPDDS系统400需要的唯一附加电路可为采样电容器和几个晶体管。通过保持比较器406的带宽大于由晶体管421,423和427形成的电流源镜的带宽，采样电容器C1就可制作成小于所需的KTC噪音电平。在采样电容器中实现的KTC噪音的减小是本领域中技术人员已知的。 这里，KTC噪音减小被结合Δ双采样使用以实现具有较小布局占位（footprint）的偏移消除。由于在获取第一样本期间且然后在转换第二样本减去第一样本的ADC循环期间使用了比较器，比较器偏移被较大地去除且因此较大地去除了ADC的偏移。因此，偏移消除电路和ADC较大程度地集成在一起来作为一个单元，同时仍进行独立运行。
图5示出了图4中的MPDDS系统400的运行的定时。MPDDS系统400的定时可归类为如图5中所示的五个运行阶段：预充电阶段、行选择(select_rst)阶段；偏移消除阶段；选择信号阶段和转换阶段。
在预充电阶段期间，像素410列线可切换至恒定偏置电平，如模拟接地。Col_latch 430可通过切换'latch_rst'成低的来复位。同时，晶体管422处的采样电容器C1端子可切换至接地，且在整个随后的行选择阶段保持为低。预充电阶段期间，建立初始偏置状态。在该阶段期间没有行被选择，所以由vpix代表的像素列线被驱动至初始偏置状态。当使用具有负阈值电压的MOS晶体管时，预充电的电平可设置成高于接地的电平，以便有效地关掉未选择的像素。
在行选择阶段期间，'rs'线可切换至中级电压(例如，1.5V)，其使行选择装置414进入饱和且使列线充电。化学敏感传感器412上的基准电压可处于高于该阶段期间的'rs'线的电平(例如，2.5V)。这确保了行选择装置414保持饱和。在行选择阶段期间，列线的值可被驱动至小于阈值电压的行选择装置414的栅极的电压和给定的偏置电流所需的栅极到源极的过驱动电压。由于行选择装置414的栅极保持为处于低于化学敏感传感器412的栅极的电压，故行选择装置414工作在饱和区域，且不会具有开关的性质。由于行选择装置414的漏极的输出电阻很高，故化学敏感传感器412的源极处的信号和噪音不可调制行选择装置414的源极。这可在偏移消除阶段期间阻挡像素的输入处的信号和噪音。因此，代替使像素410复位来获得相关值，可通过迫使行选择装置414进入到饱和中来阻挡来自于数据通路的信号。上文参照图3A和图3B论述了偏置状态和等式的细节。
当进入偏移消除阶段时，线'A'关闭且线'B'开启。这使比较器406处的'vp'端子开始充电。当'vp'端子上升到'vramp'电平以上时，比较器406可起动，这会关掉电流源436且建立第一样本电平。由于比较器406具有与形成电流源的充电电路相比较高的带宽，故电容器C1处的热噪音电压减小至小于sqrt(KT/C)。现在，信号链的偏移储存在采样电容器C1中。接下来，线'A'和'B'两者均被关掉，且锁存器430又复位，同时到比较器406的vramp线增大到其最高电平，这可超过化学敏感传感器412处的偏压和信号电平的有效输出电平。偏移消除时期可包含定时序列，其有效地模仿了负反馈环，负反馈环使电容器C1的电压成为匹配由Vramp输入设置的比较器处的基准电压所需的值。对于到比较器406的Vramp输入处的给定基准，目标在于使采样电容器C1充电至使比较器406起动的值。由于比较器406和到比较器406的数据路径从行选择时期至信号选择时期保持不变，故比较器406在施加相同的差动电压时总是起动。因此，到比较器406上的第一样本有效地"特征化"数据路径，且储存需要用来将比较器和数据路径调整到零所需的值。Vp节点首先在预充电时期建立的电压（诸如接地）处开始。vp电压可初始化成小于vramp基准电压的电压，其包括所有比较器406之间的总失配的大小。当A线释放时，启动B线，且电流源(该由晶体管421,423和427形成的电流源)开始使电容器C1充电。本质上，比较器406的输入(vramp)由vp输入扫过，直到比较器406起动。一旦比较器406起动，则电流源关掉，且起动比较器406所需的值锁到电容器C1中。现在该值被锁到电容器C1中，在vpix线(即，列线)上存在的任何新的输入电平将仅再呈现给比较器406作为新值与初始值之间的差(Δ)。因此，样本之间的减去过程是构造中固有的。在该阶段中的比较器406的带宽可控制为处于一定的第一带宽，以提供快速运行及KTC噪音抑制。
在选择信号阶段期间，'rs'线切换至其最高电势，其将行选择装置414推入三极管区域中。化学敏感传感器412处的信号电平现在存在于附接到采样电容器C1的列线上。化学敏感传感器412电压然后被通过样本电容器C1耦合且在vramp电压下降的同时保持。
在转换阶段(或选择信号阶段)期间，格雷码计数可分配给所有列。当比较器406起动时，'dout'上升且锁存在格雷码计数(未示出)中，这代表像素410的数字值。ramp线(即，Vramp)可设置成总是超过新vpix电压的电压。为了开始A/D转换，vramp线可与格雷码计数器同步地降低电压。当斜坡值(Vramp)使比较器406起动时，相应的格雷码变的被锁存到对应于该列线的局部寄存器中。被锁存的格雷码然后代表偏移消除信号。后面转换阶段中的比较器406的带宽可控制为处于第二带宽，以提供与早期偏移消除阶段相比较慢的运行。由于运行较慢，比较器可提供对由系统生成的热流体噪音的过滤。
已经结合比较器406、锁存器430和列样本420内用以使采样电容器C1充电的电流源描述了偏移消除阶段。可替代地，有可能使用连续时间反馈且将比较器406用作运算放大器。在此情况下，放大器的输出切换至放大器的反向输入端子上。比较器406中的高增益迫使输入端子变成大致相等。以此方式，比较器406的偏移和在电容器C1之前的偏移在放大器在转换阶段期间以开环构造工作时被采样和消除。在此情况下，连续时间负反馈环执行所需的偏移消除。与连续时间实现相比，使用列锁存器构造所描述的方法可使用更小的电容器，因为来自于采样的热噪音可利用带宽的适当分配来减小。比较器可具有与电流源充电电路相比较大的带宽。为了实现该较大的带宽，充电电路的输出电阻可通过使用多个共阴共栅装置来保持高电平。
图6示出了根据本发明的实施例的系统MPDDS的替代实施例。类似于图4中所述的系统400，系统600可包括像素610、行样本电路620、比较器606和列锁存器630。偏压晶体管605可基于偏置信号vb来偏置像素610。像素610可为两个晶体管设计，其具有连接到化学敏感传感器612的源极的行选择晶体管614。化学敏感传感器612的漏极可耦合到供应电压Vdda。行选择晶体管614的源极可从像素610输出，且耦合到列采样电路620和偏压晶体管605。列样本620可提供用于读出像素610的读出电路。行样本620可包括晶体管621,623,624和629(其形成镜像电流源)、采样电容器C1、复位晶体管622和电流导引晶体管624。比较器606可向从列采样电路620和基准电压Vramp接收的输入提供比较函数。比较器606可为具有低输入基准噪音电平的高增益放大器。比较器606可连接到列锁存器630。列锁存器630可为SR锁存器。锁存器630可利用'Latch_rst '复位，且利用'Latch_set '或比较器的输出设置。锁存器电路630的输出可反馈至列样本620。
在运行中，系统600与上文所述的系统400大致相同地运行。系统600还可根据图5中的定时图运行。主要差别为列样本电路620的构造不同于列样本电路420(由晶体管421,423-425,427和429形成)。具体而言，用于使采样电容器C1充电的由晶体管621,623,624和629形成的镜像电流源是不同的。在图4中，在锁存器切断时使电流改变方向，而在图6中电流被简单地关掉。尽管任一构造允许MPDDS系统600或400的正确运行，但图4中的列样本420构造具有的优点在于在消除时期期间供给电路400的电流是恒定的。恒定电流运行可减小对电源(未示出)的干扰而可能另外破坏进行相同运行的其它电路。相比于列样本电路420中的逆变器，列样本电路620的另一个差异可能在于逆变器631的构造。相比于列样本电路420中的逆变器，逆变器631构造可提供附加延迟。
可出现的两个不同的失配为电流失配和阈值失配。在像素的单(1)晶体管实施例中使用上述双采样方法，可按照电流匹配来执行双采样。在单个化学敏感晶体管像素中，像素(称为特征化晶体管)外部的附加晶体管（一个或多个）可用于解决失配；就特征化晶体管另外设计成小于化学敏感晶体管而言，特征像素可制作成大于化学敏感晶体管(排除浮动栅结构)的近似大小以减小失配。获取的附加特征化晶体管（一个或多个）的信号样本(电流或电压)可用于表征单个化学敏感晶体管像素的偏移和失配。在单晶体管像素实施例中，可对附加晶体管采样来提供表征像素的基准样本，且可对该像素采样。具体而言，可对像素电流采样，且该电流切换成穿过像素外部的较大晶体管，且可对穿过大晶体管的该电流采样。可在一个样本中的像素电流与另一个样本中的特征化晶体管电流之间获取Δ双样本。注意，阈值失配可为最小的。
在没有增加临时噪音的成本的情况下去除了失配和偏移。应当注意的是，在减小像素到像素失配的同时，去除了信号路径中的所有其它偏移。其它益处例如可为低频噪音(闪烁噪音)可由于快速双采样而减小。除能够消除信号路径电平处的偏移之外，还可在各个独立像素的像素310电平处消除偏移。具体而言，由于比较器的样本之间的间隔减小了若干数量级，故使用Δ双采样减小了比较器中的1/f噪音。
尽管上文已经参照特定实施例描述了本发明，但本发明不限于以上实施例和附图中所示的特定构造。操作过程也不限于示例中所示的那些。本领域的技术人员将认识到本发明可以以其它方式实现而不会脱离本发明的精神和大量特征。因此，本实施例在所有方面都被认为是示范性而非限制性的。本发明的范围可由所附权利要求而非以上描述指出，且因此出现在权利要求的等同的意义和范围内的所有变化都旨在包括于其中。
本文已经具体示出和描述了本发明的若干实施例。本领域的技术人员可从以上描述中认识到本发明可以以多种形式实现，且认识到各种实施例可单独实现或以组合方式实现。在其它情况下，众所周知的运行、部件和电路并未被详细描述，以免使实施例模糊。可认识到的是，本文公开的特定结构和功能的细节可为代表性的，且不必限制实施例的范围。因此，尽管已经结合其特定示例描述了本发明的实施例，但本发明的实施例和/或方法的真实范围不应当如此受限，因为在研究附图、说明书和以下权利要求时，其它改型将对于熟练的实施人员变得明显。
可使用硬件元件、软件元件或两者的组合来实现各种实施例。硬件元件的示例可包括处理器、微处理器、电路、电路元件(例如，晶体管、电阻器、电容器、电感器等)、集成电路、专用集成电路(ASIC)、可编程逻辑装置(PLD)、数字信号处理器(DSP)、字段可编程门阵列(FPGA)、逻辑门、寄存器、半导体装置、芯片、微芯片、芯片组等。软件的示例可包括软件部件、程序、应用、计算机程序、应用程序、系统程序、机器程序、操作系统程序、中间件、固件、软件模块、例行程序、子程序、功能、方法、过程、软件接口、应用程序接口(API)、指令集、计算代码、计算机代码、代码段、计算机代码段、字码、值、符号或它们的任何组合。确定实施例是否使用硬件元件和/或软件元件实现可根据任意数目的因素变化，如所期望的计算速率、功率水平、耐热性、处理周期预算、输入数据率、输出数据率、存储器资源、数据总线速度和其它设计或性能约束。
一些实施例例如可使用可储存指令或指令集的计算机可读介质或制品实现，如果由机器执行，则其可使机器执行根据实施例的方法和/或运行。此类机器可包括例如任何适合的处理平台、计算平台、计算装置、处理装置、计算系统、处理系统、计算机、处理器等，且可使用任何适合的硬件和/或软件组合来实现。例如，计算机可读介质或制品可包括任何适合类型的存储器单元、存储器装置、存储器制品、存储器介质、储存装置、储存制品、储存介质和/或储存单元，例如，存储器、可去除或非可去除的介质、可擦除的或非可擦除的介质、可写入的或可重写的介质、数字或模拟介质、硬盘、软盘、压缩光盘只读存储器(CD-ROM)、可记录压缩光盘(CD-R)、可重写压缩光盘(CD-RW)、光盘、磁介质、磁光介质、可去除的存储卡或盘、各种类型的数字通用盘(DVD)、磁带、盒式磁带等。指令可包括使用任何适合的高级、低级、面向对象的、可视的、编译的和/或转译的程序语言实现的任何适合类型的代码，如源代码、编译代码、转译代码、可执行代码、静态代码、动态代码、加密代码等。
Claims (8)
1.一种具有噪音和晶体管失配校正电路的传感器阵列，包括：
布置成行和列的像素阵列，其中所述像素按行选择且经由列读出；
所述像素中的每一个内的化学敏感传感器和选择晶体管布置成使得一旦通过到所述选择晶体管的行选择信号来选择所述像素，则用于所述像素中的每一个的传感器的输出通过所述选择晶体管；
列采样电路，其配置成用以对所述像素进行采样，所述像素为所述列选择，以及列锁存器电路，其配置成生成用以保持来自与每一个列相关联的所述像素的样本的信号，所述列采样电路和所述列锁存器电路中的每一个均配置成置于复位状态和采样或锁存状态中；
读出控制电路，其配置成导致复位电路使所述列采样电路和所述列锁存器电路在第一预定时间段期间复位，在第二预定时间段期间导致所述选择晶体管进入到饱和区域中，在处于饱和区域中时获取所述选择晶体管的第一样本，在第三时间段期间导致所述选择晶体管进入到线性区域中，在所述第三时间段期间，所述选择晶体管选择为通过所述选择晶体管读所述化学敏感传感器的第二样本；以及差分电路，其形成所述第一样本与所述第二样本之间的差异。
2.根据权利要求1所述的传感器阵列，其特征在于，所述化学敏感传感器形成在基底上的所述选择晶体管附近，以及所述选择晶体管和所述化学敏感传感器为相同大小和类型的晶体管。
3.一种用于减轻电路部件的偏移和失配的方法，包括：
将像素输出预充电至第一偏置电平，其中所述像素包括为匹配的晶体管对的化学敏感传感器和选择晶体管；
从所述像素中的选择晶体管采样基准信号样本；
消除来自于基准样本的偏移和失配信号伪像，以在电路节点处留下偏移和失配校正信号；
从所述像素中的化学敏感传感器选择输入信号以应用，其中所述选择的输入信号被采样；
根据所述电路节点处的所述偏移和失配校正信号来调整所述采样的输入信号；以及
将所述调整的采样输入信号从模拟信号转换成数字信号。
4.根据权利要求3所述的方法，其特征在于，从所述选择晶体管采样所述基准信号包括：
在获取所述基准样本时，将栅极电压施加至所述选择晶体管，导致所述选择晶体管工作在所述选择晶体管饱和区域中。
5.根据权利要求3所述的方法，其特征在于，从所述基准样本消除偏移和失配信号伪像以在电路节点处留下偏移和失配校正信号包括：
将所述采样的基准信号储存在采样电容器上；
将所述储存的采样基准信号施加于比较器电路的输入；
使所述比较器电路的端子充电至与基准信号相比较的电压，使得所述比较器输出用以停止比较器端子的充电的信号；以及
将信号值锁定在所述采样电容器处，这导致所述比较器输出用以停止的所述信号。
6.根据权利要求5所述的方法，其特征在于，所述调整所述采样输入信号，包括：
获取所述采样输入信号与所述锁定信号值之间的差异以提供调整输入信号，其中所述调整输入信号不包含来自于所述像素或所述电路的信号路径的偏移和失配伪像。
7.根据权利要求6所述的方法，其特征在于，将所述调整的采样输入信号从模拟信号转换成数字信号，包括：
将所述调整的采样输入信号与表现数字信号电平的基准信号相比较，以及
将信号输出至指出所述比较的结果的锁存器电路，以完成所述模拟信号至数字信号的转换。
8.根据权利要求6所述的方法，其特征在于，所述选择晶体管为大小和类型与所述化学敏感传感器类似的行选择晶体管。
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| CN105911126B (zh) | 2018-12-18 |
| US20120074956A1 (en) | 2012-03-29 |
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| US8912005B1 (en) | 2014-12-16 |
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| JP5913323B2 (ja) | 2016-04-27 |
| EP2619564A1 (en) | 2013-07-31 |
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| TWI584650B (zh) | 2017-05-21 |
| JP2016122019A (ja) | 2016-07-07 |
| US8685324B2 (en) | 2014-04-01 |
| US8796036B2 (en) | 2014-08-05 |
| US20120077256A1 (en) | 2012-03-29 |
| CN103299182A (zh) | 2013-09-11 |
| EP2619564B1 (en) | 2016-03-16 |
| JP2013539297A (ja) | 2013-10-17 |
| TW201233163A (en) | 2012-08-01 |
| EP2619564A4 (en) | 2013-09-04 |
| US9110015B2 (en) | 2015-08-18 |
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