CN103855120A - 多芯片封装及其制造方法 - Google Patents

多芯片封装及其制造方法 Download PDF

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Publication number
CN103855120A
CN103855120A CN201310194087.6A CN201310194087A CN103855120A CN 103855120 A CN103855120 A CN 103855120A CN 201310194087 A CN201310194087 A CN 201310194087A CN 103855120 A CN103855120 A CN 103855120A
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China
Prior art keywords
lead frame
chip
pad
frame pad
mosfet
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Pending
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CN201310194087.6A
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English (en)
Inventor
金炫东
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MagnaChip Semiconductor Ltd
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MagnaChip Semiconductor Ltd
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Priority to CN202010573279.8A priority Critical patent/CN111668107A/zh
Publication of CN103855120A publication Critical patent/CN103855120A/zh
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
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    • H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
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Abstract

本发明提供了一种多芯片封装及其制造方法。多芯片封装包括：多个半导体芯片，该多个半导体芯片中的每一个均安装在相应的引线框垫上；引线框，通过接合线连接到半导体芯片；以及固定框，与引线框垫中的至少一个一体地形成并且被配置成将引线框垫支撑在封装形成衬底上。

Description

多芯片封装及其制造方法
对相关申请的引用
该申请要求2012年12月6日向韩国知识产权局提交的韩国专利申请第10-2012-0141266号在美国专利法典第35卷第119条第(a)款下的权益，其全部公开内容通过引用合并于此以用于所有目的。
技术领域
以下描述涉及一种多芯片封装及其制造方法，并且涉及例如以多个半导体芯片布置在作为表面安装器件的小外形封装（SOP）中或者四侧引脚扁平封装（QFP）中的单封装形式提供的多芯片封装。
背景技术
正积极地研究半导体芯片封装技术，其中努力减小装置的整体尺寸并且增加装置的封装密度。封装技术涉及将诸如IC和切换元件的半导体元件适当地布置在被安装到具有有限尺寸的印刷电路板上的较小封装中，并且其中，这种布置允许较大数量的封装安装在印刷电路板上。
正进行用以开发用于将多个半导体装置安装在一个封装上的多芯片封装的积极研究。“多芯片封装”指的是两个或更多个不同功能的半导体装置布置在引线框垫上作为单个封装的结构。
其上安装有多个芯片的封装的示例是由引线框垫和其上安装的两个至四个芯片构成的封装。芯片连接到引线框和引线框垫的外围周围的接合线。
然而，当通过简单地在引线框垫上布置多个半导体芯片来制作封装时，在封装内的相邻芯片间发生热和/或电干扰。由于引线框垫由金属材料制成，没有用于将芯片彼此隔离或绝缘的分离结构，因此，产生了热和/或电干扰。这样的热和/或电干扰可引起芯片故障，并且可导致以这样的封装制造的产品的缺陷。
可提供用于将芯片彼此绝缘或隔离的结构以使得潜在的热和/或电干扰最小化。然而，这使得制造过程复杂以及增大了封装的尺寸。
另一建议是以封装形式制造每个芯片并且将多个封装安装在PCB上。然而，这些单独的芯片封装也具有其缺点。
由于PCB用于各个单独的封装，因此PCB尺寸增大。此外，如果单独的封装安装在PCB上，则与其上安装有两个至四个芯片的封装相比，对于引线框的需要增加了必须对引线框执行的焊接工作。还需要另外的工作来将其上安装有单独的封装的PCB彼此连接。
因此，单独的封装的安装与旨在通过将尽可能多的器件集成在具有有限尺寸的PCB上来改进性能的封装技术的目的相违背。
如上所述，已提出了各种多芯片封装技术，包括使得多个芯片被设计和布置在一个引线框垫上的封装或者安装单独的封装。然而，所提出的封装技术呈现出其相关联的缺点，并且不满足设计紧凑且轻量的多芯片封装的需求。相关联的缺点是它们本身阻碍了最佳多芯片封装的设计，并且正进行用于解决这些问题的研究。然而，需要更大的改进以设计用于特定封装应用的最佳多芯片封装技术。
发明内容
在一个一般方面，提供了一种多芯片封装，其包括：多个半导体芯片，该多个半导体芯片中的每一个均安装在相应的引线框垫上；引线框，通过接合线连接到半导体芯片；以及固定框，与引线框垫中的至少一个一体地形成并且被配置成将引线框垫支撑在封装形成衬底上。
多芯片封装可实现在小外形封装（SOP）或四侧引脚扁平封装（QFP）上。
固定框可包括在到引线框垫的连接部分上形成的阶梯状部分。
半导体芯片可包括一个控制集成电路（IC）芯片和多个MOSFET芯片。
在另一个一般方面，提供了一种用于小外形封装（SOP）的多芯片封装，该多芯片封装包括：第一引线框垫；第二引线框垫和第三引线框垫，布置在第一引线框垫的两个相对侧；第一至第三半导体芯片，附接到第一至第三引线框垫上；引线框，通过接合线连接到第一至第三半导体芯片；以及固定框，与第一至第三引线框垫一体地形成，以将第一至第三引线框垫支撑在封装形成衬底上。
第一半导体芯片可以是控制IC芯片，并且第二和第三半导体芯片可以是MOSFET芯片。
固定框和连接到MOSFET芯片的漏极的引线框可包括局部弯曲的阶梯状部分。
在另一个一般方面，提供了一种用于四侧引脚扁平封装（QFP）的多芯片封装，该多芯片封装包括：第一引线框垫；第二至第四引线框垫，排列在第一引线框垫的一侧；第一至第四半导体芯片，接合到第一至第四引线框垫；多个引线框，通过接合线连接到第一至第四半导体芯片；以及固定框，与第一至第四引线框垫一体地形成，以支撑第一至第四引线框垫使得第一至第四引线框垫放置在封装形成衬底上。
第一半导体芯片可以是控制集成电路（IC）芯片，并且第二至第四半导体芯片可以是MOSFET芯片。
固定框和连接到MOSFET芯片的漏极的引线框可包括局部弯曲的阶梯状部分。
连接到控制IC芯片的引线框可局部以之字形图案形成。
连接到MOSFET芯片的漏极的引线框中的每一个的宽度均可大于连接到MOSFET芯片的源极的每个引线框和连接到控制IC芯片的每个引线框的宽度。
粘合件（adhesive）可以以相对于引线框的长度方向的正交关系附接到与控制IC芯片相连接的每个引线框的上表面。
粘合件可包括加热带（heat tape）。
在又一个一般方面，提供了一种制造多芯片封装的方法，该方法包括：将第一芯片安装在第一引线框垫上；将第二芯片安装在第二引线框垫上；通过将引线框垫的部分与固定框集成来将第一和第二引线框垫放置在封装形成衬底上；以及关于第一和第二芯片以及第一和第二引线框垫形成模具。
该方法的一般方面还可包括：将第一和第二芯片与引线框用线连接，以使得第一和第二芯片放置在封装形成衬底的中心部分中，引线框从中心部分径向向外延伸，并且芯片的数量与引线框垫的数量相同。
将第一和第二芯片安装在第一和第二引线框垫上可包括利用Ag环氧树脂将第一和第二芯片接合到相应的引线框垫。
第一芯片可以是控制IC芯片，并且第二芯片可以是MOSFET芯片。
连接到MOSFET芯片的漏极的引线框中的每一个的宽度均可大于连接到MOSFET芯片的源极的引线框的宽度，并且固定框可具有阶梯状部分以使得引线框垫被放置得低于固定框。
其它特征和方面可从以下详细描述、附图和权利要求明显可见。
附图说明
图1是小外形封装的示例的平面图。
图2是具有图1所示的小外形封装的特征的实际实现封装的示例的照片。
图3是图2所示的封装的示意侧视图。
图4是四侧引脚扁平封装的示例的平面图。
图5是在对封装进行模制之前得到的实际实现的四侧引脚扁平封装的示例的照片。
在附图和详细描述中，除非另外描述，否则相同的附图标记将被理解为是指相同的元件、特征和结构。为了清楚、图示和方便，这些元件的相对尺寸和图示可被放大。
具体实施方式
提供以下详细描述以帮助读者获得对这里描述的方法、设备和/或系统的全面理解。因此，本领域的普通技术人员将会想到这里描述的系统、设备和/或方法的各种改变、修改和等同方案。另外，为了增加清楚性和简洁性，可省略公知的功能和构造的描述。
在示例中，可通过使用表面安装技术（SMT）将多个芯片添加到印刷电路板（PCB）的表面上所设置的小外形封装（SOP）和四侧引脚扁平封装（QFP）来构造多芯片封装。例如，可布置三个SOP芯片和四个QFP芯片来构造多芯片封装。
这里所使用的“QFP”指的是引线框从四个拐角突出的封装结构。这里所使用的“SOP”指的是引线框从封装的两侧突出的封装结构。SOP具有长度比其它封装（包括QFP）的长度短的引线框，以减小PCB上的占用面积并且还加速信号传输。
一般地，QFP和SOP被设计为使得最多两个芯片安装在封装上。为了保证安装在封装上的产品在最佳状况下工作，需要使用多个封装。因此，PCB上的占用面积增加。因此，需要在一个QFP和SOP上安装多个芯片。
以下描述多芯片封装和用于制造这些多芯片封装的方法的各种示例。例如，控制集成电路（IC）芯片和两个MOSFET芯片可布置在用作表面安装器件的小外形封装（SOP）上。在另一示例中，控制IC芯片和三个MOSFET芯片可布置在四侧引脚扁平封装（QFP）上。控制IC芯片和MOSFET芯片可安装在相对应的引线框垫上，而不安装在单个引线框垫上。与其上安装有芯片的引线框垫连接的引线框和固定框可包括阶梯状部分，以使得引线框垫被放置得低于固定框。在这样的示例中，可减小其上所安装的封装在PCB上的占用面积，并且由于对于每个半导体芯片的单独引线框垫的使用，可使得芯片间的热和/或电干扰的发生最小化。此外，由于阶梯状部分的存在，可阻挡或减小外部水分进入模制封装中。
以下将分别参照第一示例和第二示例更详细地说明SOP和QFP的结构。
以下将参照图1至图3说明第一示例。
图1是根据第一示例的小外形封装的平面图，并且图2是图1的实际设计封装的照片。
参照图1和图2，引线框垫110a、110b形成在封装形成衬底100上。引线框垫110a、110b可被设置成在数量上对应于封装上要安装的芯片。在该示例中，可设置总共三个芯片120a、120b。然而，在其它示例中可设置不同数量的芯片。例如，三个或更多个芯片可安装在封装上。在该示例中，可相应地设置三个引线框垫110a、110b。一个引线框垫110a可放置在封装形成衬底100的中心，侧面是相对于引线框垫110a对称地放置在左侧和右侧的两个其它引线框垫110b。引线框垫110a、110b可以以与芯片相同的形状、以比芯片稍大的尺寸来设置，从而保证芯片稳定地安装在引线框垫110a、110b上。各个引线框垫110a、110b的尺寸可以是一致的或是不同的。如果芯片具有不同的尺寸，则其上安装有芯片的引线框垫的尺寸也会变化。
如上所述，由于根据芯片的数量而单独地采用引线框垫110a、110b，因此与多个芯片安装在单个引线框垫上的示例相比，可以减少或防止芯片间的热和/或电干扰的发生。
控制IC芯片120a和MOSFET芯片120b可安装在每个引线框垫110a、110b上作为切换元件。控制IC芯片120a可在安装在中心处的引线框垫110a上，而MOSFET芯片120b可安装在控制IC芯片120a的左侧和右侧的引线框垫110b上。“MAP3321”芯片可用作控制IC芯片120a。如果在LCD中实现，则芯片可起到控制LED驱动器的背光功能的作用，该LED驱动器控制作为背光源的LED。当然，芯片和芯片的功能可根据产品而变化。控制IC芯片120a和MOSFET芯片120b可通过Ag环氧树脂112而接合，Ag环氧树脂112是施加在引线框垫110a、110b上的导电粘合剂，如图3所示。图3示出了引线框垫110a、110b和控制IC/MOSFET芯片120a、120b通过模制化合物（mold compound）而被模制的示例。
引线框130可被形成为从位于封装的中心的控制IC芯片120a和MOSFET芯片120b径向延伸。当封装安装在PCB（未示出）上时，引线框130用于将控制IC/MOSFET芯片120a、120b连接到PCB上的电路。引线框130可由诸如铜（Cu）的导电材料制成。
引线框垫110a、110b需要被固定在封装形成衬底100的下表面的上部上。为此，可使用固定框140、150。固定框140、150可与引线框垫110a、110b集成，或者基本上从引线框垫110a、110b延伸。除了固定框140、150之外，引线框130的一部分可用于支撑引线框垫110a、110b。参照其上安装有MOSFET芯片120b的引线框垫110b，连接到漏极以释放由驱动MOSFET芯片120b引起的热的引线框垫110b的特定部分可以是一个。引线框也可被视为从引线框垫110b延伸。引线框可以是例如如图2所示的引脚号15和26。
同时，局部弯曲的阶梯状部分160可形成在引线框（即，引脚号15、26）和固定框140、150上。阶梯状部分160起到将引线框垫110a、110b放置在低于引线框130的位置的作用。这么做是为了阻挡来自封装外部的水分的进入。在图3中示出了作为图1的侧视图的结构。图3示出了由于阶梯状部分160的存在而位于低于引线框130的位置的引线框垫110a、110b。
控制IC/MOSFET芯片120a、120b可通过接合线170连接到引线框130。接合线170可以是涂覆有铅（Pb）的常用铜（Cu）线。
参照第一示例，一个控制IC芯片120a和在控制IC芯片120a的左侧和右侧的两个MOSFET芯片120b布置在SOP上。这样的封装设计将需要满足使用该封装的产品的制造者的要求。
同时，分配给根据第一示例制作的SOP的引脚号的功能以表格表示如下。注意，引脚号的该布置仅被提供作为示例，并且引脚号的不同布置在本领域技术人员的预期内。
[表1]
Figure BDA00003235740300071
以下将参照图4和图5说明第二示例。
图4是根据第二示例的QFP的平面图。
参照图4，用于控制IC芯片的一个引线框垫210a和用于MOSFET芯片的三个引线框垫210b被构造在封装形成衬底200上。用于放置控制IC芯片的引线框垫210a可被放置在右侧，而用于放置三个MOSFET芯片的引线框垫210b可被平行地放置在左侧。在该示例中，引线框垫210a、210b的形状和尺寸可与上述第一示例的芯片的形状和尺寸相同，并且引线框垫210a、210b可以以比芯片稍大的尺寸来设置。
作为切换元件的一个控制IC芯片220a和三个MOSFET芯片220b可安装在每个引线框垫210a、210b上。控制IC芯片220a可安装在右侧的引线框垫210a上，而MOSFET芯片220b可安装在左侧的引线框垫210b上。“MAP3331”芯片可用作控制IC芯片120a。芯片和芯片的功能可根据产品而变化。例如，如果在LED中实现，则IC芯片120a可起到控制LED驱动器的背光功能的作用，该LED驱动器控制作为背光源的LED。控制IC芯片220a和MOSFET芯片220b可通过Ag环氧树脂112而接合到引线框垫210a、210b，Ag环氧树脂112与在图3所示的示例中施加到引线框垫110a、110b上的导电粘合剂相同。
如上所述，由于根据控制IC/MOSFET芯片220a、220b的数量而单独采用引线框垫210a、210b，因此与多个芯片安装在单个引线框垫上的示例相比，可以减少或防止芯片间的热和/或电干扰的发生。
引线框230、240a、240b可被构造为将来自一个控制IC芯片220a和MOSFET芯片220b的信号传送到PCB（未示出）。引线框230可用于控制IC芯片220a，并且引线框240a、240b可用于MOSFET芯片220b。根据所示出的示例，可设置总共34个引线框230、240a、240b以提供以下（表2）将说明的功能。引线框230、240a、240b可由诸如铜（Cu）的导电材料制成。
引线框垫210a、210b可被固定到封装形成衬底200的下表面的上部。为此，其上安装有控制IC芯片220a的引线框垫210a可与固定框250一体地形成。其上安装有MOSFET芯片220b的引线框垫210b可由从引线框垫210b延伸的固定框260和连接到漏极的引线框240b支撑。当驱动MOSFET芯片220b时，引线框240b可释放所产生的热并且还支撑引线框垫210b。另外，与其它引线框230、240a相比，引线框240b可具有相对宽的宽度。这是为了有利于将在MOSFET芯片220b的漏极处产生的热释放到外部。热释放效率基本上随着引线框的宽度增大而增加。
引线框240b和固定框250、260可包括局部弯曲的阶梯状部分270。在图4中，一些阶梯状部分由附图标记来引用。阶梯状部分270的存在使得具有控制IC/MOSFET芯片220a、220b的引线框垫210a、210b被放置在低于引线框230、240和固定框250、260的位置处。这么做是为了使得对外部水分的吸收最小化。由于该结构与图3所示的第一示例的结构相同，因此为了简洁，不再提供进一步的说明。
控制IC/MOSFET芯片220a、220b和引线框230、240a可通过接合线280而相连接。接合线280可以是涂覆有铅（Pb）的常用铜（Cu）线。
连接到控制IC芯片220a的引线框230可被形成为使得引线框230的一部分可被形成为之字形图案，如图4和图5所示。引线框230可被局部以之字形图案形成，以使得由于外部水分的可能吸收而导致的引线框230的潜在分层最小化。
加热带310也可被附接在引线框230上以固定引线框230并且还防止引线框230的弯曲。加热带310可具有预定宽度并且相对于引线框230的长度方向以正交关系形成。当然，可设置不同于加热带310的粘附构件以将引线框230固定在置于引线框230的上表面上的状态。
如上所述，根据第二示例，侧面是三个MOSFET芯片的一个控制IC芯片220a被布置和设计在QFP上。
当设计QFP时，这样的封装设计将需要满足使用这些封装的产品的制造者的要求。这些要求可包括例如使用间隔为至少1.25mm的至少28个引线框230、240a、240b、控制IC芯片220a和引线框230以及间隔为至少1.6mm的MOSFET芯片220b和引线框240a、240b。
为了说明目的，分配给根据第二示例制作的SOP的引脚号的功能以表格表示如下。对于引脚号，参照图5，其包括在对所设计的具有图4所示的特征的四侧引脚扁平封装进行模制之前所得到的照片。
[表2]
Figure BDA00003235740300101
根据上述各种示例，一个控制IC芯片和两个MOSFET芯片可布置在作为表面安装器件的SOP上，或者一个控制IC芯片和三个MOSFET芯片可布置在QFP上，从而可使得PCB上的占用面积最小化。此外，由于各个芯片安装在分别对应的引线框垫上，因此可防止或减少芯片间的任何热和/或电干扰的发生。
根据上述一些示例，通过使用相比于用在其它四侧引脚扁平封装或小外形封装中的芯片布置的改进的芯片布置，可获得其上集成有更多个半导体芯片的多芯片封装。
在另一示例中，提供了一种多芯片封装，其可包括：多个引线框垫；半导体芯片，分别安装在引线框垫上；引线框，通过接合线连接到半导体芯片；以及固定框，与各个引线框垫一体地形成，以支撑要放置在封装形成衬底的下表面的上部上的引线框垫。多芯片封装可在小外形封装（SOP）或四侧引脚扁平封装（QFP）上实现，并且固定框可包括形成在与引线框垫的连接部分上的阶梯状部分。半导体芯片可包括控制集成电路（IC）芯片和多个MOSFET芯片。
在另一示例中，提供了一种用于小外形封装（SOP）的多芯片封装，该多芯片封装可包括：第一引线框垫；第二引线框垫和第三引线框垫，对称地布置在第一引线框垫的右侧和左侧；第一至第三半导体芯片，附接到第一至第三引线框垫；引线框，通过接合线连接到第一至第三半导体芯片；以及固定框，与第一至第三引线框垫一体地形成，以支撑要放置在封装形成衬底的下表面的上部上的第一至第三引线框垫。第一半导体芯片可以是控制IC芯片，并且第二和第三半导体芯片可以是MOSFET芯片。固定框和连接到MOSFET芯片的漏极的引线框可包括局部弯曲的阶梯状部分。
在另一示例中，提供了一种用于四侧引脚扁平封装（QFP）的多芯片封装，其可包括：第一引线框垫；第二至第四引线框垫，平行地布置在第一引线框垫的一侧；第一至第四半导体芯片，接合到第一至第四引线框垫；多个引线框，通过接合线连接到第一至第四半导体芯片；以及固定框，与第一至第四引线框一体地形成，以支撑第一至第四引线框垫，使得第一至第四引线框垫放置在封装形成衬底的下表面的上部上。第一半导体芯片可以是控制集成电路（IC）芯片，并且第二至第四半导体芯片可以是MOSFET芯片。固定框和连接到MOSFET芯片的漏极的引线框可包括局部弯曲的阶梯状部分。连接到控制IC芯片的引线框可局部以之字形图案形成。粘合件可以以相对于引线框的长度方向的正交关系而附接到与控制IC芯片连接的每个引线框的上表面，并且该粘合件可包括加热带。
根据这里描述的一些示例，由于为每个封装独立地提供了其上安装有芯片的引线框垫，因此可使得芯片间的热和/或电干扰的发生最小化。
在其它示例中，通过改进多芯片封装（诸如，四侧引脚扁平封装（QFP）和小外形封装（SOP））的芯片布置，可将一个控制IC芯片和三个MOSFET芯片安装在QFP上，或者可将一个控制IC芯片和两个MOSFET芯片安装在SOP上。结果，可减小PCB上的占用面积，并且也可降低制造过程的成本。
在其它示例中，由于连接到MOSFET芯片的漏极的引线框中的每一个的宽度均大于QFP中的其它引线框的宽度，因此可以容易地将从MOSFET芯片产生的热释放到外部。因此，不需要单独的散热器来进行热释放，并且可以提供简化的封装结构。
在其它示例中，由于连接到控制IC芯片的引线框的一部分以之字形图案形成，因此可减小或防止由于来自外部的水分进入而导致的分层的可能性。另外，热粘附带可附接到引线框上以防止其由于引线框的较长长度而导致的弯曲。
尽管上述各种示例提供了在SOP和QFP上总共三个或四个芯片的芯片布置，但是可在各个引线框垫上安装多于三个芯片。引线框垫的数量可对应于芯片的数量。例如，多于3个且少于10个芯片可被安装在SOP或QFP上，并且可将引线框布置为从芯片径向延伸。本公开的特征因此可以以各种不同形式来实施，并且不应被解释为限于这里阐述的示例。相反，提供这些示例以使得本公开将是详尽的且完整的，并且将本公开的完整范围传达给本领域技术人员。附图不一定是按比例绘制的，并且在一些实例中，可能放大了比例以清楚地示出示例的特征。当第一层被称为在第二层“上”或者在衬底“上”时，可以不仅指的是第一层直接形成在第二层或衬底上的情况，而是也可以指的是第三层存在于第一层与第二层或衬底之间的情况。
以上描述了多个示例。然而，应理解，可进行各种修改。例如，如果以不同的顺序执行所描述的技术和/或如果所描述的系统、架构、装置或电路中的部件以不同的方式组合和/或由其它部件或其等同物替换或补充，则可实现适当的结果。因此，其它实现在所附权利要求的范围内。

Claims (19)

1.一种多芯片封装，包括：
多个半导体芯片，所述多个半导体芯片中的每一个均安装在相应的引线框垫上；
引线框，通过接合线连接到所述半导体芯片；以及
固定框，与所述引线框垫中的至少一个一体地形成并且被配置成将所述引线框垫支撑在封装形成衬底上。
2.根据权利要求1所述的多芯片封装，其中，所述多芯片封装在小外形封装SOP或四侧引脚扁平封装QFP上实现。
3.根据权利要求1所述的多芯片封装，其中，所述固定框包括在与所述引线框垫的连接部分上形成的阶梯状部分。
4.根据权利要求1所述的多芯片封装，其中，所述半导体芯片包括一个控制集成电路IC芯片和多个MOSFET芯片。
5.一种用于小外形封装SOP的多芯片封装，所述多芯片封装包括：
第一引线框垫；
第二引线框垫和第三引线框垫，布置在所述第一引线框垫的两个相对侧；
第一至第三半导体芯片，附接到所述第一至第三引线框垫；
引线框，通过接合线连接到所述第一至第三半导体芯片；以及
固定框，与所述第一至第三引线框垫一体地形成，以将所述第一至第三引线框垫支撑在封装形成衬底上。
6.根据权利要求5所述的多芯片封装，其中，所述第一半导体芯片是控制IC芯片，并且所述第二和第三半导体芯片是MOSFET芯片。
7.根据权利要求6所述的多芯片封装，其中，所述固定框和连接到所述MOSFET芯片的漏极的引线框包括局部弯曲的阶梯状部分。
8.一种用于四侧引脚扁平封装QFP的多芯片封装，所述多芯片封装包括：
第一引线框垫；
第二至第四引线框垫，排列在所述第一引线框垫的一侧；
第一至第四半导体芯片，接合到所述第一至第四引线框垫；
多个引线框，通过接合线连接到所述第一至第四半导体芯片；以及
固定框，与所述第一至第四引线框垫一体地形成，以支撑所述第一至第四引线框垫，使得所述第一至第四引线框垫放置在封装形成衬底上。
9.根据权利要求8所述的多芯片封装，其中，所述第一半导体芯片是控制集成电路IC芯片，并且所述第二至第四半导体芯片是MOSFET芯片。
10.根据权利要求9所述的多芯片封装，其中，所述固定框和连接到所述MOSFET芯片的漏极的引线框包括局部弯曲的阶梯状部分。
11.根据权利要求9所述的多芯片封装，其中，连接到所述控制IC芯片的引线框局部以之字形图案形成。
12.根据权利要求9所述的多芯片封装，其中，连接到所述MOSFET芯片的漏极的引线框中的每一个的宽度均大于连接到所述MOSFET芯片的源极的引线框中的每一个和连接到所述控制IC芯片的引线框中的每一个的宽度。
13.根据权利要求9所述的多芯片封装，其中，粘合件以相对于所述引线框的长度方向的正交关系而附接到与所述控制IC芯片连接的每个引线框的上表面。
14.根据权利要求13所述的多芯片封装，其中，所述粘合件包括加热带。
15.一种制造多芯片封装的方法，包括：
将第一芯片安装在第一引线框垫上；
将第二芯片安装在第二引线框垫上；
通过将引线框垫的部分与固定框集成来将所述第一和第二引线框垫放置在封装形成衬底上；以及
关于所述第一和第二芯片以及所述第一和第二引线框垫形成模具。
16.根据权利要求15所述的方法，还包括：将所述第一和第二芯片与引线框用线连接，以使得所述第一和第二芯片放置在所述封装形成衬底的中心部分中，所述引线框从所述中心部分径向向外延伸，并且所述芯片的数量与所述引线框垫的数量相同。
17.根据权利要求15所述的方法，其中，将所述第一和第二芯片安装在所述第一和第二引线框垫上包括利用Ag环氧树脂将所述第一和第二芯片接合到相应的引线框垫。
18.根据权利要求16所述的方法，其中，所述第一芯片是控制IC芯片，并且是所述第二芯片是MOSFET芯片。
19.根据权利要求18所述的方法，其中，连接到所述MOSFET芯片的漏极的引线框中的每一个的宽度均大于连接到所述MOSFET芯片的源极的引线框的宽度，并且所述固定框具有阶梯状部分以使得所述引线框垫被放置得低于所述固定框。
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