CN102569241A - 利用引线框实现电互连的多芯片模块(mcm)功率四方扁平无引线(pqfn)半导体封装 - Google Patents

利用引线框实现电互连的多芯片模块(mcm)功率四方扁平无引线(pqfn)半导体封装 Download PDF

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CN102569241A
CN102569241A CN2011101263797A CN201110126379A CN102569241A CN 102569241 A CN102569241 A CN 102569241A CN 2011101263797 A CN2011101263797 A CN 2011101263797A CN 201110126379 A CN201110126379 A CN 201110126379A CN 102569241 A CN102569241 A CN 102569241A
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vertical conduction
semiconductor packages
conduction power
pqfn
power device
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CN102569241B (zh
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迪安·费尔南多
罗埃尔·巴尔博萨
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Infineon science and technology Americas
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International Rectifier Corp USA
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Abstract

在此公开了一些典型的利用引线框实现电互连的多芯片模块(MCM)功率四方扁平无引线(PQFN)半导体封装的实施方式。一个典型的实施方式包括一种PQFN半导体封装，该半导体封装包括引线框、耦合在引线框上的驱动集成电路(IC)、耦合在引线框上的多个垂直传导功率器件，以及提供电互连的多个线键合，所述的线键合包括从多个垂直传导功率器件中的一个的顶部表面电极到引线框的部分的至少一个线键合，其中引线框的部分被电连接到多个垂直传导功率器件中的另一个的底部表面电极。以此方式，有效的多芯片电路互连能够以使用低成本的引线框的PQFN封装来实现。

Description

利用引线框实现电互连的多芯片模块(MCM)功率四方扁平无引线(PQFN)半导体封装
发明背景 
本申请要求2010年12月13日递交的序列号为61/459,527的题为“Low Cost Leadframe Based High Power Density Full Bridge Power Device”的待定的临时申请的权益和优先权。该待定的临时申请中的公开在此以引用方式全部并入本申请。 
1.发明领域
本发明一般涉及半导体器件。更具体地，本发明涉及半导体器件的多芯片封装。 
2.背景技术
结合几个半导体元件到单个封装的封装(package)能够通过保持相关的和非独立的电路元件极为贴近来帮助简化电路设计，减少成本以及提供更高的效率和提高的性能。这些集成多芯片器件封装帮助促进应用集成和相比较于使用分立元件更高的电和热性能。这个向更高电路集成的趋势导致功率四方扁平无引线(power quad flat no-lead，PQFN)封装的发展和使用，该封装可包括更大的形状因子如12毫米乘12毫米的多芯片模块(multi chip module，MCM)。通过在PQFN封装的底部表面上暴露大的表面面积的芯片垫(die pad)，使要求有效的散热的高功率密度电路应用的性能被优化。 
PQFN封装的一个优点为低成本的制造，因为利用简单的低成本引线框来做基底材料比用昂贵的多层基底材料要好。然而，由于这种单层配置，电的配线和布线成为特别的挑战，特别是对于由12毫米乘12毫米的形状 因子支持的更大和更复杂的多芯片模块。直接互连使用多层衬底材料的功率器件如功率MOSFET和IGBT的封装设计使用简单的单层引线框来实现是不可能的。因为大多数顶部表面的电互连件都必须通过线键合(wirebond)，因此线路布局必须被小心设计以防止线短路。虽然增加封装厚度可减少线短路的风险，但由于封装破裂的风险会提高，为保持封装的可靠性，通常不期望如此。 
因此，需要一种独特的符合成本效益的及可靠的解决方法来支持MCM PQFN封装的高效设计和操作。 
发明内容
一种利用引线框实现电互连的多芯片模块(MCM)功率四方扁平无引线(PQFN)半导体封装，其大致上如结合至少一个附图所示出的和/或描述的，以及如在权利要求中解释的更加完整的。 
附图说明
图1A说明了根据本发明的实施方式的半导体封装的顶面图。 
图1B说明了根据本发明的实施方式的包括线键合的半导体封装的顶面图。 
图1C说明了根据本发明的实施方式的半导体封装的底面图。 
图2说明了根据本发明的实施方式的半导体封装的部分的横截面图。 
发明详述 
本申请针对一种利用引线框实现电互连的多芯片模块(MCM)功率四方扁平无引线(PQFN)半导体封装。以下描述包括关于本发明的实现的具体信息。本领域技术人员将认识到本发明可以不同于在本申请中具体讨论的方式实施。此外，为使发明不难以理解，发明的一些具体细节没有被讨论。在本申请中没有被描述的具体细节是在本领域普通技术人员的知识 范围内的。 
本申请的附图和它们附随的细节描述仅仅针对发明的典型的实施方式。为保持简短，运用本发明原理的发明的其它实施方式没有在本申请中被具体描述并且没有通过本附图被具体说明。 
图1A说明了根据本发明的实施方式的半导体封装的顶面图。在本示例中，半导体封装可包括具有如编号的27条外部引线，或外部引线1、2、3、4、5、6、7、8、9、10、11、12、13、14、15、16、17、18、19、20、21、22、23、24、25、26和27的12毫米乘12毫米的PQFN封装(也就是具有12毫米乘12毫米的“占用面积(footprint)”)。然而，按照应用所要求的，可替代的实施方式可利用不同的封装尺寸以及可包括不同数量的外部引线。 
如图1A中所示，驱动集成电路(IC)或驱动IC 130位于封装的中心。驱动IC 130可包括适于在全桥配置中驱动六个功率器件的高压集成电路(HVIC)驱动器，如可从International Rectifier 
Figure BSA00000497113900031
得到的“第5代”HVIC。因此，驱动IC 130可连接到各个垂直传导功率器件140a、140b、140c、140d、140e和140f的栅电极141a、141b、141c、141d、141e和141f，所述器件可包括例如功率金属氧化物半导体场效应晶体管(功率MOSFET)如快速反向外延二极管场效应晶体管(fast-reverse epitaxial diode field effect transistor，FREDFET)，或绝缘栅双极晶体管(IGBT)。例如，垂直传导功率器件140a到140c可包括形成全桥功率器件的高边FET(high side FET)的MOSFET器件，以及垂直传导功率器件140d到140f可包括形成全桥功率器件的低边FET(high side FET)的MOSFET器件。 
为了清楚的目的，从图1A中删掉了可提供驱动IC 130和垂直传导功率器件140a到140f之间连接的线键合。此外，虽然提供全桥功率器件的封装已在图中示出，但按照具体应用的要求，可替代的实施方式可提供其它封装器件配置。 
引线框160可包括具有高热传导性和电传导性的材料，如可从Olin 
Figure BSA00000497113900032
得到的铜(Cu)合金C194。引线框160的大面积的底部表面可被暴露用于最佳的导电性和散热性，如在结合图1C中进一步示出和讨论的。 引线框160的顶部表面也可被选择性地用材料电镀以增强对器件芯片和电线的粘合。例如，镀层150a、150b、150c、150d、150e、150f和150g可包括选择性地涂覆到引线框160的银(Ag)镀层，该镀层可从如QPL Limited的公司得到。模具合成物165可包括低弯曲模量模具合成物，如可从 
Figure BSA00000497113900041
Chemical得到的CEL9220ZHF10(v79)。 
如图1A中所示，垂直传导功率器件140a到140c全部分享位于封装的顶部边缘附近的同一芯片垫，并且通过镀层150a耦合到引线框160。因此，高边MOSFET的底部漏电极全部一同连接在相同的芯片垫上。另一方面，包括低边MOSFET的垂直传导功率器件140d到140f各自布置在接近封装的右边缘的附近的分别独立的芯片垫上。焊料或导电粘合剂，如可由Henkel Corporation得到的填充银的QMI 529HT，其可用于连结垂直传导功率器件140a到140c的底部表面到镀层150a，垂直传导功率器件140d到镀层150d，垂直传导功率器件140e到镀层150c，垂直传导功率器件140f到镀层150b，以及驱动IC 130到镀层150g。 
因此，驱动IC 130和垂直传导功率器件140a到140f以最优方式布置在封装中以实现电传导性。为完成图1A中的全桥功率电路，源电极142a被要求连接到垂直传导功率器件140d的漏电极，源电极142b被要求连接到垂直传导功率器件140e的漏电极，源电极142c被要求连接到垂直传导功率器件140f的漏电极，且源电极142d、142e、142f被要求连接到一起。然而，为电线直接选择路径以提供必要的连接可导致跨接线和潜在的线短路。此外，因为封装的目标是用于高功率应用，因此长的电线长度要求反而可能影响电的性能和热的性能。 
因此，转到图1B，图1B说明了根据本发明的实施方式的包括线键合的半导体封装的顶面图。如图1B中所示，细电线被利用于栅极连接、电流传感、以及其它输入/输出(I/O)功能，如以线键合170b为代表示出的。这些可包括，例如，直径1.3密耳的G1型金(Au)线。更粗的电线被利用于功率连接，如以线键合170a为代表示出的。这些可包括，例如，直径2.0密耳的铜(Cu)线，如可从Kulicke & 
Figure BSA00000497113900042
得到的 
Figure BSA00000497113900043
LD线。如线键合170a的更粗的电线可使用球上针脚式键合(bond stitch on ball， BSOB)的键合方式键合。如图1B中所示，多个线键合如两个线键合可被平行的布置以提供额外的电流操纵。 
因此，要求的连接由线键合和引线框160提供，如图1B中所示，该连接完成图1A中的电路和到外部引线1到27的布线。栅电极141a到141f被使用金线键合分别直接连接到驱动IC 130。因为垂直传导功率器件140c和140f已经极为贴近，因此使用一对铜线的直接线键合可用于源电极142c和镀层150b之间。 
然而，对于距离更远的器件之间的连接，通过引线框160的布线可为有利的。因为引线框160可包括具有高传导性的材料如铜合金，引线框160可提供相比于直接电线布线更有效的传导路径。此外，如由于跨接线造成的线短路的危险的问题也被避免。 
例如，要连接源电极142b到垂直传导功率器件140e的漏电极，一对粗铜电线被键合在源电极142b的顶部和镀层150e的顶部之间。此连接在以下连同图2的讨论中示出更多细节，该图根据由线102提供的切面示出横截面图。在镀层150e下方的引线框160然后连接到镀层150c以完成到垂直传导功率器件140e的漏电极的连接。以类似的方式，源电极142a经由一对粗铜电线被键合到镀层150f，镀层150f然后经由引线框160连接到镀层150d，镀层150d已被连接在垂直传导功率器件140d的漏电极上。因此，为完成封装的必要电连接通过使用引线框160作为布线装置而实现，其有利地避免了跨线键合。 
移到图1C，图1C说明了根据本发明的实施方式的半导体封装的底面图。通过翻转图1B中所示的封装，可看到外表类似于图1C中所示的布局，并可见引线框暴露的部分。因此，例如，引线框部分160a可对应于图1B中所示的镀层150a的轮廓，以及引线框部分160b可对应于图1B中所示的镀层150e的轮廓。因此，大面积的封装引线框在底部被暴露以有效散热和导电。暴露的表面区域也可被电镀，例如用锡(Sn)电镀。通过相应地设计具有匹配的凸面的印刷电路板(PCB)，PQFN封装的有效设计可被有利地开发。 
现在讨论图2，图2说明了根据本发明的实施方式的半导体封装的部 分的横截面图。更具体地，该横截面图对应于从图1B中沿线102提供的切面。关于图2，引线框部分260a和260b对应于图1C中的引线框部分160a和160b，垂直传导器件240b对应于图1B中的垂直传导器件140b，源电极242b对应于图1B中的源电极142b，镀层250a对应于图1B中的镀层150a，镀层250e对应于图1B中的镀层150e，以及模具合成物265对应于图1B中的模具合成物165。应注意到的是，图2不必按比例绘制。 
如图2中所示，垂直传导器件240b的漏电极243b通过导电粘合剂235和镀层250a耦合到引线框部分260a。如先前讨论的，导电粘合剂235可包括填充银的粘合剂，如QMI 529HT。垂直传导器件240b的源电极242b然后通过线键合270a和镀层250e连接到引线框部分260b。线键合270a可包括以BSOB方式键合的直径2.0密耳的铜(Cu)线。如先前提到的，多个线键合可被提供用以额外的电流操纵，该线键合在图2中没有被示出，因为在图1B中这对线键合是互相平行的。在器件芯片被粘合和线键合成形之后，封装可使用模具合成物265密封。为提供弹性以防止封装破裂，由模具合成物265所界定的封装的高度(或厚度)可保持是薄的，如0.9毫米或更小。 
在图2中所示的横截面由此说明了通过线键合270a提供的电连接，其连接在图1B中示出的源电极142b和镀层150e。与图2中的引线框部分260b对应的图1B中的引线框160的部分继续向右移动以连接到镀层150c，由此完成到垂直传导功率器件140e的漏极的连接。类似的连接过程也应用到连接到垂直传导功率器件140d的漏极的源电极142a。 
因此，已描述了利用引线框实现电互连的多芯片模块(MCM)功率四方扁平无引线(PQFN)半导体封装。根据本发明，即使具有多个功率器件的复杂封装也能够通过利用低成本引线框作为有效的电互连来集成。相比于传统的封装技术，本发明的创新的封装考虑到了紧凑的形状因子、提高的电传导性和热传导性、增强的可靠性以及具有成本效益的制造。 
从发明的以上描述中看出，明显地，很多技术可以用于实现本发明的思想而不偏离其范围。此外，虽然本发明已经具体根据某种实施方式被描述，本领域的普通技术人员将认识到可以在形式和细节上进行改动而不偏 离本发明的精神和范围。同样地，描述的实施方式将作为示例而非限制被全方面的考虑。同样应理解到，本发明不限于此处描述的特殊实施方式，而是能够进行许多调整、修改以及替代而不偏离本发明范围。 

Claims (20)

1.一种功率四方扁平无引线(PQFN)半导体封装，包括：
引线框，其包括多个芯片垫；
驱动集成电路(IC)，其耦合到所述引线框的第一芯片垫；
多个垂直传导功率器件，其包括第一组垂直传导功率器件和第二组垂直传导功率器件，所述第一组垂直传导功率器件耦合到所述引线框的第二芯片垫，所述第二组垂直传导功率器件单独地耦合到所述引线框的相应的芯片垫；
多个线键合，其提供在所述驱动IC、所述多个垂直传导功率器件，以及所述引线框的多个外部引线之间的电互连，其中所述第一组垂直传导功率器件中的一个的顶部表面电极被电连接到所述第二组垂直传导功率器件中的一个的底部表面电极。
2.根据权利要求1所述的PQFN半导体封装，其中所述封装被配置为全桥功率器件。
3.根据权利要求1所述的PQFN半导体封装，其中所述引线框用银选择性地电镀以增强粘合。
4.根据权利要求1所述的PQFN半导体封装，其中所述第一组垂直传导功率器件位于所述封装的第一边缘附近，以及其中所述第二组垂直传导功率器件位于所述封装的第二边缘附近。
5.根据权利要求1所述的PQFN半导体封装，其中所述多个垂直传导功率器件在数量上为六(6)，所述第一组垂直传导功率器件在数量上为三(3)以及所述第二组垂直传导功率器件在数量上为三(3)。
6.根据权利要求1所述的PQFN半导体封装，其中所述多个垂直传导功率器件包括功率MOSFET。
7.根据权利要求1所述的PQFN半导体封装，其中所述多个垂直传导功率器件包括IGBT。
8.根据权利要求1所述的PQFN半导体封装，其中所述封装的厚度为0.9毫米或更小。
9.根据权利要求1所述的PQFN半导体封装，其中所述封装的占用面积为12毫米乘12毫米或更小。
10.根据权利要求1所述的PQFN半导体封装，其中所述多个线键合包括球上针脚式键合(BSOB)方式的铜键合以连接到所述多个垂直传导功率器件的功率电极。
11.一种功率四方扁平无引线(PQFN)半导体封装，包括：
引线框；
驱动集成电路(IC)，其耦合到所述引线框；
多个垂直传导功率器件，其耦合到所述引线框；以及
多个线键合，其提供在所述驱动IC、所述多个垂直传导功率器件，以及所述引线框的多个外部引线之间的电互连，所述多个线键合包括从所述多个垂直传导功率器件中的一个的顶部表面电极到所述引线框的部分的第一线键合，其中所述引线框的所述部分被电连接到所述多个垂直传导功率器件中的另一个的底部表面电极。
12.根据权利要求11所述的PQFN半导体封装，其中所述封装被配置为全桥功率器件。
13.根据权利要求11所述的PQFN半导体封装，其中所述引线框用银选择性地电镀以增强粘合。
14.根据权利要求11所述的PQFN半导体封装，其中所述垂直传导功率器件被分为位于所述封装的第一边缘附近的单个的芯片垫上的第一组和位于所述封装的第二边缘附近的单独的芯片垫上的第二组，所述第一组包括所述多个垂直传导功率器件中的所述的一个，以及所述第二组包括所述多个垂直传导功率器件中的所述的另一个。
15.根据权利要求11所述的PQFN半导体封装，其中所述多个垂直传导功率器件在数量上为六(6)。
16.根据权利要求11所述的PQFN半导体封装，其中所述多个垂直传导功率器件包括功率MOSFET。
17.根据权利要求11所述的PQFN半导体封装，其中所述多个垂直传导功率器件包括IGBT。
18.根据权利要求11所述的PQFN半导体封装，其中所述封装的厚度为0.9毫米或更小。
19.根据权利要求11所述的PQFN半导体封装，其中所述封装的占用面积为12毫米乘12毫米或更小。
20.根据权利要求11所述的PQFN半导体封装，其中所述第一线键合包括球上针脚式键合(BSOB)方式的铜键合。
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US9024420B2 (en) 2015-05-05
US8587101B2 (en) 2013-11-19
US9324638B2 (en) 2016-04-26
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KR20120089542A (ko) 2012-08-13
US20120146205A1 (en) 2012-06-14
JP2014060402A (ja) 2014-04-03
US9530724B2 (en) 2016-12-27
US20150235932A1 (en) 2015-08-20
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US20130105958A1 (en) 2013-05-02

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