TWM258417U - Package structure of chip - Google Patents
Package structure of chip Download PDFInfo
- Publication number
- TWM258417U TWM258417U TW093208265U TW93208265U TWM258417U TW M258417 U TWM258417 U TW M258417U TW 093208265 U TW093208265 U TW 093208265U TW 93208265 U TW93208265 U TW 93208265U TW M258417 U TWM258417 U TW M258417U
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- chip
- lead frame
- lead
- pin
- package
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73215—Layer and wire connectors
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- Lead Frames For Integrated Circuits (AREA)
Description
M258417M258417
四、創作說明(1) 【新型所屬之技術領域】 本創作係有關於一種晶片封裝結構, 格,陣列(Bau Grid Array,BGA)之封裝結構^可= 封裝結構,並縮短訊號傳輸距離者。 曰 【先前技術】 一般半導體晶片需透過封裝製程,藉以保護該曰片 並同時裝設提供電氣連接之接腳。習知的封裝製程曰曰,一 種關於BGA封裝結構,參考第四圖所顯示,其主 半導體晶片(10)以電氣連接一基層板(2〇)後、,以環 醋封裝形成一封裝體(30)所構成,其中,該晶片 數個電氣輸出入之電極(1〇1),透過金線(2〇2)打線至晶 (10)底部所黏著之基層板(20),而對應各訊號之電= 通道。㈣’基層板(2。)中’其各訊號之電氣連接通道接 會在基層板(20)底部形成一球腳(3〇2),可藉以焊接於電 |路板之電路中,形成銜接電路板之信號通路。4. Creation Instructions (1) [Technical Field to which the New Type belongs] This creation is about a chip packaging structure. The packaging structure of a Bau Grid Array (BGA) can be the packaging structure and shorten the signal transmission distance. [Previous technology] Generally, semiconductor chips need to be packaged to protect the chip and also provide pins that provide electrical connections. The conventional packaging process refers to a BGA package structure, as shown in the fourth figure. After the main semiconductor wafer (10) is electrically connected to a base board (20), it is packaged with a vinegar to form a package ( 30), in which several electrical input / output electrodes (101) of the chip are wired through a gold wire (202) to the base board (20) adhered to the bottom of the crystal (10), corresponding to each signal Electricity = channel. ㈣In the base board (2.), the electrical connection channels of its signals will form a ball pin (302) at the bottom of the base board (20), which can be soldered to the circuit of the circuit board to form a connection Signal path of the circuit board.
另外,習知的封裝製程中,亦有利用小外引腳封裝 (thm small outline package,TS〇p)之封裝結構者,其 係利用一導線架連接晶片之訊號源,經過封裝後,再 導線架延伸出.封裝體的部份,焊接至電路板上,因此 晶片固設且電氣連接至電路板中所對應的電路中。V 【新型内容】 《所欲解決之技術問題》 第5頁 M258417 四、創作說明(2) 前述習用之晶片封裝結構 結構者,其利用導線架延伸出 通道者,具有結構簡單之特性 太長,而不利於高頻之資料傳 佔據面積過大之問題。再者, 者,透過球腳形成訊號通道, 導致的問題,然而為了形成晶 面層’其底部必須形成一基層 的製作成本或製程複雜度較高 面積,將會使得其成本或複雜 習用晶片封裝結構的缺失進行 《解決問題之技術手段》 關於本創作係一種晶片封 數個前述相關技術中的限制及 為達到上述目的,本創作 主要係在球腳格狀陣列(β a 1 1 結構中,透過導線架形成球腳 球腳之間的電氣連接介面層, 連接結構之封裝體中形成對應 其球腳之目的者。 ^ 中’其利用習知的TSOP封農 封裝體外,直接形成其電^ 卻因為形成訊號通道路徑 輪’且其腳位之分佈也造^ 利用習知的BGA封裝結構 雖然可改善TSOP封裝結構所 片與球腳之間的電氣連接介 板。相較於導線架,基層板 ’而且若欲縮小球腳的分佈 度增加。因此,本創作基於 創作。 裝結構,以實際解決一個或 缺失。 提供一種晶片封裝結構,其 Grid Array, BGA)晶片封裝 之承載面,用以作為晶片與 並藉由封裝包覆晶片及電氣 承載面的穿孔,而達到設置 《對先前技術之功效》 基於刖述本創作晶片封裝結構,其係可以達到以下的In addition, in the conventional packaging process, there is also a packaging structure that uses a small small outline package (TS0p), which uses a lead frame to connect the signal source of the chip. The frame extends out of the package body and is soldered to the circuit board, so the chip is fixed and electrically connected to the corresponding circuit in the circuit board. V [New content] "Technical problem to be solved" Page 5 M258417 IV. Creation instructions (2) Those who used the conventional chip package structure and structure to extend the channel through the lead frame have a simple structure and are too long. It is not conducive to the problem of the large area occupied by high-frequency data transmission. Furthermore, the problem caused by the formation of the signal channel through the ball foot, however, in order to form the crystal surface layer, a base layer must be formed at the bottom of the manufacturing cost or the complexity of the process area is high, which will make its cost or complex conventional chip packaging The lack of structure is the "technical means to solve the problem." About this creation is a kind of chip that is limited to several of the aforementioned related technologies and in order to achieve the above purpose, this creation is mainly in the ball foot grid array (β a 1 1 structure, The electrical connection interface layer between the ball and the ball is formed through the lead frame, and the object corresponding to the ball and the foot is formed in the package of the connection structure. ^ "It uses the conventional TSOP package to seal the outside of the agricultural package to directly form its electrical connection ^ However, because of the formation of the signal path path wheel and the distribution of its pins, the conventional BGA package structure can be used to improve the electrical connection board between the TSOP package structure and the ball pin. Compared with the lead frame, the base layer Board, and if you want to reduce the distribution of the ball foot increase. Therefore, this creation is based on the creation. The installation structure to actually solve one or the missing. Provide a A kind of chip packaging structure, the bearing surface of Grid Array (BGA) chip package is used as the perforation of the chip and by encapsulating the chip and the electrical bearing surface to achieve the setting of "Effect on the Prior Technology" Create a chip package structure, which can reach the following
第6頁 M258417 、創作說明(3) 作用與效果: •由於本創作之晶 減短訊號傳輸路徑 2 ·藉由本創作之晶 而可降低封裝後之 •本創作之晶片封 上’並透過封裝體 此,省卻習用基層 程者。 4 ·透過本創作之晶 該封裝體表面處, 本創作之目的及功 為明瞭。 片封裝結構,其 ,因而更適用於 片封裝結構,其 晶片佔有電路& 裝結構中,装曰 六曰日 型成球腳接著導 電路板,而簡化 片封裝結構,其 因此,可增進晶 能經配合下列圖 晶片透過BGA結構,可 高頻訊號之傳輸者。 晶片透過BGA結構,因 的面積者。 片係直接承載於導線架 線架之穿孔結構,因 封裝體結構,以及其製 晶片之導線架係裸露在 片之散熱效率。 示作進一步說明後將更 【實施方式】 s丨彳^本^彳作所提供之晶片封裝結構,其主要在球腳格狀ρ 列(Ball Gr 1(i Array, BGA)晶片封裝結構中,藉由封裝定 覆晶片及電氣連接結構之封装體,設置其球腳者。Page 6 M258417, creation description (3) Function and effect: • Shorten the signal transmission path 2 due to the crystal of this creation • The packaged chip can be reduced by the crystal of this creation • The chip of this creation is sealed and passed through the package Therefore, those who are accustomed to grassroots processes are omitted. 4 · Through the crystal of this creation The purpose and function of this creation are clear at the surface of the package. The chip package structure is more suitable for the chip package structure. In the chip occupying circuit & package structure, a six-day Japanese ball-shaped foot is connected to the circuit board to simplify the chip package structure. Therefore, the chip package structure can be improved. It can pass the BGA structure through the chip shown below, which can transmit high-frequency signals. The chip passes the BGA structure, because of the area. The chip is directly carried on the perforated structure of the lead frame. Due to the package structure and the chip-made lead frame, the heat dissipation efficiency of the bare chip is exposed. It will be further described after the description. [Embodiment] The chip package structure provided by the s 丨 彳 ^ 本 ^ 彳 work is mainly in a ball-foot grid ρ row (Ball Gr 1 (i Array, BGA) chip package structure, The package body with the fixed chip and the electrical connection structure is provided with a ball foot.
參考第一圖所顯示為本創作晶片封裴結構之一種較^ 實施例之剖面示意圖,其主要係將一半導體晶片(丨)以電’ 氣連接一導線架(2)後,再以環氧樹醋封裝形成一封装體 (3 )所構成,其各元件之特徵為: 該晶片(1)係具有半導體積體電路,其底面具有數個 電極(11 ),並藉由各個電極(11)以電氣連接該導線架Referring to the first figure, a schematic cross-sectional view of a comparative embodiment of the wafer sealing structure is shown, which is mainly a semiconductor wafer (丨) electrically connected to a lead frame (2), and then epoxy resin. The tree vinegar is packaged to form a package (3). The characteristics of each component are: The wafer (1) has a semiconductor integrated circuit, and the bottom surface has several electrodes (11), and each electrode (11) To electrically connect the leadframe
M258417 四、創作說明(4) (2)。 參考第二圖所顯示,該導線架(2 )係具有數個引腳 (2 1 )以配合該晶片(丨)底部之各個電極(丨丨),各個引腳 (21)係一#號通路(signai channel),並分別透過金屬導 線所構成之金線(2 2 )以電氣連接所對應的電極(丨丨),藉以 使得晶片(1 )中作為信號輸出入之數個電極(i i ),可分別 透過金線(22)而電氣連接至該導線架中所對應的引腳 (2 1 ) ’而提供訊號之傳輸。再者,該導線架(2 )之各個引 腳(21)中,至少具有一承載面(21a),且該承載面(21以係 形成相當之面積。 前述之導 電極(11 ),而 chip, LOC)的 前述之導 裸露於該封裝 參考第一 材料,諸如環 構成,其配合 面貫穿形成數 (21 )中的承載 (31),而焊接 係一錫球而具 電路中,形成 根據前述M258417 Fourth, creation instructions (4) (2). Referring to the second figure, the lead frame (2) has a plurality of pins (2 1) to match the electrodes (丨 丨) at the bottom of the chip (丨), and each pin (21) is a ## channel (Signai channel), and electrically connect the corresponding electrodes (丨 丨) through the gold wires (2 2) made of metal wires respectively, so that the electrodes (ii) in the chip (1) are output as signals. Signal transmission can be provided by being electrically connected to corresponding pins (2 1) 'in the lead frame through gold wires (22), respectively. In addition, each pin (21) of the lead frame (2) has at least one bearing surface (21a), and the bearing surface (21) forms a corresponding area. The aforementioned conductive electrode (11), and chip , LOC) The foregoing guide is exposed in the package reference first material, such as a ring structure, and its mating surface penetrates the load (31) in the formation number (21), and the solder is a solder ball and the circuit is formed according to the foregoing
線架(2)之引腳(21),係配合該金線(22)及 形成以引腳(21)直接跨接在晶片上(lead 〇 形式。 線架(2)中的各個引腳(2 〇一端朝側向延伸 體(3 )之側邊,而可增進散熱。The pins (21) of the wire frame (2) are matched with the gold wire (22) and formed with the pins (21) directly connected to the chip (lead 0 form. Each pin in the wire frame (2) ( 〇 One end faces the side of the lateral extension body (3), which can improve heat dissipation.
及第三圖所顯示,該封裝體(3)係由高分子 氧樹醋等,包覆整個晶片(丨)及導線架(2 )所 導線架(2)之各個引腳(21)信號通路,於底 個穿孔(31),用以對應各導線架(2)引腳 面(2 1 a )’使得數個球腳(3 2 )可穿過該穿孔 至各個對應的承载面(2 1 a ),各個球腳(3 2 ) 有導引電氣之特性,可藉以焊接於電路板之 銜接電路板之信號通路。 之晶片封裝結構中,該晶片(1)透過其導線As shown in the third figure, the package body (3) is made of high molecular oxygen vinegar, etc., and covers the entire chip (丨) and each pin (21) of the lead frame (2) of the lead frame (2) signal path The bottom hole (31) corresponds to the lead surface (2 1 a) 'of each lead frame (2), so that a plurality of ball pins (3 2) can pass through the hole to each corresponding bearing surface (2 1 a) Each ball foot (3 2) has the characteristics of guiding electrical, which can be connected to the signal path of the circuit board by soldering to the circuit board. In a chip packaging structure, the chip (1) passes through its wires
第8頁 M258417 四、創作說明(5) 架(2)之引腳(21)中形成的數個承載面(21a),以及該封裴 體(3 )中對應各個承載面(2 1 a )所形成的數個穿孔(3丨),使 得可將數個球腳(32)植入各個穿孔(31),而接著至對應的 承載面(21a)。因此,達成較短之信號通路距離,並簡化 曰曰片(1)與各個球腳(32)形成的電氣連接結構。 以上所述者僅為用以解釋本創作之較佳實施例,並非 企圖具以對本創作作任何形式上之限 3實口古/相 同之新型精神下所作有關本創作之 疋以,凡有在 應包括在本創作意圖保護之範疇。㈣飾或變更,皆仍Page 8 M258417 IV. Creation instructions (5) Several bearing surfaces (21a) formed in the pins (21) of the frame (2), and the corresponding bearing surfaces (2 1 a) in the seal body (3) The plurality of perforations (3 丨) are formed, so that a plurality of ball feet (32) can be implanted in each of the perforations (31), and then to the corresponding bearing surface (21a). Therefore, a shorter signal path distance is achieved, and the electrical connection structure formed between the chip (1) and each ball foot (32) is simplified. The above are only for explaining the preferred embodiment of this creation, and are not intended to be used in any form to limit the creation of this creation in the spirit of the same / the same new spirit, all those who make It should be included in the scope of protection of this creative intention. Decorate or change, still
第9頁 M258417 圖式簡單說明 【圖式簡單說明】 附圖所顯示係提供作為具體呈現本說明書中所描述各組成 元件之具體化實施例,並解釋本創作之主要目的以增進對 本創作之了解。 第一圖為顯示本創作晶片封裝結構一實施例之剖面示意 圖。 第二圖為顯示本創作晶片封裝結構關於導線架之平面示意 圖。 第三圖為顯示本創作晶片封裝結構關於封裝體之平面示意 圖。 第四圖為顯示習用之晶片封裝結構的剖面示意圖。 【元件符號說明】 晶片(1) 電極(11) 導線架(2) 引腳(21) 承載面(21a) 金線(2 2 ) 封裝體(3) 穿孔(3 1 ) 球腳(3 2 )Page M258417 Brief description of the drawings [Simplified illustration of the drawings] The drawings show specific embodiments for presenting each component described in this specification, and explain the main purpose of the creation to improve the understanding of the creation . The first figure is a schematic cross-sectional view showing an embodiment of a chip packaging structure of the present invention. The second figure is a schematic plan view showing the lead frame of the original chip package structure. The third figure is a schematic plan view showing the package structure of the original chip package. The fourth figure is a schematic cross-sectional view showing a conventional chip package structure. [Element symbol description] Chip (1) Electrode (11) Lead frame (2) Pin (21) Bearing surface (21a) Gold wire (2 2) Package (3) Perforation (3 1) Ball foot (3 2)
第10頁 M258417 圖式簡單說明 晶片(1 〇) 電極(101) 基層板(20) 金線(2 0 2 ) 封裝體(3 0 ) 球腳(3 0 2 ) 11·!Page 10 M258417 Brief description of the diagram Wafer (1 〇) Electrode (101) Base board (20) Gold wire (2 0 2) Package (3 0) Ball foot (3 0 2) 11 ·!
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