CN107293531A - 单分流器倒相电路中的电力方形扁平无引线封装 - Google Patents

单分流器倒相电路中的电力方形扁平无引线封装 Download PDF

Info

Publication number
CN107293531A
CN107293531A CN201710493835.9A CN201710493835A CN107293531A CN 107293531 A CN107293531 A CN 107293531A CN 201710493835 A CN201710493835 A CN 201710493835A CN 107293531 A CN107293531 A CN 107293531A
Authority
CN
China
Prior art keywords
power switch
phase power
phase
driver
pqfn
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN201710493835.9A
Other languages
English (en)
Other versions
CN107293531B (zh
Inventor
迪安·费尔南多
罗埃尔·巴尔博萨
T·塔卡哈施
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Infineon Technologies Americas Corp
Infineon Technologies North America Corp
Original Assignee
Infineon Technologies North America Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US14/102,275 external-priority patent/US9659845B2/en
Application filed by Infineon Technologies North America Corp filed Critical Infineon Technologies North America Corp
Publication of CN107293531A publication Critical patent/CN107293531A/zh
Application granted granted Critical
Publication of CN107293531B publication Critical patent/CN107293531B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49503—Lead-frames or other flat leads characterised by the die pad
    • H01L23/49513—Lead-frames or other flat leads characterised by the die pad having bonding material between chip and die pad
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49517—Additional leads
    • H01L23/4952—Additional leads the additional leads being a bump or a wire
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49541—Geometry of the lead-frame
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49541—Geometry of the lead-frame
    • H01L23/49548—Cross section geometry
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49541—Geometry of the lead-frame
    • H01L23/49562—Geometry of the lead-frame for devices being provided for in H01L29/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49575—Assemblies of semiconductor devices on lead frames
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05554—Shape in top view being square
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/0601—Structure
    • H01L2224/0603—Bonding areas having different sizes, e.g. different heights or widths
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/061—Disposition
    • H01L2224/0618—Disposition being disposed on at least two different sides of the body, e.g. dual array
    • H01L2224/06181—On opposite sides of the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/291—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/29101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/29198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/29199—Material of the matrix
    • H01L2224/2929—Material of the matrix with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/29198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/29298—Fillers
    • H01L2224/29299—Base material
    • H01L2224/293—Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/29338—Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/29339—Silver [Ag] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/4501—Shape
    • H01L2224/45012—Cross-sectional shape
    • H01L2224/45015—Cross-sectional shape being circular
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45147—Copper (Cu) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/48137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/4901—Structure
    • H01L2224/4903—Connectors having different sizes, e.g. different diameters
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4911—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
    • H01L2224/49111—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain the connectors connecting two common bonding areas, e.g. Litz or braid wires
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4911—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
    • H01L2224/49113—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain the connectors connecting different bonding areas on the semiconductor or solid-state body to a common bonding area outside the body, e.g. converging wires
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49171—Fan-out arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49175—Parallel arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49579—Lead-frames or other flat leads characterised by the materials of the lead frames or layers thereon
    • H01L23/49582—Metallic layers on lead frames
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L24/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01005—Boron [B]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01047—Silver [Ag]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/0105—Tin [Sn]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/06—Polymers
    • H01L2924/078—Adhesive characteristics other than chemical
    • H01L2924/0781—Adhesive characteristics other than chemical being an ohmic electrical conductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1305—Bipolar Junction Transistor [BJT]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1305—Bipolar Junction Transistor [BJT]
    • H01L2924/13055—Insulated gate bipolar transistor [IGBT]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • H01L2924/13064—High Electron Mobility Transistor [HEMT, HFET [heterostructure FET], MODFET]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/183—Connection portion, e.g. seal
    • H01L2924/18301—Connection portion, e.g. seal being an anchoring portion, i.e. mechanical interlocking between the encapsulation resin and another package part
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3011—Impedance
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3011—Impedance
    • H01L2924/30111—Impedance matching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/35—Mechanical effects
    • H01L2924/351—Thermal stress
    • H01L2924/3512—Cracking

Landscapes

  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Geometry (AREA)
  • Inverter Devices (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

本发明申请公开了单分流器倒相电路中的电力方形扁平无引线封装。根据示例性实现，电力方形扁平无引线(PQFN)封装包括位于引线框上的驱动器集成电路(IC)。PQFN封装还包括位于引线框上的低压侧U‑相电力开关、低压侧V‑相电力开关和低压侧W‑相电力开关。引线框的逻辑地耦合到驱动器IC的支持逻辑电路。引线框的电力级地耦合到低压侧U‑相电力开关、低压侧V‑相电力开关和低压侧W‑相电力开关的源极。电力级地还可耦合到驱动器IC的选通驱动器。

Description

单分流器倒相电路中的电力方形扁平无引线封装
本申请是申请日为2014年01月27日，申请号为201410039117.0，发明名称为“单分流器倒相电路中的电力方形扁平无引线封装”的申请的分案申请。
本申请要求序列号为61/774,484，申请日期为2013年3月7日，名称为“Power QuadFlat No-Lead(PQFN)Package in a Single Shunt Inverter Circuit”的临时申请的利益和优先权。本申请也是序列号为13/662,244，申请日期为2012年10月26日，并且名称为“Compact Wirebonded Power Quad Flat No-Lead(PQFN)Package”的部分继续申请，其依次要求序列号为13/034,519，申请日期为2011年2月24日，并且名称为“Multi-Chip Module(MCM)Power Quad Flat No-Lead(PQFN)Semiconductor Package Utilizing a Leadframefor Electrical Interconnections”的申请的优先权，其依次要求序列号为61/459,527，申请日期为2010年12月13日，并且名称为“Low Cost Leadframe Based High PowerDensity Full Bridge Power Device”的临时申请的优先权。本申请要求所有以上认定的申请的利益和优先权。而且，所有以上认定的申请的公开和内容据此通过引用完全并入本申请。
技术领域
本发明申请涉及单分流器倒相电路中的电力方形扁平无引线封装。
背景技术
正如这里所使用的，术语“III-V族”指代的是包括至少一种III族元素和至少一种V族元素的化合物半导体。例如，III-V族半导体可采用III-氮化物半导体的形式。“III-氮化物”或“III-N”，指的是包括氮和至少一种III族元素，诸如铝(Al)、镓(Ga)、铟(In)和硼(B)的化合物半导体并且包括但不限于其合金的任何一种，例如，诸如氮化铝镓(AlxGa(1-x)N)，氮化铟镓(InyGa(1-y)N)、氮化铝铟镓(AlxInyGa(1-x-y)N、氮磷砷化镓(GaAsaPbN(1-a-b))、氮磷砷化铝铟镓(AlxInyGa(1-x-y)AsaPbN(1-a-b))。III-氮化物一般也指的是任何极性，包括但不限于Ga-极性、N-极性、半极性或非极性晶体方向。III-氮化物材料也可包括或者纤锌矿、闪锌矿或者混合多型体，并且可包括单晶、单晶体、多晶或无定形结构。于此使用的氮化镓或GaN，指的是III-氮化物化合物半导体，其中III族元素包括一些或大量的镓，但是也可包括除镓以外的其它III族元素。III-V族或GaN晶体管也可指的是复合高电压增强模式晶体管，其通过将III-V族或GaN晶体管串联连接低电压IV族晶体管形成。
而且，于此使用的术语“IV族”指的是包括至少一种IV族元素诸如硅(Si)、锗(Ge)和碳(C)的半导体，并且也可包括化合物半导体，例如，诸如锗化硅(SiGe)和碳化硅(SiC)。IV族也指的是包括超过一层的IV族元素或IV族元素的掺杂物以产生应变的IV族材料的半导体材料，并且也可包括基于IV族的复合衬底，例如，诸如绝缘体上的硅(SOI)，通过注入氧进行分离(SIMOX)工艺的衬底，及蓝宝石上的硅(SOS)。
组合几种半导体器件的封装可简化电路设计，减少成本并且通过使相关的和依赖的电路部件保持靠近，提供更高的效率和改善的性能。而且，与使用部件的独立封装相比，这些封装可促进应用集成和更好的电性能和热性能。
方形扁平无引线(QFN)封装是用于电气部件诸如电力半导体器件的无引线封装。QFN封装可使用引线框和键合线以连接容纳在其中的电气部件。QFN封装经常具有有限的复杂性且电气布线可具有挑战性，特别是对于更复杂的配置。这样，QFN封装经常具有简单的配置且容纳小数量的电气部件。
发明内容
单分流器倒相电路中的电力方形扁平无引线(PQFN)封装，基本上如至少一幅附图中显示的和/或结合至少一幅附图描述的，并且如以下更完整地描述的：
1)一种电力方形扁平无引线PQFN封装，包括：
驱动器集成电路IC，其位于引线框上；
U-相电力开关、V-相电力开关和W-相电力开关，位于所述引线框上；
所述引线框的逻辑地，该逻辑地耦合到所述驱动器IC的支持逻辑电路；
所述引线框的电力级地，该电力级地耦合到所述U-相电力开关、所述V-相电力开关和所述W-相电力开关的源极。
2)根据1)所述的PQFN封装，其中所述电力级地还耦合到所述驱动器IC的选通驱动器。
3)根据1)所述的PQFN封装，包括将所述引线框的所述电力级地连接到所述W-相电力开关的所述源极的至少一条键合线。
4)根据1)所述的PQFN封装，包括将所述W-相电力开关的所述源极连接到所述V-相电力开关的所述源极的至少一条键合线。
5)根据1)所述的PQFN封装，包括将所述V-相电力开关的所述源极连接到所述U-相电力开关的所述源极的至少一条键合线。
6)根据1)所述的PQFN封装，包括将所述PQFN封装的电力级地端子连接到所述W-相电力开关的所述源极的至少一条键合线。
7)根据1)所述的PQFN封装，包括将所述PQFN封装的逻辑地端子连接到所述驱动器IC的所述支持逻辑电路的至少一条键合线。
8)根据1)所述的PQFN封装，包括通过所述引线框将所述U-相电力开关的所述源极连接到所述驱动器IC的选通驱动器的至少一条键合线。
9)根据1)所述的PQFN封装，其中所述U-相电力开关、所述V-相电力开关和所述W-相电力开关位于所述引线框的相应的管芯垫上。
10)根据1)所述的PQFN封装，其中所述U-相电力开关、所述V-相电力开关和所述W-相电力开关通过所述引线框分别耦合到另一个U-相电力开关、另一个V-相电力开关和另一个W-相电力开关。
11)根据1)所述的PQFN封装，其中所述U-相电力开关、所述V-相电力开关和所述W-相电力开关包括快速反相外延二极管场效应晶体管(FREDFET)。
12)根据1)所述的PQFN封装，其中所述U-相电力开关、所述V-相电力开关和所述W-相电力开关包括绝缘栅双极型晶体管(IGBT)。
13)根据1)所述的PQFN封装，其中所述U-相电力开关、所述V-相电力开关和所述W-相电力开关包括III-V族晶体管。
14)根据1)所述的PQFN封装，其中所述PQFN封装具有大于12mm×12mm的覆盖区。
15)根据1)所述的PQFN封装，其中所述PQFN封装具有小于12mm×12mm的覆盖区。
16)一种电力方形扁平无引线PQFN封装，包括：
驱动器集成电路IC，其位于引线框上；
U-相电力开关、V-相电力开关和W-相电力开关，位于所述引线框上；
所述引线框的逻辑地，该逻辑地耦合到所述驱动器IC的支持逻辑电路；
所述引线框的电力级地，该电力级地耦合到所述驱动器IC的选通驱动器。
17)根据16)所述的PQFN封装，其中所述引线框的所述电力级地还耦合到所述U-相电力开关、所述V-相电力开关和所述W-相电力开关的源极。
18)根据16)所述的PQFN封装，其中所述U-相电力开关、所述V-相电力开关和所述W-相电力开关位于所述引线框的相应的管芯垫上。
19)根据16)所述的PQFN封装，其中所述引线框的所述电力级地通过至少一条键合线耦合到所述驱动器IC的所述选通驱动器。
20)根据16)所述的PQFN封装，包括将所述U-相电力开关的所述源极连接到所述引线框从而将所述电力级地耦合到所述选通驱动器的至少一条键合线。
附图说明
图1A示出了电力方形扁平无引线(PQFN)封装的示例性电路的原理图。
图1B示出了示例性单分流器倒相电路中的PQFN封装的原理图。
图2A示出了示例性PQFN封装的引线框的俯视图。
图2B示出了带有键合线的示例性PQFN封装的俯视图。
图2C示出了示例性PQFN封装的仰视图。
图2D示出了示例性PQFN封装的一部分的横截面图。
具体实施方式
以下描述包括与本公开中的实现有关的具体信息。本申请的附图和随同它们的详细描述仅针对示例性实现。除非另外指出，否则附图中相同或相应的元素可被相同或相应的参考数字指示。而且，本申请中的附图和图示一般并不按比例，也不打算对应于实际的相对尺寸。
图1A示出了电力方形扁平无引线(PQFN)封装100的示例性电路的原理图。图1B示出了单分流器倒相电路150中的PQFN封装100的原理图。
参考图1A和1B，PQFN封装100包括驱动器集成电路(IC)102、U-相电力开关104a和104b、V-相电力开关106a和106b以及W-相电力开关108a和108b。驱动器IC102包括输入逻辑162、电平位移器164、低电压保护电路168、比较器170、锁存器172、选通驱动器174a、选通驱动器174b、电容器CR和自举二极管D1、D2和D3。
在图1B的单分流器倒相电路150中，PQFN封装100连接到总线电压源114、电源电压源116、微控制器124、马达126、电阻器R1、电容器C1、自举电容器CB1、CB2、CB3和分流器RS。PQFN封装100、微控制器124、马达126、电阻器R1、电容器C1、自举电容器CB1、CB2、CB3和分流器RS中的任何一个可被安装在印刷电路板(PCB)上。而且，PQFN封装100通过PCB上的导电引线可被连接到总线电压源114、电源电压源116、微控制器124、马达126、电阻器R1、电容器C1、自举电容器CB1、CB2、CB3和分流器RS中的任何一个。
PQFN封装100也包括VBUS端子112a、VCC端子112b、HIN1端子112c、HIN2端子112d、HIN3端子112e、LIN1端子112f、LIN2端子112g、LIN3端子112h、EN端子112i、故障端子112j、RCIN端子112k、IM端子112l、VSS端子112m、VCOM端子112n、SW1端子112o、SW2端子112p、SW3端子112q、VB1端子112r、VB2端子112s和VB3端子112t，其统称为I/O端子112。
在PQFN封装100中，VBUS端子112a从总线电压源114接收VBUS输入。VCC端子112b从电源电压源116接收VCC作为到驱动器IC102的输入。HIN1端子112c、HIN2端子112d和HIN3端子112e分别从微控制器124接收HIN1、HIN2和HIN3作为到驱动器IC102的输入。LIN1端子112f、LIN2端子112g和LIN3端子112h分别从微控制器124接收LIN1、LIN2和LIN3作为到驱动器IC102的输入。EN端子112i从微控制器124接收EN作为到驱动器IC102的输入。故障端子112j接收从驱动器IC102输出的故障信号作为微控制器124的输入。RCIN端子112k从电阻器R1和电容器C1接收RCIN作为到驱动器IC102的输入。IM端子112l从U-相电力开关104b、V-相电力开关106b和W-相电力开关108b接收ITRIP作为到驱动器IC102和微控制器124的输入。VSS端子112m从逻辑地GVSS接收VSS作为到驱动器IC102的输入。VCOM端子112n从电力级地GCOM接收VCOM作为到驱动器IC102、U-相电力开关104b、V-相电力开关106b和W-相电力开关108b的输入。SW1端子112从U-相输出节点110a接收输出到马达126的SW1。驱动器IC102也从U-相输出节点110a接收SW1作为输入。SW2端子112p从V-相输出节点110b接收输出到马达126的SW2。驱动器IC102也从V-相输出节点110b接收SW2作为输入。SW3端子112q从W-相输出节点110c接收输出到马达126的SW3。驱动器IC102也从W-相输出节点110c接收SW3作为输入。VB1端子112r从自举电容器CB1接收VB1作为到驱动器IC102的输入。VB2端子112s从自举电容器CB2接收VB2作为到驱动器IC102的输入。VB3端子112t从自举电容器CB3接收VB3作为到驱动器IC102的输入。
应当理解在各种各样的实现中，I/O端子112的编号、数量和位置与所示出的不同。例如，在各种实现中，不同于驱动器IC102的驱动器IC可被使用，其可具有与驱动器IC102不同的能力和/或I/O要求。这可反映在I/O端子112以及PQFN封装100的其它连接上。作为一个特定的实施例，在一个实现中，驱动器IC102代替地是合并驱动器IC102和微控制器124的功能的功能集成IC。这样，附加I/O端子112可被微控制器124的功能所要求，而某些I/O端子112，诸如故障端子112j可不被要求。
PQFN封装100用于多相电力倒相器并且驱动器IC102可以是用于驱动U-相电力开关104a和104b、V-相电力开关106a和106b及W-相电力开关108a和108b的高电压IC(HVIC)，其是全桥配置。驱动器IC102的实施例包括可从国际整流器公司(“InternationalRectifier Corporation”)购买的“5代”HVIC。在本实现中，U-相电力开关104a和104b、V-相电力开关106a和106b以及W-相电力开关108a和108b是垂直导通电力器件，例如，IV族半导体电力金属氧化物半导体场效应晶体管(电力MOSFET)，诸如快速反相外延二极管场效应晶体管(FREDFET)或IV族半导体绝缘栅双极型晶体管(IGBT)。在其它实现中，III-V族半导体FET，HEMT(高电子迁移率晶体管)，和具体地，GaNFET和/或HEMT可在U-相电力开关104a和104b、V-相电力开关106a和106b以及W-相电力开关108a和108b中用作电力器件。如上所定义的，于此所使用的氮化镓或GaN，指的是III-氮化物化合物半导体，其中III族元素包括一些或大量的镓，但是也可包括除镓之外的其它III族元素。如以前所阐明的，III-V族或GaN晶体管也可指复合高电压增强模式晶体管，其通过将III-V族或GaN晶体管串联连接低电压IV族晶体管形成。虽然PQFN封装100提供全桥电力器件，可选的实现可提供被具体的应用所要求的其它封装配置。
在PQFN封装100中，HIN1、HIN2和HIN3是用于为高压侧晶体管的U-相电力开关104a、V-相电力开关106a和W-相电力开关108a的控制信号。输入逻辑162接收HIN1、HIN2和HIN3，其被分别提供到电平位移器164。在本实现中，电平位移器164是具有可维持例如大约600伏的终端的高电压电平位移器。HIN1、HIN2和HIN3的电平位移的形式被选通驱动器174a接收以将高压侧选通信号H1、H2和H3提供给U-相电力开关104a、V-相电力开关106a和W-相电力开关108a，如图1A所示。选通驱动器174a还分别从U-相输出节点110a、V-相输出节点110b和W-相输出节点110c接收SW1、SW2和SW3。驱动器IC102因此分别从HIN1、HIN2和HIN3产生高压侧选通信号H1、H2和H3。
相似的，LIN1、LIN2和LIN3是用于为低压侧晶体管的U-相电力开关104b、V-相电力开关106b和W-相电力开关108b的控制信号。输入逻辑162接收LIN1、LIN2和LIN3，其被分别提供给电平位移器166。在本实现中，电平位移器166是低压电平位移器，其补偿逻辑地GVSS和电力级地GCOM之间的差。例如，这可以是近似一伏或近似两伏。LIN1、LIN2和LIN3的电平位移的形式被分别提供给选通驱动器174b以将低压侧选通信号L1、L2和L3提供给U-相电力开关104b、V-相电力开关106b和W-相电力开关108b，如图1A所示。驱动器IC102因此分别从LIN1、LIN2和LIN3产生低压侧选通信号L1、L2和L3。
驱动器IC102可因此使用选通驱动器174a和174b驱动U-相电力开关104a和104b、V相电力开关106a和106b和W-相电力开关108a和108b的切换以为马达126供电，马达126产生马达电流IM。在本实现中，选通驱动器174a和174b被阻抗匹配到U-相电力开关104a和104b、V-相电力开关106a和106b和W-相电力开关108a和108b中的相应的电力开关。选通驱动器174a和174b可因此驱动U-相电力开关104a和104b、V-相电力开关106a和106b，以及W-相电力开关108a和108b而无需选通电阻，这允许PQFN封装100更小。
VBUS是来自总线电压源114的总线电压，其耦合到U-相电力开关104a、V-相电力开关106a和W-相电力开关108a的各自的漏极。作为一个实施例，总线电压源114可以是AC到DC整流器。作为一个实施例，AC可以是出线端电压(outlet voltage)，诸如230伏。例如，DC电压可以是用于VBUS的近似300伏到近似400伏。
VCC是来自电源电压源116的用于驱动器IC102的电源电压，例如，其可以是近似15伏。如图1A所示，选通驱动器174b被VCC供电。在一些实现中，电源电压源116从VBUS产生VCC。VB1、VB2和VB3是用于驱动器IC102的自举电压并且分别由自举电容器CB1、CB2和CB3提供。自举电容器CB1、CB2和CB3可例如分别通过自举二极管D1、D2和D3被VCC充电。自举电容器CB1被耦合在VB1端子112r和SW3端子112q之间。自举电容器CB2被耦合在VB2端子112s和SW2端子112p之间。自举电容器CB3被耦合在VB3端子112t和SW1端子112o之间。
在显示的实现中，VCC耦合到低电压保护电路168。当VCC下降到阈值电压，诸如近似9伏以下时，低电压保护电路168探测到低电压条件。VCC将低电压条件通知给输入逻辑162以因此禁止驱动器IC102中的切换。驱动器IC102中的切换也可使用EN被改变。EN可由微控制器124用来启用驱动器IC102的切换。更具体的，驱动器IC102被配置为响应于EN启用H1、H2、H3、L1、L2和L3的切换。
图1A显示了提供到驱动器IC102作为ITRIP的马达电流IM。驱动器IC102使用ITRIP用于过电流保护。例如，图1A显示了将ITRIP与由电容器CR产生的参考电压比较的比较器170。如果ITRIP超过参考电压，比较器170触发锁存器172，其通过提供故障信号到故障端子112j将过电流情况指示给微控制器124。输入逻辑162也接收故障信号以禁止驱动器IC102的切换。驱动器IC102使用RCIN以根据过电流保护自动重置锁存器172。如图1B所示，电阻器R1耦合在VCC端子112b和RCIN端子112k之间以对电容器C1充电。电容器C1耦合在RCIN端子112k和VSS端子112m之间。电阻器R1和电容器C1可被改变以更改过电流保护的自动重置的定时。
VSS是来自逻辑地GVSS的、驱动器IC102的支持逻辑电路的逻辑地。作为一个示例，图1A显示VSS作为电容器CR的逻辑地。VSS也是支持逻辑电路的其它部件的逻辑地，支持逻辑电路包括输入逻辑162、电平位移器164、低电压保护电路168、比较器170、锁存器172和电容器CR，但是可包括不同的部件。VCOM是来自电力级地GCOM的U-相电力开关104a和104b、V-相电力开关106a和106b和W-相电力开关108a和108b的电力级地。图1A显示VCOM连接到封装100内的U-相电力开关104a和104b、V-相电力开关106a和106b以及W-相电力开关108a和108b的源极。VCOM也可被用于驱动器IC102。如图1A所示，VCOM耦合到驱动器IC102的选通驱动器174b。
与提供的电力级地分离的逻辑地用于使用分流器RS的单分流器倒相电路150。分流器RS跨接VSS端子112m和VCOM端子112n耦合。分流器RS也可通过VCOM端子112n耦合到U-相电力开关104b、V-相电力开关106b和W-相电力开关108b中的每个的源极。这样，来自马达126的马达电流IM，如图1A所示，与来自U-相电力开关104b、V-相电力开关106b和W-相电力开关108b的相电流组合。马达电流IM通过IM端子112l被提供到微控制器124。微控制器124使用马达电流IM重构各个相电流(U、V和W)以通过控制HIN1、HIN2、HIN3、LIN1、LIN2和LIN3控制脉宽调制(PWM)。
这样，在本实现中，PQFN封装100有与电力级地分离的逻辑地。在U-相电力开关104a和104b、V-相电力开关106a和106b以及W-相电力开关108a和108b的切换期间，可在分流器RS两端之间产生电压。通过使逻辑地与电力级地分离，支持逻辑电路的VCC可以相对于地而不是分流器RS两端的电压形成。这样，通过使用分离的地，PQFN封装100被保护免于闭锁和噪声故障，否则其可由来自U-相电力开关104a和104b、V-相电力开关106a和106b以及W-相电力开关108a和108b的过大切换电压导致。
典型的QFN封装具有有限的复杂性，其具有简单的配置和小数目的电气部件。对于更复杂的配置，布置连接的线同时避免线交叉和线短路是困难的。而且，较长长度的线将不利地影响电气性能和热性能。然而，根据本公开的各种实现的PQFN封装，可以比典型的QFN封装实质上更复杂，同时避免线交叉和线短路并且达到高的电气性能和热性能。而且，在单分流器倒相电路中，PQFN封装可实现逻辑地与电力级地分离。
转向图2A、2B和2C，图2A示出了图2B和2C的PQFN封装200的引线框的俯视图。图2B示出了PQFN封装200的俯视图。图2C示出了PQFN封装200的仰视图。在本实现中，PQFN封装200是多芯片模块(MCM)PQFN封装，其可具有近似12mm×近似12mm的覆盖区(footprint)。在其它实现中，PQFN封装200可具有大于12mm×12mm的覆盖区。在另一个实现中，PQFN封装200可具有小于12mm×12mm的覆盖区。
PQFN封装200对应于图1A和1B中的PQFN封装100。例如，PQFN封装200包括驱动器IC202、U-相电力开关204a和204b、V-相电力开关206a和206b以及W-相电力开关208a和208b，其分别对应于图1A中的驱动器IC102、U-相电力开关104a和104b、V-相电力开关106a和106b以及W-相电力开关108a和108b。而且，PQFN封装200包括VBUS端子212a、VCC端子212b、HIN1端子212c、HIN2端子212d、HIN3端子212e、LIN1端子212f、LIN2端子212g、LIN3端子212h、EN端子212i、故障端子212j、RCIN端子212k、IM端子212l、VSS端子212m(也被称为“逻辑地端子112m”)、VCOM端子212n(也被称为“电力级地端子112n”)、SW1端子212o(也被称为“U-相输出端子212o”)、SW2端子212p(也被称为“V-相输出端子212p”)、SW3端子212q(也被称为“W-相输出端子212q”)、VB1端子212r、VB2端子212s和VB3端子212t(也被称为“I/O端子212”)，其分别对应于PQFN封装100中的VBUS端子112a、VCC端子112b、HIN1端子112c、HIN2端子112d、HIN3端子112e、LIN1端子112f、LIN2端子112g、LIN3端子112h、EN端子112i、故障端子112j、RCIN端子112k、IM端子112l、VSS端子112m、VCOM端子112n、SW1端子112o、SW2端子112p、SW3端子112q、VB1端子112r、VB2端子112s和VB3端子112t。
图2A显示了包括驱动器IC管芯垫220、W-相管芯垫222a、V-相管芯垫222b、U-相管芯垫222c、公共管芯垫228的引线框260。引线框岛233电连接和机械连接(也就是一体地连接)到驱动器IC管芯垫220。引线框260还包括引线框条230和232和I/O端子212。引线框岛234在引线框260的引线框条230上并且引线框条230电连接和机械连接(也就是一体地连接)到引线框260的V-相管芯垫222b。引线框岛236在引线框260的引线框条232上并且引线框条232电连接和机械连接到(也就是一体地连接)引线框260的U-相管芯垫222c。如图2B所示，引线框条230和232可可选地延伸到PQFN封装200的边242c。这样做，引线框条230和232中的任何一个可提供，例如，用于PQFN封装200的附加I/O端子。例如，引线框条232被显示为在PQFN封装200的边242c提供附加的SW1端子212o。
引线框260可包括具有高的热导率和电导率的材料，诸如可向Olin购买的铜(Cu)合金C194。引线框260的上边240a可被选择性地电镀用于增强与器件管芯和导线的粘接性的材料。镀层可包括被选择性地应用到引线框260的银镀层(Ag)，其可以从诸如QPL有限公司购买。
图2A和2B显示引线框260是蚀刻的引线框，诸如半蚀刻的引线框。引线框260的未被蚀刻(例如，未被半刻蚀)的部分在图2A和2B中用虚线指示。引线框岛233、234和236是这样的未蚀刻部分的实例。例如，图2C显示引线框260的底侧240b(其也对应于PQFN封装200的底侧)。图2C还显示PQFN封装200的模压化合物265，其覆盖引线框260的蚀刻部分。模压化合物265可以是具有低的弯曲模量的塑料，诸如可从chemical购买的CEL9220ZHF10(v79)。为了提供抗封装碎裂的弹性，由模压化合物265所限定的PQFN封装200的高度(或厚度)可保持非常薄，诸如0.9mm或更少。
I/O端子212、引线框岛233、引线框岛234和引线框岛236未被蚀刻并且通过模具化合物265被暴露在引线框260的底侧240b(其也对应于PQFN封装200的底侧)上。因此，I/O端子212、引线框岛233、引线框岛234和引线框岛236被暴露在引线框260的底侧240b上用于高的电导率和/或热耗散。通过为(PCB)提供匹配岛，这个特征可可选地利用。引线框260的暴露区域可被电镀，例如用锡(Sn)。
驱动器IC202、U-相电力开关204a和204b、V-相电力开关206a和206b和W-相电力开关208a和208b使用键合线和引线框260互连。
图2B显示U-相电力开关204a和204b、V-相电力开关206a和206b、W-相电力开关208a和208b以及驱动器IC202被电连接和机械连接到引线框260。这可使用焊接剂或导电粘合剂完成，诸如可从Henkel公司购买的银填充的QMI529HT。
如图2B所示，U-相电力开关204b、V-相电力开关206b和W-相电力开关208b沿着PQFN封装200的边242a位于引线框260上。W-相电力开关208b位于W-相管芯垫222a上。更具体地，W-相电力开关208b的漏极236a位于W-相管芯垫222a上。类似地，V-相电力开关206b位于V-相管芯垫222b上。更具体地，V-相电力开关206b的漏极236b位于V-相管芯垫222b上。而且，U-相电力开关204b位于U-相管芯垫222c上。更具体地，U-相电力开关204b的漏极236c位于U-相管芯垫222c上。因此，U-相电力开关204b、V-相电力开关206b和W-相电力开关208b被各自耦合到引线框260的相应的管芯垫。这样，W-相管芯垫222a可对应于PQFN封装200的W-相输出端子212q，V-相管芯垫222b可对应于PQFN封装200的V-相输出端子212p，并且U-相管芯垫222c可对应于PQFN封装200的U-相输出端子212o，如图2B所示。
如图2B所示，U-相电力开关204a、V-相电力开关206a和W-相电力开关208a沿着PQFN封装200的边242b位于引线框260上，其与边242a相交。U-相电力开关204a、V-相电力开关206a和W-相电力开关208a位于公共管芯垫228。更具体地，U-相电力开关204a的漏极236d、V-相电力开关206a的漏极236e和W-相电力开关208a的漏极236f位于引线框260的公共管芯垫228。这样，公共管芯垫228可对应于PQFN封装200的VBUS端子212a(例如，总线电压输入端子)，如图2B所示。
这个配置的实施例更详细地显示在图2D。图2D示出了PQFN封装200的一部分的横截面图。图2D中的横截面图对应于图2B和2C的横截面2D-2D。图2D显示了V-相电力开关206a的漏极236e通过导电粘合剂254和引线框260的镀层248a连接到公共管芯垫228。导电粘合剂254可包括银填充的粘合剂诸如QMI529HT。PQFN封装200的其它管芯可相似地连接到引线框260。
如图2B所示，驱动器IC202位于引线框260上。更具体地，驱动器IC202位于引线框260的驱动器IC管芯垫220上。驱动器IC管芯垫220大于驱动器IC202并且可因此容纳不同的、更大的驱动器IC，其可具有与驱动器IC202不同的特征。
图2B也显示了键合线，诸如将驱动器IC202电连接和机械连接到VCC端子212b、HIN1端子212c、HIN2端子212d、HIN3端子212e、LIN1端子212f、LIN2端子212g、LIN3端子212h、EN端子212i、故障端子212j、RCIN端子212k、IM端子212l、VSS端子212m、VB1端子212r、VB2端子212s、VB3端子212t并且连接到U-相电力开关204a和204b、V-相电力开关206a和206b及W-相电力开关208a和208b的相应的栅极的键合线244a。
图2B中的键合线244和相似描述的键合线可包括，例如，1.3mil直径G1类型金(Au)线。较粗的线可被用于电力连接，诸如键合线246a、246b、246c、246d、246e和246f(也被称为“键合线246”)。例如，键合线246可以是2.0mil直径铜(Cu)线，诸如可从购买的LD线。键合线246可使用在球上键合引线(bond stitch on ball)(BSOB)焊接的方式被焊接。如图2B所示，多条键合线，诸如两条键合线，可以平行于键合线246以用于附加的电流处理。
U-相电力开关204b、V-相电力开关206b和W-相电力开关208b通过引线框260分别耦合到U-相电力开关204a、V-相电力开关206a和W-相电力开关208a。
在图2B中，键合线246a将U-相电力开关204a的源极238d电连接和机械连接到引线框260。更具体地，源极238d经由键合线246a连接到引线框条232的引线框岛236。这样，图1A中的U-相输出节点110a位于引线框260的引线框条232，在此，引线框条232被连接到引线框260的U-相管芯垫222c。这样，PQFN封装200在布置键合线246a和其它键合线诸如键合线244b时具有显著的灵活性，同时避免由于线交叉导致的线短路并且达到高的电性能和热性能。键合线244b电连接和机械连接到驱动器IC202和在引线框岛236的引线框260的引线条232以将SW1提供到图1A所示的驱动器IC202。图1A的U-相输出节点110a也位于引线框260的引线框岛236上。因为引线框岛236暴露在PQFN封装200的底侧240b上(如图2C所示)，U-相输出节点110a产生的热可有效地从PQFN封装200消散。
相似的，键合线246b将V-相电力开关206a的源极238e电连接和机械连接到引线框260。图2D示出了该连接的一个实施例。源极238e经由键合线246b通过引线框260的镀层248b连接到引线条230的引线框岛234。引线框条230之后通过V-相管芯垫222b连接到V-相电力开关206b的漏极236b。相似的连接可被用于连接源极238d与U-相电力开关204b的漏极236c。键合线246b将V-相电力开关206a的源238e电连接和机械连接到在引线框岛234的引线框条230。这样，图1A的V-相输出节点110b位于引线框260的引线框条230，在此，引线框条230连接到引线框260的V-相管芯垫222b。这样，PQFN封装200在布置键合线246b和其它引线诸如键合线244c时具有显著的灵活性，同时避免由于线交叉导致的短路并达到高的电性能和热性能。键合线244c电连接和机械连接驱动器IC202和在引线框岛234的引线框260的引线框条230以将SW2提供到如图1A所示的驱动器IC202。图1A的V-相输出节点110b也位于引线框260的引线框岛234上。由于引线框岛234暴露在PQFN封装200的底侧240b上(如图2C所示)，在V-相输出节点110b产生的热可从PQFN封装200有效地消散。
应当指出，PQFN封装200可包括引线框岛234和/或236而没有引线框条230和/或232。例如，引线框岛234可通过PCB上的迹线连接到V-相管芯垫222b。还应当指出PQFN封装200可包括引线框条230和/或232而没有引线框岛234和/或236。然而，具有带有引线框岛234和236的引线框条230和232可在布置PQFN封装200中的键合线时提供显著的灵活性，同时达到高的电性能和机械性能。
在图2B中，键合线246c将W-相电力开关208a的源极238电连接和机械连接到引线框260。更具体地，键合线246b将W-相电力开关208a的源极238f电连接和机械连接到引线框260上的W-相管芯垫222a。这样，图1A的W-相输出节点110c连同W-相电力开关208b位于引线框260的W-相管芯垫222a。由于W-相电力开关208b临近W-相电力开关208a，W-相电力开关208a的源极238f可被耦合到W-相电力开关208b的漏极236a，同时容易避免由于线交叉导致的线短路并达到高的电性能和机械性能。这可无需使用引线框条和/或引线框岛而完成。这样，PQFN封装200可被制得明显较小，同时避免U-相输出节点110a、V-相输出节点110b和W-相输出节点110c之间的电弧。例如，附加的引线框条和/或引线框岛将要求大的PQFN封装200以维持在引线框条230和232之间的足够的间距252(例如，至少1mm)从而防止电弧。进一步，这个配置并不显著影响布置PQFN封装200的引线的灵活性。而且，由于W-相管芯垫222a暴露在PQFN封装200的底侧240b(如图2C所示)，在W-相输出节点110c产生的热可有效地从PQFN封装200消散。键合线244d电连接和机械连接驱动器IC202和源极238f以将SW3提供到如图1A所示的驱动器IC202。
PQFN封装200包括引线框260的逻辑地，其耦合到驱动器IC202的支持逻辑电路。引线框260的逻辑地包括逻辑地端子212m。至少键合线244g将引线框260的逻辑地端子212m电连接和机械连接到驱动器IC202并且更具体地，将引线框260的逻辑地端子212m连接到驱动器IC202的支持逻辑。
PQFN封装200还包括引线框260的电力级地，其耦合到U-相电力开关204b、V-相电力开关206b和W-相电力开关208b的源极238c、238b和238a。引线框260的电力级地包括电力级地端子212n、驱动器IC管芯垫220和引线框岛233。在图2B中，至少键合线246d将引线框260的电力级地的电力级地端子212n电连接和机械连接到W-相电力开关208b的源极238a。至少键合线246e将W-相电力开关208b的源极238a电连接和机械连接到V-相电力开关206b的源极238b。而且，至少键合线246f将V-相电力开关206b的源极238b电连接和机械连接到U-相电力开关204b的源极238c。这样，源极238a、238b和238c在PQFN封装200内彼此电连接。
也在本实现中，引线框260的电力级地耦合到驱动器IC202的选通驱动器(例如，图1中的选通驱动器174b)。键合线244e和244f通过引线框260将U-相电力开关204b的源极238c连接到驱动器IC202的选通驱动器。键合线244e将U-相电力开关204b的源极238c电连接和机械连接到引线框260的引线框岛233。键合线244f将引线框260的引线框岛233电连接和机械连接到驱动器IC202。通过引线框260将U-相电力开关204b的源极238c连接到驱动器IC202，提供了连接PQFN封装200的灵活性。然而，应当指出引线框岛233是可选的并且键合线可将U-相电力开关204b的源极238c直接连接到驱动器IC202。进一步，在一些实现中，驱动器IC202可选地具有地256，其位于引线框260的驱动器IC管芯垫220上。地256可以是电力级地和/或逻辑地。在显示的实现中，在地256是电力级地的情况下，键合线244f可被排除。
这样，如上关于图1A、1B和2A到2D描述的，根据各种实现，PQFN封装可以比典型的QFN封装实质上更复杂，同时避免线交叉和线短路并达到高的电性能和机械性能。这样做，PQFN封装可实现复杂的电路，诸如具有与电力级地分离的逻辑地的单分流器倒相电路。
从以上的描述，显然各种技术可被用于实现本申请中描述的概念而不背离这些概念的范围。而且，虽然这些概念具体参考特定的实施例已被描述，本领域的普通技术人员将认识到可在形式和细节上做出改变而不背离这些概念的范围。这样，描述的实现将在各个方面被视为示例性的而不是限制性的。应当理解本申请并不限于如上描述的具体实现，而是许多重新布置、修改和替换是可能的而不背离本公开的范围。

Claims (19)

1.一种电力方形扁平无引线PQFN封装，包括：
引线框；以及
驱动器集成电路IC，其位于所述引线框的驱动器IC管芯垫上，其中所述驱动器IC包括：
第一电平位移器，其配置成输出信号至第一选通驱动器以驱动所述PQFN封装的桥电路的高压侧电力晶体管；以及
第二电平位移器，其配置成输出信号至所述驱动器IC的第二选通驱动器以驱动所述PQFN封装的所述桥电路的低压侧电力晶体管。
2.根据权利要求1所述的PQFN封装，其中所述驱动器IC还包括输入逻辑，其耦合到所述第一电平位移器以控制所述第一电平位移器输出信号至所述第一选通驱动器以驱动所述PQFN封装的所述桥电路的所述高压侧电力晶体管，并且耦合到所述第二电平位移器以控制所述第二电平位移器输出信号至所述第二选通驱动器以驱动所述PQFN封装的所述桥电路的所述低压侧电力晶体管。
3.根据权利要求1所述的PQFN封装，其中所述驱动器IC还包括低电压保护电路，其配置成检测电源电压低电压条件以禁止所述桥电路的切换。
4.根据权利要求1所述的PQFN封装，其中所述驱动器IC还包括过电压保护电路，其配置成输出指示过电压条件的信号以禁止所述桥电路的切换。
5.根据权利要求4所述的PQFN封装，其中所述第一电平位移器被配置成以比所述第二电平位移器被配置成输出信号至所述第二选通驱动器的幅度更大的幅度输出信号至所述第一选通驱动器。
6.根据权利要求1所述的PQFN封装，其中所述高压侧电力晶体管对应于所述桥电路的U-相电力开关、V-相电力开关和W-相电力开关之一。
7.根据权利要求1所述的PQFN封装，其中所述低压侧电力晶体管对应于所述桥电路的U-相电力开关、V-相电力开关和W-相电力开关之一。
8.根据权利要求1所述的PQFN封装，其中所述高压侧电力晶体管和所述低压侧电力晶体管中的至少一个对应于快速反相外延二极管场效应晶体管(FREDFET)。
9.根据权利要求1所述的PQFN封装，其中所述高压侧电力晶体管和所述低压侧电力晶体管中的至少一个对应于绝缘栅双极型晶体管(IGBT)。
10.根据权利要求1所述的PQFN封装，其中所述高压侧电力晶体管和所述低压侧电力晶体管中的至少一个对应于III-V族晶体管。
11.一种电力方形扁平无引线PQFN封装，包括：
引线框；以及
U-相电力开关、V-相电力开关、W-相电力开关和驱动器集成电路IC，所述U-相电力开关、V-相电力开关、W-相电力开关和驱动器IC中的每一个位于所述引线框上，其中所述驱动器IC包括：
第一电平位移器，其配置成输出信号至第一选通驱动器以驱动所述U-相电力开关；
第二电平位移器，其配置成输出信号至第二选通驱动器以驱动所述V-相电力开关；以及
第三电平位移器，其配置成输出信号至第三选通驱动器以驱动所述W-相电力开关。
12.根据权利要求11所述的PQFN封装，其中所述U-相电力开关、所述V-相电力开关和所述W-相电力开关中的至少一个对应于所述PQFN封装的桥电路的高压侧电力开关。
13.根据权利要求11所述的PQFN封装，其中所述U-相电力开关、所述V-相电力开关和所述W-相电力开关中的至少一个对应于所述PQFN封装的桥电路的低压侧电力开关。
14.根据权利要求11所述的PQFN封装，其中所述U-相电力开关、所述V-相电力开关和所述W-相电力开关中的至少一个对应于所述PQFN封装的桥电路的低压侧电力开关，并且所述U-相电力开关、所述V-相电力开关和所述W-相电力开关中的至少一个对应于所述PQFN封装的所述桥电路的高压侧电力开关。
15.根据权利要求11所述的PQFN封装，其中所述驱动器IC还包括低电压保护电路，所述低电压保护电路配置成检测电源电压低电压条件以禁止包括所述U-相电力开关、所述V-相电力开关和所述W-相电力开关的所述PQFN封装的桥电路的切换。
16.根据权利要求11所述的PQFN封装，其中所述驱动器IC还包括过电流保护电路，所述过电流保护电路配置成输出指示过电流条件的信号以禁止包括所述U-相电力开关、所述V-相电力开关和所述W-相电力开关的所述PQFN封装的桥电路的切换。
17.根据权利要求11所述的PQFN封装，其中所述U-相电力开关、所述V-相电力开关和所述W-相电力开关中的至少一个对应于快速反相外延二极管场效应晶体管(FREDFET)。
18.根据权利要求11所述的PQFN封装，其中所述U-相电力开关、所述V-相电力开关和所述W-相电力开关中的至少一个对应于绝缘栅双极型晶体管(IGBT)。
19.根据权利要求11所述的PQFN封装，其中所述U-相电力开关、所述V-相电力开关和所述W-相电力开关中的至少一个对应于III-V族晶体管。
CN201710493835.9A 2013-03-07 2014-01-27 单分流器倒相电路中的电力方形扁平无引线封装 Active CN107293531B (zh)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
US201361774484P 2013-03-07 2013-03-07
US61/774,484 2013-03-07
US14/102,275 2013-12-10
US14/102,275 US9659845B2 (en) 2010-12-13 2013-12-10 Power quad flat no-lead (PQFN) package in a single shunt inverter circuit
CN201410039117.0A CN104037154B (zh) 2013-03-07 2014-01-27 单分流器倒相电路中的电力方形扁平无引线封装

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
CN201410039117.0A Division CN104037154B (zh) 2013-03-07 2014-01-27 单分流器倒相电路中的电力方形扁平无引线封装

Publications (2)

Publication Number Publication Date
CN107293531A true CN107293531A (zh) 2017-10-24
CN107293531B CN107293531B (zh) 2021-03-12

Family

ID=49885048

Family Applications (2)

Application Number Title Priority Date Filing Date
CN201410039117.0A Active CN104037154B (zh) 2013-03-07 2014-01-27 单分流器倒相电路中的电力方形扁平无引线封装
CN201710493835.9A Active CN107293531B (zh) 2013-03-07 2014-01-27 单分流器倒相电路中的电力方形扁平无引线封装

Family Applications Before (1)

Application Number Title Priority Date Filing Date
CN201410039117.0A Active CN104037154B (zh) 2013-03-07 2014-01-27 单分流器倒相电路中的电力方形扁平无引线封装

Country Status (5)

Country Link
EP (1) EP2775518A3 (zh)
JP (1) JP6235918B2 (zh)
KR (1) KR101615512B1 (zh)
CN (2) CN104037154B (zh)
TW (1) TWI550734B (zh)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10818568B1 (en) * 2019-06-28 2020-10-27 Alpha And Omega Semiconductor (Cayman) Ltd. Super-fast transient response (STR) AC/DC converter for high power density charging application

Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20010015676A1 (en) * 2000-02-21 2001-08-23 Kumiko Takikawa Wireless communication system
US20060175627A1 (en) * 2005-02-08 2006-08-10 Masaki Shiraishi Power supply, multi chip module, system in package and non-isolated DC-DC converter
US20070196950A1 (en) * 2006-02-21 2007-08-23 Nobuyuki Shirai Semiconductor device and manufacturing the same
CN101030733A (zh) * 2007-03-21 2007-09-05 中国科学院电工研究所 一种轻型单元级联式多电平功率变换器
CN201234208Y (zh) * 2008-07-02 2009-05-06 东南大学 链式变换器功率单元控制器用开关电源
CN101577482A (zh) * 2008-06-13 2009-11-11 崇贸科技股份有限公司 用于功率转换器的具节能的晶体管闸极驱动电路
CN101582415A (zh) * 2004-03-31 2009-11-18 株式会社瑞萨科技 半导体器件
CN201928197U (zh) * 2010-12-13 2011-08-10 成都成电硅海科技股份有限公司 开关电源控制系统
CN102569241A (zh) * 2010-12-13 2012-07-11 国际整流器公司 利用引线框实现电互连的多芯片模块(mcm)功率四方扁平无引线(pqfn)半导体封装

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3394377B2 (ja) * 1996-01-09 2003-04-07 三菱電機株式会社 半導体装置および半導体モジュール
JP3674333B2 (ja) * 1998-09-11 2005-07-20 株式会社日立製作所 パワー半導体モジュール並びにそれを用いた電動機駆動システム
US6465875B2 (en) * 2000-03-27 2002-10-15 International Rectifier Corporation Semiconductor device package with plural pad lead frame
JP4450530B2 (ja) * 2001-07-03 2010-04-14 三菱電機株式会社 インバータモジュール
JP4004460B2 (ja) * 2003-12-16 2007-11-07 三菱電機株式会社 半導体装置
KR101340966B1 (ko) * 2006-05-24 2013-12-13 페어차일드코리아반도체 주식회사 3상 인버터 모듈 및 이를 이용한 모터구동장치와 인버터집적회로 패키지
US20090189261A1 (en) 2008-01-25 2009-07-30 Lay Yeap Lim Ultra-Thin Semiconductor Package
CN102074513A (zh) * 2009-11-25 2011-05-25 国碁电子(中山)有限公司 方形扁平无引脚芯片封装结构及方法
CN102148168B (zh) * 2010-02-04 2015-04-22 飞思卡尔半导体公司 制造具有改进抬升的半导体封装的方法
CN102184917B (zh) * 2011-03-25 2013-04-03 锐迪科创微电子（北京）有限公司 采用四方扁平无引脚封装的gsm射频发射前端模块
US20120256193A1 (en) * 2011-04-08 2012-10-11 Intersil Americas Inc. Monolithic integrated capacitors for high-efficiency power converters

Patent Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20010015676A1 (en) * 2000-02-21 2001-08-23 Kumiko Takikawa Wireless communication system
CN101582415A (zh) * 2004-03-31 2009-11-18 株式会社瑞萨科技 半导体器件
US20060175627A1 (en) * 2005-02-08 2006-08-10 Masaki Shiraishi Power supply, multi chip module, system in package and non-isolated DC-DC converter
US20070196950A1 (en) * 2006-02-21 2007-08-23 Nobuyuki Shirai Semiconductor device and manufacturing the same
CN101030733A (zh) * 2007-03-21 2007-09-05 中国科学院电工研究所 一种轻型单元级联式多电平功率变换器
CN101577482A (zh) * 2008-06-13 2009-11-11 崇贸科技股份有限公司 用于功率转换器的具节能的晶体管闸极驱动电路
CN201234208Y (zh) * 2008-07-02 2009-05-06 东南大学 链式变换器功率单元控制器用开关电源
CN201928197U (zh) * 2010-12-13 2011-08-10 成都成电硅海科技股份有限公司 开关电源控制系统
CN102569241A (zh) * 2010-12-13 2012-07-11 国际整流器公司 利用引线框实现电互连的多芯片模块(mcm)功率四方扁平无引线(pqfn)半导体封装

Also Published As

Publication number Publication date
TWI550734B (zh) 2016-09-21
KR20140110724A (ko) 2014-09-17
EP2775518A3 (en) 2017-11-08
KR101615512B1 (ko) 2016-04-26
CN104037154A (zh) 2014-09-10
EP2775518A2 (en) 2014-09-10
JP6235918B2 (ja) 2017-11-22
CN104037154B (zh) 2017-07-25
CN107293531B (zh) 2021-03-12
JP2014195045A (ja) 2014-10-09
TW201448065A (zh) 2014-12-16

Similar Documents

Publication Publication Date Title
US10438876B2 (en) Power quad flat no-lead (PQFN) package in a single shunt inverter circuit
US9362215B2 (en) Power quad flat no-lead (PQFN) semiconductor package with leadframe islands for multi-phase power inverter
US9601418B2 (en) Stacked half-bridge package
US9324646B2 (en) Open source power quad flat no-lead (PQFN) package
US9443795B2 (en) Power quad flat no-lead (PQFN) package having bootstrap diodes on a common integrated circuit (IC)
US9899481B2 (en) Electronic component and switch circuit
CN107305877A (zh) 适应性模制引线框封装件及相关方法
EP2775520B1 (en) Open source Power Quad Flat No-Lead (PQFN) leadframe
KR102041939B1 (ko) 다상 파워 인버터용 리드프레임 아일랜드들을 갖는 파워 쿼드 플랫 노-리드 반도체 패키지
CN104037154B (zh) 单分流器倒相电路中的电力方形扁平无引线封装
US20220102253A1 (en) Semiconductor package and method of manufacturing a semiconductor package
TWI570878B (zh) 在共同積體電路上具有自舉二極體的功率四面扁平無引線封裝

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant