CN101685807B - 散热型半导体封装件及其制法 - Google Patents

散热型半导体封装件及其制法 Download PDF

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CN101685807B
CN101685807B CN2008101612620A CN200810161262A CN101685807B CN 101685807 B CN101685807 B CN 101685807B CN 2008101612620 A CN2008101612620 A CN 2008101612620A CN 200810161262 A CN200810161262 A CN 200810161262A CN 101685807 B CN101685807 B CN 101685807B
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CN101685807A (zh
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曾祥伟
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JINGZHI SEMICONDUCTOR CO Ltd
Amtek Semiconductor Co Ltd
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Abstract

一种散热型半导体封装件及其制法，是在导线架的芯片座上布设多条金属线，以在该芯片座上粘贴半导体芯片时，使该半导体芯片直接接触该金属线，如此相比于现有技术中的半导体芯片通过银胶而安置于芯片座上的结构，本发明通过导热性佳、厚度低、热阻小的金属线，将有效减少半导体芯片运件时所产生的热量向外散发的热阻问题，进而提升半导体芯片的散热效率。

Description

散热型半导体封装件及其制法
技术领域
本发明涉及一种半导体封装件及其制法，特别是涉及一种具良好散热性的散热型半导体封装件及其制法。
背景技术
传统导线架式半导体封装件是在一导线架的芯片座上接置一半导体芯片，再利用打线及封胶作业，以形成用于包覆焊线及该半导体芯片的封装胶体；其中用以包覆芯片的封装胶体多为散热性差的环氧树脂(Epoxy Resin)类的材料，因此半导体芯片在运行时所产生的热量将无法经由封装胶体有效散发至外界，造成热量散发效率不佳，进而影响到半导体芯片的性能。
请参阅图1，为解决前述传统导线架式半导体封装件的散热问题，业界遂发展出一种具外露芯片座的半导体封装件，其是将半导体芯片11利用银胶13粘置于导线架12的芯片座121上，再进行打线及封胶作业，以使该半导体芯片11通过焊线14电性连接至该导线架12的导脚122，并形成包覆该焊线14及半导体芯片11的封装胶体15，其中相比于传统导线架式半导体封装件最大的差异是使该导线架12的芯片座121外露出该封装胶体15，以形成具外露芯片座的半导体封装件，后续即可将该具外露芯片座的半导体封装件通过焊锡16电性连接至一电路板17上，并使该外露的芯片座121通过该焊锡16而接置于该电路板17的一接地面(ground plane)171上，进而使该半导体芯片11运行时所产生的热量得以通过该芯片座121而传导至该接地面171，以有效解决传统导线架式半导体封装件散热不佳问题。该种具外露芯片座的半导体封装件技术可参见美国专利第5,252,783、5,594,234、6,143,981、6,583,499、6,661,083、6,818,973及6,400,004号。
然而前述具外露芯片座的半导体封装件仍存在着许多问题，主要是因为前述半导体芯片运行时所产生的热量传递路径是经由芯片表面、芯片硅基板、银胶、芯片座、焊锡至电路板的接地面，以进行热量的散发，但是该热量散发途径中所通过各元件的彼此间界面均构成影响热量散发的热阻(thermal resistance)，其中该芯片(硅基板)的热阻约为0.5℃/W，芯片座(主要材料为铜)的热阻约为0.1℃/W，而银胶的热阻约为10～40℃/W，且该热阻(R)的计算公式为R＝L/(KA)，其中该L代表热量通过的元件厚度，A代表热量通过的元件面积，K代表导热系数(thermal conductivity)，由该计算公式中明显可知，当L(热量通过的元件厚度)愈大时，热阻愈高，愈不利于散热。
因此，如何有效减少半导体芯片热量通过的元件厚度，即可有效减少热阻，进而提升半导体芯片的散热效率，实为目前业界为解决半导体封装件散热问题所急待考虑的问题。
发明内容
有鉴于上述现有技术的缺点，本发明的主要目的是提供一种散热型半导体封装件及其制法，得以有效减少半导体封装件的热阻，进而提升散热效率。
为达到上述目的，本发明提供一种散热型半导体封装件，包括：导线架，该导线架具有一芯片座及设于该芯片座周围的多个导脚；金属层，布设于该芯片座上；至少一半导体芯片，接触且承载于该金属层上；焊线，电性连接该半导体芯片及该导脚；以及封装胶体，包覆该焊线、半导体芯片及部分导线架，并至少使该芯片座底面及导脚部分面积外露出该封装胶体。
该金属层可由多条金属线所构成，该金属线可经由打线机进行焊接作业所制得，另外该金属线也可经由电镀、物理沉积、化学沉积作业所制得，且该多条金属线可呈水平方向、垂直方向、斜向、交叉网状、或任意排列方式，再者该多条金属线外围所构成的面积可选择大于、等于或小于半导体芯片的平面投影面积。此外，该金属层也可由多个金属块所排列形成。构成该金属层的该金属线的线径约为0.8～1.5mils(密尔)，该金属块的厚度约为0.8～1.5mils。
该半导体芯片是通过导热粘着层粘置于该芯片座上，但是使该半导体芯片直接接触该芯片座上的金属层。
本发明还提供一种散热型半导体封装件的制法，包括：提供一导线架，该导线架具有一芯片座及设于该芯片座周围的多个导脚；在该芯片座上布设一金属层；将至少一半导体芯片粘置于该芯片座上，并使该半导体芯片直接接触该金属层；电性连接该半导体芯片及该导脚；以及形成包覆该半导体芯片及部分导线架的封装胶体，并至少使该芯片座底面及导脚部分面积外露出该封装胶体。
该金属层的制法可利用打线机焊接多条金属线所形成，或经由电镀、物理沉积、化学沉积等方式形成多条金属线，其中该多条金属线可以水平方向、垂直方向、斜向、交叉网状结构、或任意形式进行排列，且该多条金属线外围所构成的面积可选择大于、等于或小于半导体芯片的平面投影面积。此外，该金属层也可由多个金属块所排列形成。另外，该半导体芯片与该芯片座间还包括有导热粘着层，且该半导体芯片直接接触该金属层。
因此，本发明的散热型半导体封装件及其制法是在导线架的芯片座上形成由多条金属线(或金属块)所构成的金属层，以在该芯片座上粘着半导体芯片时，使该半导体芯片直接接触该金属线(或金属块)，如此相比于现有的具外露芯片座的半导体封装件中半导体芯片通过银胶而接置于芯片座上的结构，本发明通过导热性较佳，且厚度较低，热阻较小的金属线(或金属块)，将可有效减少半导体芯片运行时产生的热量所通过元件的厚度，同时有效减少热阻，进而提升半导体芯片散热效率。
附图说明
图1为现有的具外露芯片座的半导体封装件示意图；
图2A至图2E为本发明的散热型半导体封装件及其制法第一实施例的示意图；
图2B’为对应图2B的局部俯视示意图；
图2C’为对应图2C的局部俯视示意图；
图2D’为对应图2D的局部俯视示意图；
图3为本发明的散热型半导体封装件接置于电路板的示意图；
图4为本发明的散热型半导体封装件第二实施例的示意图；
图5A至图5C为本发明的散热型半导体封装件第三实施例的示意图；
图6A及图6B为本发明的散热型半导体封装件第四实施例的示意图。
主要元件符号说明：
11             半导体芯片
12             导线架
121            芯片座
122            导脚
13             银胶
14             焊线
15             封装胶体
16             焊锡
17             电路板
171            接地面
20             金属层
201,401,501    金属线
201a           球型接点
201b           缝接焊点
21，31，51     半导体芯片
210            硅基板
211            主动面
212            非主动面
22             导线架
221,321,421,521芯片座
222            导脚
23             导热粘着层
24             焊线
25             封装胶体
26             导电材料
27         电路板
271        接地面
28         打线机
301        金属块
具体实施方式
以下通过特定的具体实施例说明本发明的实施方式，本领域技术人员可由本说明书所揭示的内容轻易地了解本发明的其他优点与功效。
第一实施例：
请参阅图2A至图2E，为本发明的散热型半导体封装件及其制法第一实施例的示意图。
如图2A所示，首先提供一导线架22，该导线架22具有一芯片座221及设于该芯片座221周围的多个导脚222。
如图2B及图2B’所示，其中该图2B’为对应图2B的局部俯视示意图，接着在该芯片座221上布设一金属层20，该金属层20例如由多条金属线201所构成，其可利用打线作业所使用的打线机(Wire bonder)28在该芯片座221上焊接多条金属线201，也就是说，该金属线201的制法是通过打线机28在该导线架22的芯片座221上利用该打线机28焊嘴先将焊线形成一球型接点201a(ball bond)，再移动该打线机28焊嘴至芯片座221的另一区域，接着截断该焊线以形成缝接焊点(stitchbond)201b，重复此步骤以在该芯片座221上焊接形成多条金属线201。该金属线201的材料可为金(Au)、铜(Cu)、铝(Al)所组群组的其中之一者。较为详细地，构成该金属层的该金属线201的线径约为0.8～1.5mils(密尔)。
该金属线201可如本图示呈水平状排列。另外，该金属线201也可由利用电镀、物理沉积、或化学沉积等方法形成于该芯片座221上。
如图2C及图2C’所示，其中该图2C’为对应图2C的局部俯视示意图，再在该芯片座221上对应这些金属线201位置涂布一例如银胶的导热粘着层23。
如图2D及图2D’所示，其中该图2D’为对应图2D的局部俯视示意图。提供至少一半导体芯片21，该半导体芯片由一芯片硅基板210组成，且具有相对的主动面211及非主动面212，并使该半导体芯片21以其非主动面212间隔该导热粘着层23而接置于该芯片座221上，同时使该半导体芯片21直接接触该金属线201。
如图2E所示，进行打线作业，利用打线机形成电性连接该半导体芯片主动面211及导脚222的焊线24。
接着，进行封装模压作业，以形成包覆该焊线24、半导体芯片21及部分导线架的封装胶体25，并至少使该芯片座221底面及导脚222部分面积外露出该封装胶体25，以形成具外露芯片座的半导体封装件。
通过前述制法，本发明还提供一种散热型半导体封装件，包括：导线架22，该导线架22具有一芯片座221及设于该芯片座221周围的多个导脚222；金属层20，布设于该芯片座上221，该金属层20是由多条金属线201所构成；至少一半导体芯片21，粘置于该芯片座221上，且使该半导体芯片21直接接触该些金属线201；焊线24，电性连接该半导体芯片21及该导脚222；以及封装胶体25，用以包覆该焊线24、半导体芯片21及部分导线架22，并至少使该芯片座221底面及导脚222部分面积外露出该封装胶体25。
请参阅图3，后续即可将本发明的散热型半导体封装件通过如焊锡的导电材料26接置并电性连接至如电路板27的外部装置，并使该半导体封装件外露出封装胶体25的芯片座221也得以通过该例如焊锡的导电材料26接置于电路板27的接地面271，以供该半导体芯片21运行时所产生的热量得以由该半导体芯片主动面211、芯片硅基板210、金属线201、芯片座221、焊锡26至该电路板接地面271而进行散发，其中由于本发明通过在导线架22的芯片座221上形成多条金属线201，并使该半导体芯片21直接接触该金属线201，如此相比于现有具外露芯片座的半导体封装件中半导体芯片通过银胶而接置于芯片座的结构，本发明通过导热性较佳，且厚度较低，热阻较小的金属线，将可减少热量通过的元件厚度，同时有效减少热阻，进而提升半导体芯片的散热效率。
第二实施例：
请参阅图4，为本发明的散热型半导体封装件第二实施例的示意图。
本实施例与前述实施例大致相同，主要差异在于设于导线架的芯片座321上的金属层也可由多个金属块301所构成，以供半导体芯片31粘置于该芯片座321上，同时接触这些金属块301，该金属块301可利用打线机直接焊接形成球形接点所制得，或通过电镀、物理沉积、化学沉积等方式制得。较为详细地，构成该金属层的该金属块301的厚度约为0.8～1.5mils。
第三实施例：
请参阅图5A至图5C，为本发明的散热型半导体封装件第三实施例的示意图。
本实施例与前述实施例大致相同，主要差异在于设于导线架的芯片座421上的金属层是由多条金属线401所构成，且相比于图2C的水平排列外，该多条金属线401也可呈垂直排列(如图5A所示)、斜向排列(如图5B所示)、或交叉网状排列(如图5C所示)。
当然该些多条金属线的排列方式非以前述图式为限，也可呈现前述排列方式的组合，或呈不规则排列。
第四实施例：
请参阅图6A及图6B，为本发明的散热型半导体封装件第四实施例的示意图。
本实施例与前述实施例大致相同，主要差异在于设于导线架的芯片座521上的多条金属线501外围所构成的面积除可大于半导体芯片的平面投影面积外，也可等于(如图6A所示)或小于(如图6B所示)半导体芯片51的平面投影面积。
因此，本发明的散热型半导体封装件及其制法是在导线架的芯片座上形成由多条金属线(或金属块)所构成的金属层，以在该芯片座上粘贴半导体芯片时，使该半导体芯片直接接触该金属线(或金属块)，如此相比于现有的具外露芯片座的半导体封装件中半导体芯片通过银胶而接置于芯片座上的结构，本发明通过导热性较佳，且厚度较低，热阻较小的金属线(或金属块)，将可有效减少半导体芯片运行时产生的热量所通过元件的厚度，同时有效减少热阻，进而提升半导体芯片的散热效率。
上述实施例仅为例示性说明本发明的原理及其功效，而非用于限制本发明。任何本领域技术人员均可在不违背本发明的精神及范畴下，对上述实施例进行修饰与变化。因此，本发明的权利保护范围，应以权利要求书的范围为依据。

Claims (21)

1.一种散热型半导体封装件，其特征在于，包括：
导线架，该导线架具有一芯片座及设于该芯片座周围的多个导脚；
金属层，布设于该芯片座上；
至少一半导体芯片，是通过导热粘着层粘置于该芯片座上，且使该半导体芯片直接接触该金属层及导热粘着层；
焊线，电性连接该半导体芯片及该导脚；以及
封装胶体，包覆该焊线、半导体芯片及部分导线架，并至少使该芯片座底面及导脚部分面积外露出该封装胶体。
2.根据权利要求1所述的散热型半导体封装件，其特征在于：该金属层是由多条金属线所构成。
3.根据权利要求2所述的散热型半导体封装件，其特征在于：该金属线是利用打线机在该芯片座上焊接形成。
4.根据权利要求3所述的散热型半导体封装件，其特征在于：该金属线是在该导线架的芯片座上利用打线机焊嘴先将焊线形成一球型接点，再移动该焊嘴至芯片座另一区域，接着截断焊线以形成缝接焊点，并重复在该芯片座上焊接形成多条金属线。
5.根据权利要求2所述的散热型半导体封装件，其特征在于：该多条金属线的排列方式是呈水平排列、垂直排列、斜向排列、及交叉网状排列所组群组的其中一者。
6.根据权利要求2所述的散热型半导体封装件，其特征在于：该金属线是由电镀、物理沉积、及化学沉积的其中之一方法形成于该芯片座上。
7.根据权利要求2所述的散热型半导体封装件，其特征在于：该金属线的线径为0.8～1.5mils。
8.根据权利要求1所述的散热型半导体封装件，其特征在于：该金属层的材料为金、铜、及铝所组群组的其中之一者。
9.根据权利要求1所述的散热型半导体封装件，其特征在于：该芯片座上的金属层是由多个金属块所构成。
10.根据权利要求9所述的散热型半导体封装件，其特征在于：该金属块的厚度为0.8～1.5mils。
11.根据权利要求9所述的散热型半导体封装件，其特征在于：该金属块是利用打线机焊接形成。
12.根据权利要求9所述的散热型半导体封装件，其特征在于：该金属块是通过电镀、物理沉积、及化学沉积的其中之一方式形成。
13.根据权利要求1所述的散热型半导体封装件，其特征在于：该芯片座上的金属层外围所构成的面积可选择大于、等于或小于半导体芯片的平面投影面积。
14.一种散热型半导体封装件的制法，其特征在于，包括：
提供一导线架，该导线架具有一芯片座及设于该芯片座周围的多个导脚；
在该芯片座上布设一金属层；
通过导热粘着层将至少一半导体芯片粘置于该芯片座上，并使该半导体芯片直接接触该金属层及导热粘着层；
电性连接该半导体芯片及该导脚；以及
形成包覆该半导体芯片及部分导线架的封装胶体，并至少使该芯片座底面及导脚部分面积外露出该封装胶体。
15.根据权利要求14所述的散热型半导体封装件的制法，其特征在于：该金属层是由多条金属线所构成。
16.根据权利要求15所述的散热型半导体封装件的制法，其特征在于：该金属线是利用打线机在该芯片座上焊接形成。
17.根据权利要求16所述的散热型半导体封装件的制法，其特征在于：该金属线是在该导线架的芯片座上利用打线机焊嘴先将焊线形成一球型接点，再移动该焊嘴至芯片座另一区域，接着截断焊线以形成缝接焊点，并重复在该芯片座上焊接形成多条金属线。
18.根据权利要求15所述的散热型半导体封装件的制法，其特征在于：该多条金属线的排列方式是呈水平排列、垂直排列、斜向排列、及交叉网状排列所组群组的其中一之者。
19.根据权利要求15所述的散热型半导体封装件的制法，其特征在于：该金属线是由电镀、物理沉积、及化学沉积的其中一之方法形成于该芯片座上。
20.根据权利要求15所述的散热型半导体封装件的制法，其特征在于：该金属线的线径为0.8～1.5mils。
21.根据权利要求14所述的散热型半导体封装件的制法，其特征在于：该金属层的材料为金、铜、及铝所组群组的其中之一者。
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CN1499619A (zh) * 2002-11-11 2004-05-26 ������������ʽ���� 模塑树脂封装型功率半导体装置及其制造方法
CN101180726A (zh) * 2005-05-23 2008-05-14 德克萨斯仪器股份有限公司 使用背面散热的集成电路管芯固定

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CN2543202Y (zh) * 2002-04-15 2003-04-02 叶颖明 一种软封装芯片
CN1499619A (zh) * 2002-11-11 2004-05-26 ������������ʽ���� 模塑树脂封装型功率半导体装置及其制造方法
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