CN101180726A - 使用背面散热的集成电路管芯固定 - Google Patents

使用背面散热的集成电路管芯固定 Download PDF

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CN101180726A
CN101180726A CNA2006800177274A CN200680017727A CN101180726A CN 101180726 A CN101180726 A CN 101180726A CN A2006800177274 A CNA2006800177274 A CN A2006800177274A CN 200680017727 A CN200680017727 A CN 200680017727A CN 101180726 A CN101180726 A CN 101180726A
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metal layer
heat
chip
layer
conducting
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B·兰格
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Texas Instruments Inc
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Texas Instruments Inc
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Abstract

导热金属层(200)形成在集成电路芯片(102)的背面上，通过环氧树脂或其它管芯固定材料(106)固定在衬底(104)上。金属层(200)通过传导出现在管芯固定材料内的气孔(109)周围的、来自芯片(102)的热来改善散热。金属层(200)可以是复合结构，有主要金属层、一个或多个阻挡金属层、提高金属粘合到芯片上的能力的粘合金属层和能够选择地直接将焊料附在衬底上的焊料层。

Description

使用背面散热的集成电路管芯固定
【0001】本发明一般涉及集成电路的管芯固定领域；并且，更特别地是涉及使用了背面散热管芯固定的集成电路器件和方法。
背景技术
【0002】增加功耗需要、减小功率晶体管尺寸和其它因素促使单位面积上需要更大的功耗。在集成电路封装中，热量通常是从芯片表面通过芯片和管芯固定材料散布到引线框(leadframe)管芯焊盘或外部热沉热沉。管芯固定材料中的气孔(void)能导致管芯表面上的局部热点，这是由于在这些点有降低的热传导。这些热点能导致可靠性故障。如果在功率晶体管中出现成孔，例如，如果芯片上实现了过热保护则电路寿命会减少或者输出驱动能力会降低。
发明内容
【0003】根据本发明的一个实施例，集成电路管芯固定包括准备一个芯片、在芯片背面向外形成一个导热金属层以及连接芯片到衬底上。导热背面金属层，例如铜，沉积在晶片(wafer)背面，作为散热层来传导孔周围的热量。芯片背面上的金属厚度可以根据需要的性能而变化。一个优选的导热金属层有至少0.5密耳的厚度。本发明提供从芯片到引线框管芯焊盘或外部热沉热沉的有利散热。
附图说明
【0004】图1是根据本发明的一个实施例的集成电路芯片器件的横截面图，该器件有固定在热沉热沉上的导热背面金属层。
【0005】图2是图1中导热背面金属层的一个应用实例的横截面图；以及
【0006】图3至图5根据本发明的不同实施例，图释了芯片和导热背面金属层结合的不同封装。
发明的详细描述
【0007】本发明的具体实施例参考附图中的图1至图5被描述，其中同样的数字指的是同样的元件。
【0008】图1是根据本发明的一个实施例的管芯固定系统100的横截面图。在图示的实施例中，系统100包括半导体芯片102，该芯片102有通过管芯固定材料106连接到衬底104上的导热背面金属层200。如下面更详细的描述，导热背面金属层200有利于提高从半导体芯片102到衬底104的散热。
【0009】芯片102可以是有任何合适尺寸和形状的任何适当的半导体芯片或者管芯，并且可以以任何适当的材料形式和层数形成。芯片1 02上也有任何适当的相关电子部件。例如，如图1所示，一个或多个功率晶体管108可以被连接到芯片102的上表面103上。与芯片102相关的部件，例如功率晶体管108，产生热量，该产生的热量需要通过芯片102的厚度、通过导热背面金属层200、通过管芯固定材料106向下耗散到衬底104内，一般如箭头110所指示。导热的背面金属层200作为一个散热层来促进这种耗散，以散布由与芯片102关联的功率晶体管108或其它部件产生的在一个或多个孔109四周的热量，其中所述孔109在芯片102连接到衬底104期间形成在管芯固定材料106内。下面进一步结合图2描述导热背面金属层200。
【0010】管芯固定材料106可以是任何适当的管芯固定材料，例如环氧树脂、粘合膜或焊料。管芯固定材料106可以是任何适当的厚度。衬底104可以是任何适当的衬底，其作为热沉并且可以有任何适当的尺寸和形状。在一个实施例中，衬底104是由适当适当金属形成的引线框。
【0011】图2所示为根据本发明的一个实施例的导热背面金属层200。在一个实施例中，导热背面金属层200包括至少为0.5密耳的厚度201。在本发明的一个更特别实施例中，厚度201至少为0.5密耳并且不超过4.0密耳。在所述实施例中，导热背面金属层200包括粘合金属层202、阻挡金属层204、金属层206、阻挡金属层208和可焊金属层210。本发明预期导热背面金属层200有比图2所示更多、更少或不同的部件。
【0012】导热背面金属层200可以以任何适当方式形成在芯片102上，例如通过背面溅射、电镀或其它适当处理方法。导热背面金属层200优选地形成在晶片级上。
【0013】粘合金属层202可以有任何适当的厚度，并且可以由任何适当的材料形成，例如铬、钛和钛钨。粘合金属层202作为导热背面金属层200的后续层的粘合层。如果金属层206使用的材料有足够的粘合性能够粘合到芯片102的背面，则粘合金属层202可以不存在。
【0014】阻挡金属层204也是可选择层，该层可以有任何适当的厚度并且可以是任何适当的材料形成的，例如镍、铜和钛钨。阻挡金属层204作为金属层206的扩散阻挡层。
【0015】金属层206可以有任何适当的导热金属形成，例如铜、镍、钯、钨、金和银。在一个实施例中，金属层206有至少0.5密耳的厚度。金属层206是作为散热层的主要层，来散布由与芯片102关联的功率晶体管108或其它部件产生的热量。
【0016】阻挡金属层208也是导热背面金属层200的可选择层，阻挡金属成208可以有任何适当厚度，并且由任何适当材料形成，例如镍或钛钨。阻挡金属层208作为扩散阻挡层，以便当焊接处理或经受较高的封装温度时，金属层206不扩散到焊料内。
【0017】可焊金属层210可以有任何适当厚度并且由任何适当材料形成，例如钯、金或银。在焊料管芯固定处理中，是可选择层的可焊金属层210用来允许导热背面金属层200被焊接到衬底上，例如衬底104上。一般地，可焊金属层210溶解在液体焊料内，然后该焊料浸湿阻挡金属层208。
【0018】根据本发明的一个实施例的操作并且参考图1和图2，芯片102装备了导热背面金属层200，所述芯片102具有与其相关的功率晶体管108或其它电气部件。在芯片102通过管芯固定材料106连接到衬底104上前，形成导热背面金属层200的每一层均形成在芯片102的背面。在芯片102连接到衬底104期间，气孔109会产生在管芯固定材料106中。在芯片102工作时，热量由功率晶体管108和其它电子部件产生，该热量需要被散逸，以防止在芯片102内由孔109引起局部热点。导热背面金属层200作为散热层以便将由功率晶体管108产生的热量散步在孔的周围并散布到衬底104中。
【0019】图3至图5图示了根据本发明的不同实施例，将芯片102和导热背面金属层200结合在一起的不同封装方法。首先参考图3，图示了封装300，其中用多个引线接合将芯片102连接到印刷电路板302上。为了封装芯片102，可以利用圆顶封装体(“glob top”)301。(“圆顶封装体”是工业术语，用来形容不导电的封装材料的圆形沉积，经常是塑料。)圆顶封装体301可以是由任何适当的材料形成，例如适当的成形化合物。印刷电路板302可以是由任何适当材料形成的任何适当的印刷电路板。
【0020】图4所示为封装400的一个实施例，其中管芯固定材料106是用于直接焊料管芯固定方法的焊料。在另一些实施例中，管芯固定材料106可以是环氧树脂或粘合膜。有导热背面金属层200的芯片102被连接到外部散热器402上，该外部散热器402在芯片102需要放置的位置有可焊金属层404。外部散热器可以是任何适当尺寸和形状的散热片，并且可焊金属层404可以是由任何适当材料以任何适当的厚度形成。通过多个引线接合407，芯片102也被连接到多个引线接头406上，并且其后由密封剂408密封，该密封剂可以是任何适当的封装材料。引线接头406可以通过多个引线接合410被连接到一个适当的印刷电路板409上。在一个可选择实施例中，芯片102可以通过引线接合407被直接连接到印刷电路板409上。引线接头406可以被焊接或其它电学连接到印刷电路板409上。
【0021】图5所示为封装500，该封装类似用于表面装配技术或通过孔装配在印刷电路板上的传统集成电路封装。在这个实施例中，在通过多个引线接合503将芯片102连接到多个引线接头502前，芯片102通过管芯固定材料106被连接到衬底104上。其后，芯片102由适当的密封剂504密封，该密封剂可以是任何适当的封装材料。即使引线接头502在图5中向下朝向衬底104形成，本发明预期引线接头502远离衬底104被形成。在图5的一个可选择实施例中，衬底104可以是和引线接头502同样形式的材料和厚度，并且可以与引线接头502成为一体。
【0022】本发明相关领域的技术人员将意识到，在所有不超出权利要求的发明的范围内，可以在所述实例实施例上进行不同的变型、附加和省略。

Claims (10)

1.一种集成电路器件，包括：
半导体芯片，该芯片具有与其相关的一个或多个电子部件并具有背部表面；
形成在所述芯片的背部表面上的导热金属层；
该导热金属层适于并被配置成通过传导来自围绕孔的所述芯片的热量来促进散热，其中所述孔在管芯固定材料内，所述管芯固定材料用来固定所述芯片到下面的引线框或其它安装衬底上。
2.根据权利要求1所述的器件，其中所述导热金属层有主要金属层，该主要金属层包括铜、镍、钯、钨、金和银中的至少一种。
3.根据权利要求1或2所述的器件，其中所述导热层包括主要金属层和至少一个阻挡层，该阻挡层包括镍、铜和钛钨中的至少一种。
4.根据权利要求1或2所述的器件，其中所述导热层包括主要金属层和粘合金属层，该粘合金属层包括铬、钛和钛钨中的至少一种；该粘合层被附在所述芯片的背部表面。
5.根据权利要求1或2所述的器件，其中所述导热层包括主要金属层和可焊金属层，该可焊金属层包括钯、金或银中的至少一种；所述可焊金属层适于并被配置成能够将所述导热层焊接到所述下面的引线框或其它安装衬底上。
6.根据权利要求1所述的器件，其中所述导热金属层是复合层，该复合层包括主要金属层和在所述主要金属层相对面的第一和第二阻挡层。
7.根据权利要求6所述的器件，其中所述导热层进一步包括粘合金属层，该粘合金属层将所述阻挡层中的第一阻挡层附着在所述芯片的所述背部表面。
8.根据权利要求6或7所述的器件，其中所述导热层进一步包括可焊金属层，该可焊金属层用来通过焊接方法将所述阻挡层中的第二阻挡层附着在所述下面的引线框或其它安装衬底上。
9.根据权利要求8所述的器件，其中，如可适用的，
所述主要金属层包括铜、镍、钯、钨、金和银中的至少一种；
每个阻挡层包括镍、铜和钛钨中的至少一种；
所述粘合金属层包括铬、钛和钛钨中的至少一种；以及
所述可焊金属层包括钯、金或银中的至少一种。
10.一种将集成电路器件固定在衬底上的方法，包括：
提供半导体芯片，该芯片具有与其相关的一个或多个电子部件并且具有背部表面；
提供形成在所述芯片的背部表面上的导热金属层；
通过环氧树脂、焊料或其它管芯固定材料的手段，将所述芯片在所述导热金属层处固定在下面的引线框或其它安装衬底上；
借此，通过引导围绕孔的热量来将热量从所述芯片传导到其它安装衬底的引线框上，所述导热金属层促进散热，所述孔存在于所述管芯固定材料中。
CNA2006800177274A 2005-05-23 2006-05-23 使用背面散热的集成电路管芯固定 Pending CN101180726A (zh)

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Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101685807B (zh) * 2008-09-24 2011-07-13 晶致半导体股份有限公司 散热型半导体封装件及其制法
CN103035169A (zh) * 2011-10-04 2013-04-10 乐金显示有限公司 显示设备及其驱动器组件以及传递热的方法
CN105720024A (zh) * 2009-02-02 2016-06-29 马克西姆综合产品公司 热性改进的半导体封装
CN114446904A (zh) * 2021-12-30 2022-05-06 光梓信息科技(深圳)有限公司 基于纳米级散热器的晶圆封装结构及方法

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7335534B2 (en) * 2005-01-10 2008-02-26 Hvvi, Semiconductors, Inc. Semiconductor component and method of manufacture
US7605451B2 (en) * 2006-06-27 2009-10-20 Hvvi Semiconductors, Inc RF power transistor having an encapsulated chip package
US8110906B2 (en) * 2007-01-23 2012-02-07 Infineon Technologies Ag Semiconductor device including isolation layer
US7923823B2 (en) * 2007-01-23 2011-04-12 Infineon Technologies Ag Semiconductor device with parylene coating
US8067834B2 (en) * 2007-08-21 2011-11-29 Hvvi Semiconductors, Inc. Semiconductor component
US8361899B2 (en) 2010-12-16 2013-01-29 Monolithic Power Systems, Inc. Microelectronic flip chip packages with solder wetting pads and associated methods of manufacturing
TWI476841B (zh) 2012-03-03 2015-03-11 矽品精密工業股份有限公司 半導體封裝件及其製法
JP2019161105A (ja) * 2018-03-15 2019-09-19 東芝メモリ株式会社 半導体装置
US10764989B1 (en) 2019-03-25 2020-09-01 Dialog Semiconductor (Uk) Limited Thermal enhancement of exposed die-down package

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4872047A (en) * 1986-11-07 1989-10-03 Olin Corporation Semiconductor die attach system
KR100307465B1 (ko) * 1992-10-20 2001-12-15 야기 추구오 파워모듈
US5371404A (en) * 1993-02-04 1994-12-06 Motorola, Inc. Thermally conductive integrated circuit package with radio frequency shielding
US5777385A (en) * 1997-03-03 1998-07-07 International Business Machines Corporation Ceramic ball grid array (CBGA) package structure having a heat spreader for integrated-circuit chips
JPH11233712A (ja) * 1998-02-12 1999-08-27 Hitachi Ltd 半導体装置及びその製法とそれを使った電気機器
US6770513B1 (en) 1999-12-16 2004-08-03 National Semiconductor Corporation Thermally enhanced flip chip packaging arrangement
JP3815239B2 (ja) * 2001-03-13 2006-08-30 日本電気株式会社 半導体素子の実装構造及びプリント配線基板
KR100443399B1 (ko) * 2001-10-25 2004-08-09 삼성전자주식회사 보이드가 형성된 열 매개 물질을 갖는 반도체 패키지
US6870243B2 (en) 2002-11-27 2005-03-22 Freescale Semiconductor, Inc. Thin GaAs die with copper back-metal structure
US6833289B2 (en) * 2003-05-12 2004-12-21 Intel Corporation Fluxless die-to-heat spreader bonding using thermal interface material
TWI247395B (en) * 2004-03-09 2006-01-11 Siliconware Precision Industries Co Ltd Semiconductor package with heatsink and method for fabricating the same and stiffener

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101685807B (zh) * 2008-09-24 2011-07-13 晶致半导体股份有限公司 散热型半导体封装件及其制法
CN105720024A (zh) * 2009-02-02 2016-06-29 马克西姆综合产品公司 热性改进的半导体封装
CN103035169A (zh) * 2011-10-04 2013-04-10 乐金显示有限公司 显示设备及其驱动器组件以及传递热的方法
CN103035169B (zh) * 2011-10-04 2016-03-09 乐金显示有限公司 显示设备及其驱动器组件以及传递热的方法
CN114446904A (zh) * 2021-12-30 2022-05-06 光梓信息科技(深圳)有限公司 基于纳米级散热器的晶圆封装结构及方法

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