CN114093855A - 用于半导体装置组合件的堆叠半导体裸片 - Google Patents
用于半导体装置组合件的堆叠半导体裸片 Download PDFInfo
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- CN114093855A CN114093855A CN202110948031.XA CN202110948031A CN114093855A CN 114093855 A CN114093855 A CN 114093855A CN 202110948031 A CN202110948031 A CN 202110948031A CN 114093855 A CN114093855 A CN 114093855A
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- H01L2924/181—Encapsulation
Abstract
公开用于半导体装置组合件的堆叠半导体裸片及相关联方法和系统。在一些实施例中,所述半导体裸片组合件包含衬底,所述衬底具有在所述衬底的内部部分中的第一开口和外部部分中的第二开口。此外,所述半导体裸片组合件可包含附接到所述衬底的前侧的主裸片,其中所述主裸片包含靠近所述第一开口的第一接合垫和靠近所述第二开口的第二接合垫。所述主裸片的所述第一接合垫和所述第二接合垫可使用分别延伸穿过所述第一开口和所述第二开口的第一接合线和第二接合线与所述衬底的与所述前侧相对的背侧上的第一和第二衬底接合垫耦合。
Description
技术领域
本公开大体上涉及半导体裸片组合件,且更具体地,涉及用于半导体装置组合件的堆叠半导体裸片及相关联系统和方法。
背景技术
半导体封装通常包含安装在衬底上且围封在保护性覆盖物中的一或多个半导体裸片(例如存储器芯片、微处理器芯片、成像器芯片)。半导体裸片可包含功能特征,例如存储器单元、处理器电路和成像器装置,以及电连接到所述功能特征的接合垫。接合垫可电连接到衬底的对应导电结构,所述导电结构可耦合到保护性覆盖物外部的端子以使得半导体裸片可连接到较高层级电路。
市场压力不断促使半导体制造商减小裸片封装的尺寸以适应电子装置的空间约束,同时也促使他们降低与制造裸片封装相关联的成本。在一些半导体封装中,两个或更多个半导体裸片堆叠在彼此之上以减少半导体封装的覆盖面积。在一些情况下,半导体裸片可包含衬底穿通孔(TSV)以便于半导体裸片的堆叠。
发明内容
根据本申请的方面,提供一种半导体裸片组合件。所述半导体裸片组合件包括:衬底,其包含前侧和与所述前侧相对的背侧,其中所述衬底包含所述衬底的内部部分中的第一开口和所述衬底的外部部分中的第二开口;主裸片,其附接到所述衬底的所述前侧,其中所述主裸片包含朝向所述衬底的所述前侧的第一侧,所述主裸片的所述第一侧包含靠近所述第一开口的第一接合垫和靠近所述第二开口的第二接合垫;第一接合线,其穿过所述第一开口将所述主裸片的所述第一接合垫与所述衬底的所述背侧上的第一衬底接合垫耦合;以及第二接合线,其穿过所述第二开口将所述主裸片的所述第二接合垫与所述衬底的所述背侧上的第二衬底接合垫耦合。
根据本申请的另一方面,提供一种半导体裸片组合件。所述半导体裸片组合件包括:封装衬底,其包含前侧和与所述前侧相对的背侧,其中所述封装衬底包含所述封装衬底的中间部分中的第一开口和所述封装衬底的周边部分中的第二开口;第一半导体裸片,其附接到所述封装衬底的所述前侧,其中所述第一半导体裸片包含朝向所述封装衬底的所述前侧的第一侧,所述第一半导体裸片的所述第一侧包含靠近所述第一开口的第一接合垫和靠近所述第二开口的第二接合垫;第一接合线,其穿过所述第一开口将所述第一半导体裸片的所述第一接合垫与所述衬底的所述背侧上的第一衬底接合垫耦合;以及第二接合线,其穿过所述第二开口将所述第一半导体裸片的所述第二接合垫与所述衬底的所述背侧上的第二衬底接合垫耦合。
根据本申请的又一方面,提供一种方法。所述方法包括:在包含前侧和与所述前侧相对的背侧的衬底中形成第一和第二开口,所述第一开口位于所述衬底的内部部分中,并且所述第二开口位于所述衬底的外部部分中;将主裸片附接到所述衬底的所述前侧,其中所述主裸片包含朝向所述衬底的所述前侧的第一侧,所述主裸片的所述第一侧包含靠近所述第一开口的第一接合垫和靠近所述第二开口的第二接合垫;形成穿过所述第一开口将所述主裸片的所述第一接合垫与所述衬底的所述背侧上的第一衬底接合垫耦合的第一接合线;以及形成穿过所述第二开口将所述主裸片的所述第二接合垫与所述衬底的所述背侧上的第二衬底接合垫耦合的第二接合线。
附图说明
参照附图可以更好地理解本发明技术的许多方面。附图中的组件不一定按比例。实际上,重点在于清楚地说明本发明技术的总特征和原理。
图1是半导体裸片组合件的横截面图。
图2是根据本发明技术的实施例配置的半导体裸片组合件的横截面图。
图3是示意性地说明包含根据本发明技术的实施例配置的半导体裸片组合件的系统的框图。
图4是形成根据本发明技术的实施例配置的半导体裸片组合件的方法的流程图。
具体实施方式
下文描述用于半导体装置组合件的堆叠半导体裸片的若干实施例的特定细节以及相关联系统和方法。术语“半导体装置或裸片”一般指包含一或多种半导体材料的固态装置。半导体装置(或裸片)的实例包含逻辑装置、存储器装置、控制器或微处理器(例如,中央处理单元(CPU)、图形处理单元(GPU)),以及其它装置。此类半导体装置可包含集成电路或组件、数据存储元件、处理组件和/或在半导体衬底上制造的其它特征。
在某些半导体封装中,封装衬底(也可称为支撑衬底、衬底等)可承载第一半导体裸片,在其上布置一或多个第二半导体裸片。在一些情况下,第一半导体裸片不同于第二半导体裸片,例如,第一半导体裸片是存储器控制器裸片,并且一或多个第二半导体裸片是存储器裸片。在其它情况下,第一半导体裸片在结构上与第二半导体裸片相同。例如,第一半导体裸片和一或多个第二半导体裸片是相同类型的存储器裸片,例如,动态随机存取存储器(DRAM)裸片的堆叠。在此类情况下,堆叠的最底部的裸片(例如,附接到衬底的DRAM裸片,第一半导体裸片)可以用作堆叠的剩余半导体裸片的主裸片,所述剩余半导体裸片可以被称为从裸片(例如,堆叠的剩余DRAM裸片)。
小外观尺寸封装对在衬底上方容纳半导体裸片(例如DRAM裸片)的堆叠提出了挑战。在一些实施例中,半导体裸片可具有TSV,其便于半导体裸片的线内堆叠以减少堆叠的覆盖面积。然而,形成TSV往往会增加半导体装置组合件的成本。在一些实施例中,主裸片可翻转(例如,其具有导电柱的有源表面朝向衬底)并直接连接到衬底(例如,衬底的导电垫电连接到主裸片的导电柱),其可称为倒装芯片或直接芯片附接(DCA)方案。产生导电柱(和有助于导电柱连接到主裸片的接触垫的其它结构)并将导电柱连接到衬底的对应导电垫的工艺步骤可称为凸块工艺。通常,例如考虑到涉及的许多工艺模块(例如,薄膜沉积、光刻、蚀刻、清洁)以及与凸块工艺相关联的各种产量和/或可靠性问题,凸块工艺往往是用于形成半导体装置组合件的成本高昂的工艺。
本发明技术的各个方面有助于提供成本较低的替代品,以产生具有半导体裸片堆叠的半导体裸片组合件,例如,无需使用TSV和/或凸块工艺。如本文更详细描述的,主裸片可翻转以使其有源表面朝向衬底。以这种方式,信号完整性(例如,传播延迟)可以保持与采用凸块工艺的半导体组合件相当。此外,衬底可包含衬底中的开口,其从衬底的前表面延伸到背表面。衬底还包含背表面上的衬底接合垫,使得可以形成接合线,以代替凸块工艺而通过开口将主裸片的接合垫电耦合到背表面上的衬底接合垫。
此外,从裸片可放置在主裸片上方,以使其有源表面背对衬底。以这种方式,可以形成接合线以将从裸片的接合垫与衬底前表面上的衬底接合垫电耦合。因而,主裸片和从裸片都建立到衬底的电连接,这可配置成例如通过衬底中的导电迹线操作地将主裸片与从裸片耦合。因此,主裸片和从裸片可通过衬底中的导电迹线而不是TSV在它们之间建立电连接。
如本文中所使用,术语“前”、“后”、“竖直”、“横向”、“向下”、“向上”、“上部”和“下部”可指半导体装置组合件中的特征鉴于图中展示的定向的相对方向或位置。例如,“上部”或“最上部”可指比另一特征更接近页面的顶部定位的特征。然而,这些术语应当广义地解释为包含具有其它定向的半导体装置。除非以其它方式陈述,否则例如“第一”和“第二”等术语用于任意地区别这些术语所描述的元件。因此,这些术语未必意在指示此类元件的时间或其它优先级排序。
图1是半导体裸片组合件100(“组合件100”)的横截面图。组合件100可包含衬底105、附接到衬底105的第一半导体裸片130(例如,主裸片),以及第二半导体裸片150(例如,从裸片)。此外,组合件100示出了第二半导体裸片150与衬底105之间的接合线165,以及第一半导体裸片130与衬底105之间的互连件180。
衬底105包含前侧106和与前侧106相对的背侧107。前侧106可包含各种导电结构,例如用于接合线165的衬底接合垫145、用于互连件180的导电垫、金属迹线和/或导线等。金属迹线可配置成在前侧106(例如,前侧106上的导电结构)与背侧107(例如,背侧107上的端子125)之间路由电信号。背侧107上的端子125可将组合件100耦合到其它组件,例如,通过端子125将组合件100安装在印刷电路板上,所述印刷电路板承载其它组件。
第一半导体裸片130包含第一侧131和与第一侧131相对的第二侧132。第一半导体裸片130的第一侧131可包含各种导电结构,例如接合垫135、再分布特征136(例如,配置成在接合垫135之间路由电信号的金属迹线)等。如图1所示,第一半导体裸片130布置成使第一侧131朝向衬底105的前侧106,例如,与第二半导体裸片150相比翻转。此外,第一半导体裸片130通过具有高度H的互连件180耦合到衬底105。在一些实施例中,个别互连件180包含耦合到第一半导体裸片130的接合垫(或接触垫)的导电柱、衬底105的导电垫以及导电柱与导电垫之间的接合材料(例如,焊料材料)。以这种方式,第一半导体裸片130可以附接到衬底105并建立到衬底105的电连接。
第二半导体裸片150包含第一侧151(例如,有源侧,鉴于靠近第一侧151的第二半导体裸片150的功能特征)和与第一侧151相对的第二侧152(例如,无源侧)。图1示出第二半导体裸片150布置成使第一侧151背对衬底105的前侧106。在一些实施例中,第二半导体裸片150的结构可与第一半导体裸片130相同。例如,第一半导体裸片130可以是第二半导体裸片150的主裸片,并且第二半导体裸片150可以是从裸片。第二半导体裸片150的第一侧151可包含各种导电结构,例如接合垫160、再分布特征161(例如,配置成在接合垫160之间路由电信号的金属迹线)等。此外,粘合层(未示出)可安置在最底部的第二半导体裸片与第一半导体裸片130之间,以将第二半导体裸片150附接到第一半导体裸片130。第二半导体裸片150通过接合线165耦合到衬底105,例如,第二半导体裸片150的接合垫(例如,接合垫160)通过接合线165耦合到衬底105的衬底接合垫145。以这种方式,第二半导体裸片150可以附接到第一半导体裸片130并建立到衬底105的电连接。
如上所述,第一半导体裸片130(例如,主裸片)可通过互连件180电连接到衬底105,并且第二半导体裸片150(例如,从裸片)可通过接合线165电连接到衬底105。衬底105可配置成例如通过衬底105的导电迹线操作地耦合第一半导体裸片130和第二半导体裸片150。此外,第一半导体裸片130、第二半导体裸片150和接合线165可通过模塑件170包封。与包含带TSV的半导体裸片的半导体裸片组合件相比,组合件100可提供低成本的替代方案。此外,鉴于第一半导体裸片130的倒装芯片配置,组合件100可通过第一半导体裸片130提供合适的信号传输能力(例如,关于行业标准规范,例如联合电子装置工程委员会(JEDEC))。
图2是半导体裸片组合件200(“组合件200”)的横截面图。组合件200可包含衬底205、附接到衬底205的第一半导体裸片230(例如,主裸片),以及布置在第一半导体裸片230上方的第二半导体裸片250(例如,从裸片)。此外,组合件200示出了第一半导体裸片230与衬底205之间的接合线240,以及第二半导体裸片250与衬底205之间的接合线265。第一半导体裸片230可包含第一半导体裸片130的方面。此外,第二半导体裸片250可以是第二半导体裸片150的实例或包含所述第二半导体裸片的方面。
衬底205包含前侧206和与前侧206相对的背侧207。前侧206可以具有各种导电结构,例如用于接合线265的衬底接合垫245(也个别地标识为245c-d)、金属迹线和/或导线等。类似地,背侧207可以具有各种导电结构,例如用于接合线240的衬底接合垫245(也个别地标识为245a和245b)、金属迹线和/或导线等。金属迹线可配置成在各种导电结构之间提供电连接。此外,金属迹线可配置成在前侧206(例如,前侧206上的导电结构)与背侧207(例如,背侧207上的导电结构和背侧207上的端子225)之间路由电信号。背侧207上的端子225可将组合件200耦合到其它组件,例如,通过端子225将组合件200安装在印刷电路板上,所述印制电路板承载其它组件。在一些实施例中,端子225包含焊球。此外,衬底205可包含一或多个开口220。例如,组合件200的衬底205包含在衬底205的内部部分(例如,中间部分)中的第一开口220a和外部部分(例如,周边部分)中的第二开口220b。第一开口220a和第二开口220b从衬底205的第一侧206延伸到第二侧207。
第一半导体裸片230包含第一侧231和与第一侧231相对的第二侧232。鉴于靠近第一侧231的第一半导体裸片的功能特征,第一侧231可被称为有源侧。第二侧232可被称为无源侧,与有源侧相对。第一半导体裸片230的第一侧231可包含各种导电结构,例如接合垫235(也个别地标识为235a和235b)、再分布特征236(例如,配置成在接合垫235之间路由电信号的金属迹线)等。如图2所示,第一半导体裸片230布置成使第一侧231朝向衬底205的前侧206,例如,与第二半导体裸片250相比翻转。在一些实施例中,第一半导体裸片230通过安置在第一半导体裸片230的第一侧231与衬底205的前侧206之间的粘合层(未示出)附接到衬底205。在一些实施例中,粘合层的厚度可小于参考图1描述的互连件180的高度(H)。因而,如图2所示,衬底205上方的半导体裸片堆叠的总高度可小于图1的半导体裸片堆叠的总高度。
如图2所示,第一半导体裸片230的接合垫235可布置成靠近(例如,邻近)衬底205的开口220,例如,可经由开口220接入。以这种方式,接合线(例如,接合线240)可以穿过开口220形成,以将第一半导体裸片230的接合垫235耦合到衬底205的背侧207上的衬底接合垫245(也个别地标识为245a和245b)。例如,第一接合线240a可通过第一开口220a将第一半导体裸片230的第一接合垫235a与衬底205的背侧207上的第一衬底接合垫245a耦合。类似地,第二接合线240b可通过第二开口220b将第一半导体裸片230的第二接合垫235b与衬底205的背侧207上的第二衬底接合垫245b耦合。以这种方式,第一半导体裸片230可以(通过粘合层)附接到衬底205,并通过穿过开口220的接合线240建立到衬底205的电连接。
尽管图2描绘了穿过一个开口(例如,第二开口220b)的一个接合线(例如,第二接合线240b)和穿过另一开口(例如,第一开口220a)的两个接合线(例如,第一接合线240a和邻近接合线),但本领域技术人员将容易理解,横截面图仅捕获潜在的许多此类接合线中的一或两者。换句话说,多个接合线(例如,三个、四个、十个、二十个、甚至更多个)可以穿过单个开口,使得第一半导体裸片230的多个接合垫可以耦合到衬底205的背侧207上的多个衬底接合垫。例如,第一开口220a可以是细长开口,并且第一半导体裸片230可以具有两列接合垫,其中第一列接合垫布置在细长开口的第一侧附近,并且第二列接合垫布置在细长开口的第二侧附近。此外,衬底205的背侧207可以具有对应的两列衬底接合垫,所述衬底接合垫布置在细长开口的每一侧旁边,使得穿过细长开口的多个接合线可以将第一半导体裸片230的个别接合垫耦合到衬底205的背侧207上的对应衬底接合垫。
第二半导体裸片250包含第一侧251(例如,有源侧,鉴于靠近第一侧251的第二半导体裸片的功能特征)和与第一侧251相对的第二侧252(例如,无源侧)。图2示出第二半导体裸片250布置成使第一侧251背对衬底205的前侧206。在一些实施例中,第二半导体裸片250的结构可与第一半导体裸片230相同。例如,第一半导体裸片230可以是第二半导体裸片250的主裸片,并且第二半导体裸片250可以是从裸片。第二半导体裸片250的第一侧251可包含各种导电结构,例如接合垫260(也个别地标识为260a-c)、再分布特征261(例如,配置成在接合垫260之间路由电信号的金属迹线)等。如图2所示,第二半导体裸片250中的每一者包含未被位于上方的第二半导体裸片250覆盖的暴露部分(例如,暴露部分255)。因而,第二半导体裸片250的至少一侧延伸超过位于上方的第二半导体裸片250的对应侧。第二半导体裸片250包含暴露部分255中的一或多个接合垫260(也个别地标识为260a和260b),使得一或多个接合线265可以将暴露部分255中的一或多个接合垫260耦合到衬底205的前侧206上的衬底接合垫245(也个别地标识为245c-e)。在一些情况下,至少一个衬底接合垫260可耦合到半导体裸片组合件200的接地节点。
此外,粘合层(未示出)可安置在最底部的第二半导体裸片与第一半导体裸片230之间,以将第二半导体裸片250附接到第一半导体裸片230。第二半导体裸片250通过接合线265(也个别地标识为265a-c)耦合到衬底205,例如,第二半导体裸片250的接合垫260(例如,接合垫260a、接合垫260b)通过接合线265耦合到衬底205的前侧206的衬底接合垫245(也个别地标识为245c-e)。以这种方式,第二半导体裸片250可以附接到第一半导体裸片230并建立到衬底205的电连接。
如上所述,第一半导体裸片230(例如,主裸片)可通过接合线240电连接到衬底205,并且第二半导体裸片250(例如,从裸片)可通过接合线265电连接到衬底205。衬底205可配置成例如通过衬底205的导电迹线操作地耦合第一半导体裸片230和第二半导体裸片250。因此,第一半导体裸片230通过一或多个接合线265结合第一接合线240a、第二接合线240b或两者与第二半导体裸片250操作地耦合。
此外,第一半导体裸片230、第二半导体裸片250和接合线265可通过衬底205的前侧206上的第一模塑件270包封。此外,组合件200可包含衬底205的背侧207上的第二模塑件275,其中第二模塑件275延伸至第一开口220a、第二开口220b或两者。另外,第二模塑件275可以包封第一接合线240a、第二接合线240b或两者。与包含带TSV的半导体裸片和/或例如参考图1描述的互连件180的直接芯片附接方案的半导体裸片组合件相比,组合件200可提供低成本的替代方案。此外,鉴于第一半导体裸片230的倒装芯片配置,组合件100可通过第一半导体裸片230提供合适的信号传输能力(例如,例如,关于行业标准规范,例如JEDEC)。
上文参考图2描述的半导体裸片组合件(例如,半导体裸片组合件200)可并入到大量更大和/或更复杂的系统中的任一个中,其代表性实例为图3中示意性示出的系统300。系统300可包含半导体裸片组合件370、电源372、驱动器374、处理器376,和/或其它子系统或组件378。半导体裸片组合件370可包含通常与上文描述的半导体裸片组合件相似的特征,因此可包含衬底,衬底的内部具有第一开口且外部具有第二开口。此外,半导体裸片组合件370可包含附接到衬底前侧的主裸片,其中主裸片包含靠近第一开口的第一接合垫和靠近第二开口的第二接合垫。主裸片的第一接合垫可使用延伸穿过第一开口的第一接合线与和前侧相对的衬底背侧上的第一衬底接合垫耦合。类似地,主裸片的第二接合垫可使用延伸穿过第二开口的第二接合线与衬底背侧的第二衬底接合垫耦合。
所得系统300可以执行多种功能中的任何一种,例如存储器存储、数据处理和/或其它合适的功能。因此,代表性系统300可包含但不限于手持装置(例如,移动电话、平板电脑、数字阅读器和数字音频播放器)、计算机和家用电器。系统300的组件可以封装在单个单元中,或者分布在多个互连单元上(例如,通过通信网络)。系统300的组件还可包含远程装置和各种计算机可读媒体中的任何一种。
图4是形成根据本发明技术的实施例配置的半导体裸片组合件的方法的流程图400。所述方法包含在包含前侧和与前侧相对的背侧的衬底中形成第一和第二开口,第一开口位于衬底的内部部分中,并且第二开口位于衬底的外部部分中(框410)。所述方法进一步包含将主裸片附接到衬底的前侧,其中主裸片包含朝向衬底的前侧的第一侧,主裸片的第一侧包含靠近第一开口的第一接合垫和靠近第二开口的第二接合垫(框415)。所述方法进一步包含形成穿过第一开口将主裸片的第一接合垫与衬底的背侧上的第一衬底接合垫耦合的第一接合线(框420)。所述方法进一步包含形成穿过第二开口将主裸片的第二接合垫与衬底的背侧上的第二衬底接合垫耦合的第二接合线(框425)。
在一些实施例中,所述方法可进一步包含将一或多个从裸片附接到主裸片,其中一或多个从裸片中的每一者包含带第三接合垫的暴露部分,以及附接将一或多个从裸片的一或多个第三接合垫与衬底的第一侧上的第三衬底接合垫耦合的一或多个第三接合线。在一些实施例中,所述方法可进一步包含在衬底的前侧上形成第一模塑件,第一模塑件包封主裸片和一或多个从裸片,并在衬底的背侧上形成第二模塑件,第二模塑件延伸至第一开口、第二开口或两者并包封第一接合线、第二接合线或两者。在一些实施例中,主裸片可通过一或多个第三接合线结合第一接合线、第二接合线或两者与一或多个从裸片操作地耦合。
综上所述,应了解,本文中已经出于说明的目的描述了本发明技术的具体实施例,但是可以在不偏离本公开的情况下进行各种修改。例如,尽管半导体裸片组合件的实施例描述为具有四(4)个半导体裸片(例如,一个主裸片和三个从裸片),但在其它实施例中,半导体裸片组合件可配置成具有不同数量(例如,两个、三个、五个、六个、八个甚至更多个)半导体裸片。此外,尽管半导体裸片组合件的实施例描述为从裸片以类似阶梯的图案布置,其中接合线耦合从裸片的接合垫与对应衬底接合垫,但本发明技术不限于此。例如,半导体裸片可按Z形图案布置,其中半导体裸片的至少一侧暴露以用于接合线形成,从而将从裸片的接合垫与对应衬底接合垫耦合。
此外,虽然在前述示例实施例中,已经描述并说明具有两个开口的衬底,但是在其它实施例中,衬底可以具有三个或更多个此类开口。另外,开口可形成于衬底中的任何地方(例如但不限于内部部分和外部部分)以提供对主裸片的接合垫的接入,使得接合线可形成为穿过开口将主裸片的接合垫耦合到衬底的对应衬底接合垫。另外,虽然在示出的实施例中某些特征或组件已经示出为具有某些布置或配置,但其它布置和配置是可能的。此外,在特定实施例的上下文中描述的本发明技术的某些方面还可在其它实施例中组合或去除。
本文中所论述的包含半导体装置(或裸片)的装置可形成在例如硅、锗、锗化硅合金、砷化镓、氮化镓等半导体衬底或裸片上。在一些状况下,衬底为半导体晶片。在其它状况下,衬底可为绝缘体上硅(SOI)衬底,例如玻璃上硅(SOG)或蓝宝石上硅(SOP),或另一衬底上的半导体材料的外延层。可通过使用包含但不限于磷、硼或砷的各种化学物质的掺杂来控制衬底或衬底的子区的导电性。可在衬底的初始形成或生长期间,通过离子植入或通过任何其它掺杂方法执行掺杂。
如本文中所使用,包含在权利要求书中,如在项列表(例如,后加例如“中的至少一个”或“中的一或多个”的短语的项列表)中所使用的“或”指示包含端点的列表,使得例如A、B或C中的至少一个的列表意指A或B或C或AB或AC或BC或ABC(即,A和B和C)。另外,如本文所用,短语“基于”不应理解为提及封闭条件集。例如,在不脱离本公开的范围的情况下,描述为“基于条件A”的示范性步骤可基于条件A和条件B两者。换句话说,如本文所用,短语“基于”应同样地解释为短语“至少部分地基于”。
从上文中将了解,本文中已经出于说明的目的描述了本发明的具体实施例,但是可以在不偏离本发明的精神和范围的情况下进行各种修改。相反,在以上描述中,论述了众多具体细节以提供对本发明技术的实施例的透彻及启发性描述。然而,相关领域的技术人员将认识到,可在并无具体细节中的一或多个的情况下实践本公开。在其它情况下,未展示或未详细地描述通常与存储器系统及装置相关联的众所周知的结构或操作,以避免混淆技术的其它方面。一般来说,应理解,除了本文公开的那些具体实施例之外的各种其它装置、系统和方法可在本发明技术的范围内。
Claims (20)
1.一种半导体裸片组合件,其包括:
衬底,其包含前侧和与所述前侧相对的背侧,其中所述衬底包含所述衬底的内部部分中的第一开口和所述衬底的外部部分中的第二开口;
主裸片,其附接到所述衬底的所述前侧,其中所述主裸片包含朝向所述衬底的所述前侧的第一侧,所述主裸片的所述第一侧包含靠近所述第一开口的第一接合垫和靠近所述第二开口的第二接合垫;
第一接合线,其穿过所述第一开口将所述主裸片的所述第一接合垫与所述衬底的所述背侧上的第一衬底接合垫耦合;以及
第二接合线,其穿过所述第二开口将所述主裸片的所述第二接合垫与所述衬底的所述背侧上的第二衬底接合垫耦合。
2.根据权利要求1所述的半导体裸片组合件,其进一步包括:
一或多个从裸片,其安置在所述主裸片上方,其中:
所述一或多个从裸片中的每一者包含暴露部分,所述暴露部分包含第三接合垫;以及
一或多个第三接合线,其将所述一或多个从裸片的一或多个第三接合垫与所述衬底的所述前侧上的第三衬底接合垫耦合。
3.根据权利要求2所述的半导体裸片组合件,其中所述主裸片通过所述一或多个第三接合线结合所述第一接合线、所述第二接合线或两者与所述一或多个从裸片操作地耦合。
4.根据权利要求2所述的半导体裸片组合件,其中所述第三衬底接合垫耦合到所述半导体裸片组合件的接地节点。
5.根据权利要求2所述的半导体裸片组合件,其进一步包括:
第一模塑件,其在所述衬底的所述前侧上,所述第一模塑件包封所述主裸片和所述一或多个从裸片;以及
第二模塑件,其在所述衬底的所述背侧上,所述第二模塑件延伸至所述第一开口、所述第二开口或两者,并包封所述第一接合线、所述第二接合线或两者。
6.根据权利要求2所述的半导体裸片组合件,其中所述主裸片在结构上与所述一或多个从裸片相同。
7.根据权利要求2所述的半导体裸片组合件,其中:
所述一或多个从裸片中的每一者包含有源侧和与所述有源侧相对的无源侧,并且
所述一或多个从裸片的所述有源侧背对所述衬底的所述前侧。
8.根据权利要求7所述的半导体裸片组合件,其进一步包括:
粘合层,其在所述主裸片的与所述第一侧相对的第二侧与所述一或多个从裸片中的最底部的从裸片的所述无源侧之间。
9.根据权利要求1所述的半导体裸片组合件,其进一步包括在所述衬底的所述背侧上的模塑件,其中:
所述模塑件延伸至所述第一开口、所述第二开口或两者;并且
所述模塑件包封所述第一接合线、所述第二接合线或两者。
10.根据权利要求1所述的半导体裸片组合件,其中所述第一开口和所述第二开口从所述第一侧延伸到所述第二侧。
11.一种半导体裸片组合件,其包括:
封装衬底,其包含前侧和与所述前侧相对的背侧,其中所述封装衬底包含所述封装衬底的中间部分中的第一开口和所述封装衬底的周边部分中的第二开口;
第一半导体裸片,其附接到所述封装衬底的所述前侧,其中所述第一半导体裸片包含朝向所述封装衬底的所述前侧的第一侧,所述第一半导体裸片的所述第一侧包含靠近所述第一开口的第一接合垫和靠近所述第二开口的第二接合垫;
第一接合线,其穿过所述第一开口将所述第一半导体裸片的所述第一接合垫与所述衬底的所述背侧上的第一衬底接合垫耦合;以及
第二接合线,其穿过所述第二开口将所述第一半导体裸片的所述第二接合垫与所述衬底的所述背侧上的第二衬底接合垫耦合。
12.根据权利要求11所述的半导体裸片组合件,其进一步包括:
第二半导体裸片,其附接到所述第一半导体裸片,其中所述第二半导体裸片包含背对所述第一半导体裸片的有源侧,所述第二半导体裸片的所述有源侧包含第三接合垫;以及
第三接合线,其将所述第二半导体裸片的所述第三接合垫与所述封装衬底的所述第一侧上的第三衬底接合垫耦合。
13.根据权利要求12所述的半导体裸片组合件,其中所述第一半导体裸片通过所述第三接合线结合所述第一接合线、所述第二接合线或两者与所述第二半导体裸片操作地耦合。
14.根据权利要求12所述的半导体裸片组合件,其进一步包括:
第三半导体裸片,其附接到所述第二半导体裸片,其中所述第三接合线进一步将所述第三衬底接合垫与所述第三半导体裸片的有源侧上的第四接合垫耦合。
15.根据权利要求11所述的半导体裸片组合件,其进一步包括:
模塑件,其在所述封装衬底的所述背侧上,所述模塑件包封所述第一接合线、所述第二接合线或两者。
16.根据权利要求11所述的半导体裸片组合件,其中所述第一半导体裸片在结构上与所述第二半导体裸片相同。
17.一种方法,其包括:
在包含前侧和与所述前侧相对的背侧的衬底中形成第一和第二开口,所述第一开口位于所述衬底的内部部分中,并且所述第二开口位于所述衬底的外部部分中;
将主裸片附接到所述衬底的所述前侧,其中所述主裸片包含朝向所述衬底的所述前侧的第一侧,所述主裸片的所述第一侧包含靠近所述第一开口的第一接合垫和靠近所述第二开口的第二接合垫;
形成穿过所述第一开口将所述主裸片的所述第一接合垫与所述衬底的所述背侧上的第一衬底接合垫耦合的第一接合线;以及
形成穿过所述第二开口将所述主裸片的所述第二接合垫与所述衬底的所述背侧上的第二衬底接合垫耦合的第二接合线。
18.根据权利要求17所述的方法,其进一步包括:
将一或多个从裸片附接到所述主裸片,其中所述一或多个从裸片中的每一者包含暴露部分,所述暴露部分包含第三接合垫;以及
附接一或多个第三接合线,其将所述一或多个从裸片的一或多个第三接合垫与所述衬底的所述第一侧上的第三衬底接合垫耦合。
19.根据权利要求18所述的方法,其进一步包括:
在所述衬底的所述前侧上形成第一模塑件,所述第一模塑件包封所述主裸片和所述一或多个从裸片;以及
在所述衬底的所述背侧上形成第二模塑件,所述第二模塑件延伸至所述第一开口、所述第二开口或两者,并包封所述第一接合线、所述第二接合线或两者。
20.根据权利要求18所述的方法,其中所述主裸片通过所述一或多个第三接合线结合所述第一接合线、所述第二接合线或两者与所述一或多个从裸片操作地耦合。
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US20110084374A1 (en) * | 2009-10-08 | 2011-04-14 | Jen-Chung Chen | Semiconductor package with sectioned bonding wire scheme |
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