CN103050515A - 晶体管及其制造方法 - Google Patents

晶体管及其制造方法 Download PDF

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CN103050515A
CN103050515A CN201210385506XA CN201210385506A CN103050515A CN 103050515 A CN103050515 A CN 103050515A CN 201210385506X A CN201210385506X A CN 201210385506XA CN 201210385506 A CN201210385506 A CN 201210385506A CN 103050515 A CN103050515 A CN 103050515A
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安藤崇志
J.B.常
S.K.卡纳卡萨巴帕西
P.库卡尼
T.E.斯坦达特
山下典洪
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GlobalFoundries Inc
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
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    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

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Abstract

本发明提供一种晶体管，例如，FinFET，该晶体管包括设置在基板之上的栅极结构。栅极结构具有宽度以及限定栅极结构的两个相对侧壁的长度和高度。晶体管还包括:至少一个导电沟道，设在源极区域和漏极区域之间且通过栅极结构的侧壁；电介质层，设置在栅极结构之上以及导电沟道的在栅极结构外侧的部分之上；以及气隙，设在电介质层下。气隙设置为相邻于栅极结构的侧壁且用于减小晶体管的寄生电容。本发明还公开了制造该晶体管的至少一种方法。

Description

晶体管及其制造方法
技术领域
本发明的示范性实施例总体上涉及场效晶体管（FET），更具体地，涉及诸如FinFET的多栅极FET和减小寄生电容的技术。
背景技术
根本上，FET是具有源极、栅极和漏极的晶体管。FET的运转取决于多数载流子沿着源极和漏极之间的沟道而通过栅极的流动。通过源极和漏极之间的沟道的电流由栅极下的横向电场控制。为了更加有效地控制沟道，可采用多于一个的栅极（多栅极）。栅极的长度决定了FET开关的快慢，并且可与沟道的长度（即源极和漏极之间的距离）大致相同。
通过采用一个或多个鳍状沟道，FET的尺寸已经得到成功减小。采用这样沟道结构的FET可称为FinFET。过去，互补金属氧化物半导体（CMOS）器件沿着半导体基板的表面实质上为平面的，例外的是FET栅极设置在沟道的顶部之上。为了最大化沟道暴露到栅极的表面面积，通过采用垂直沟道而使得鳍突破了该示例。栅极控制沟道更强，因为它延伸在沟道的多于一侧（表面）。例如，栅极可围绕三维沟道的三个表面，而不是设置为仅跨过传统平面沟道的顶表面。在某些器件中，栅极可完全围绕沟道，即，悬浮（suspended）沟道通过栅极且沟道的所有表面暴露到栅极。
与传统的平面FET相比，制造多栅极FET的一个挑战是固有的高寄生电容。例如，可参考X.Wang等人发表于Simulation of Semiconductor Processand Device,Vol.12,pages.125-128的"Simulation Study of Multiple FINFinFET Device Design for 32nm Technology Node and Beyond"以及C.R.Manoj等人发表于IEEE Electron Device Letters,Vol.31,p.83-85的"Impact ofFringe Capacitance on Performance of Nanoscale FinFET"。
发明内容
在本发明示范性实施例的一个方面中，提供一种晶体管，其包括设置在基板之上的栅极结构。该栅极结构具有宽度以及限定栅极结构的两个相对侧壁的长度和高度。该晶体管还包括：至少一个导电沟道，设在源极区域和漏极区域之间且通过栅极结构的侧壁；电介质层，设置在栅极结构以及导电沟道的在栅极结构外侧的部分之上；以及气隙，位于电介质层之下。气隙设置为相邻于栅极结构的侧壁。
在本发明示范性实施例的另一个方面中，提供一种制造晶体管的方法。该方法包括在基板之上形成位于源极区域和漏极区域之间的至少一个导电沟道，并且形成设置在至少一个导电沟道的一部分之上的栅极结构。栅极结构具有限定栅极结构的两个相对侧壁的宽度、长度和高度。栅极结构形成为使至少一个导电沟道通过栅极结构的侧壁。该方法还包括：在栅极结构的侧壁上形成间隔物；在至少一个导电沟道之上形成外延硅层；去除间隔物；以及形成设置在栅极结构之上以及导电沟道的在栅极结构外侧的部分之上的电介质层，使气隙位于电介质层之下。气隙设置为在间隔物先前占据的区域中相邻于栅极结构的侧壁。
在本发明示范性实施例的另一个方面中，提供了在多栅极场效晶体管中减小寄生电容的方法。该方法包括：在源极区域和漏极区域之间制造多个鳍；制造栅极结构使多个鳍通过栅极结构的侧壁；以及在电介质材料层中包封多栅极场效晶体管的至少部分，使气隙形成为相邻于栅极结构的侧壁且在电介质材料层之下。
附图说明
图1A-1G，共同称为图1，示出了制造FinFET器件的一个示范性工序的概图（侧壁成像转移）；其中
图1A示出了绝缘体上硅（SOI）层上形成的SiO2层上的多晶硅（多晶Si）芯棒（mandrel）的定义；
图1B示出了SIT节距加倍的结果，其中芯棒的侧壁具有SiN层形成于其上；
图1C示出了蚀刻操作和芯棒去除的结果以及所形成的鳍（没有示出SOI晶片的下层BOX（埋设氧化物）和基板）；
图1D示出了栅极堆叠沉积和平坦化、硬掩模沉积、栅极光刻以及反应离子蚀刻的结果；
图1E示出了SiN偏移间隔物（offset spacer）形成（后面是延伸注入）的结果；
图1F示出了外延硅生长的结果，其提供覆盖鳍的外延Si层；以及
图1G示出了后面是S/D注入和快速热退火的偏移间隔物去除以及最终间隔物形成的结果。
图2A-2H，共同称为图2，示出了制造FinFET器件的另一个示范性方法，其中
图2A示出了基板和多晶硅结构上形成的硬掩模层；
图2B示出了氮化硅（SiN）结构沿着多晶硅结构的侧面形成；
图2C示出了蚀刻形成鳍结构的结果；
图2D示出了附加蚀刻以及垂直于鳍结构的栅极堆叠和SiN层形成的结果；
图2E示出了示出了去除硬掩模层和SiN层的一部分以及沿着栅极堆叠形成SiN间隔物的结果；
图2F示出了鳍结构上沉积的外延硅（外延Si）层；
图2G示出了形成源极和漏极区域的有角离子注入程序的截面图；以及
图2H示出了外延Si层上和栅极堆叠之上形成的硅化物层。
图3A示出了通过图1的示范性工艺或图2的示范性工艺形成的FinFET器件的截面图；
图3B示出了根据本发明实施例进一步处理的结果，其中去除了相邻于栅极结构的侧壁的SiN间隔物；以及
图3C示出了沉积层间电介质层以实质上均匀地覆盖FinFET结构并且在图3B中去除SiN间隔物的位置形成与栅极结构的侧壁相邻设置的下层气隙的结果。
具体实施方式
下面，在FinFET的上下文中描述本发明的示范性实施例。图1A-1G提供了一个示范性技术的总图，以制造根据共同转让的Chung-Hsun Lin和Josephine B.Chang的名称为“Recessed Contact for Multi-Gate FET OptimizingSeries Resistance”的美国专利申请公开US 2011/0049583 A1中示出的实施例的FinFET。图2A-2H提供了另一个示范性技术的总图，以制造根据共同转让的Josephine B.Chang、Leland Chang、Chung-Hsun Lin和Jeffery W.Sleight的名称为“Asymmetric FINFET Device with Improved ParasiticResistance and Capacitance”的美国专利申请公开US 2011/0065244 A1中示出的实施例的FinFET。
图1A-1G呈现在侧壁图像转移（SIT）制造技术的示范性上下文中，其采用间隔物作为硬掩模以限定鳍（fin）。然而，这仅是一个合适的FinFET制造技术，在使用和实施本发明时不应以限制的意思来解释。通常，本发明的示范性实施例可采用或不采用硬掩模。而且，示范性实施例可采用绝缘体上硅（SOI）基板或者它们可采用体基板。
图1A示出了绝缘体上硅（SOI）层1（没有示出SOI晶片的下层埋设氧化物（BOX）和基板）上形成的SiO2层2上的多晶硅（多晶Si）芯棒3的定义。图1B示出了SIT节距加倍的结果，其中芯棒3的侧壁具有SiN层4形成于其上。图1C示出了蚀刻操作和芯棒去除的结果以及所形成的鳍5（没有示出SOI晶片的下层BOX（埋设）和基板）。每个鳍5都是多层结构，由Si下层（其形成完成的FinFET的沟道）、SiO2中间层和SiN上层（其在执行图1D所示的操作前去除）组成。图1D示出了栅极堆叠沉积和平坦化、硬掩模沉积、栅极光刻和反应离子蚀刻（RIE）的结果。所形成的栅极堆叠6例如包括多晶Si栅极和上覆SiN层7。图1E示出了后面是延伸注入的SiN偏移间隔物8形成的结果。图1F示出了外延硅（外延Si）生长的结果，其提供覆盖鳍5因此与鳍合并的外延Si层9。图1G示出了后面是S/D注入和快速热退火（RTA）的偏移间隔物去除及最终间隔物形成的结果。所形成的FinFET器件20包括硅化物层10，位于栅极堆叠6的顶部之上和鳍外延Si之上。通常，图1D-1G示出了图1C的转换成S/D的暴露鳍5。硅化物层10的厚度可为约5nm至约30nm（或更厚）的范围。在某些实施例中，硅化物层10可具有约10nm的常规厚度。硅化物层10可由任何适当的硅化物，例如硅化钴（CoSi2）、硅化镍（NiSi）或硅化铂（PtSi、Pt2Si），组成，作为非限定性示例。
图2A-2H示出了制造FinFET器件100的另一个示范性方法。参见图2A，二氧化硅（SiO2）（或氮化硅（SiN））硬掩模层104形成在基板上。在所示的实施例中，基板可为绝缘体上硅（SOI）层111。在其它实施例中，基板可为体基板。多晶硅结构204通过沉积和蚀刻工艺形成在硬掩模层104上。参见图2B，氮化硅（SiN）结构206采用沉积和蚀刻工艺形成为沿着多晶硅结构204的侧面。在图2C中，多晶硅结构204以及硬掩模层104和SOI层111的部分被蚀刻以形成鳍结构208。所示的两个鳍结构208是示范性的，因为可形成多于两个或少于两个的鳍结构。在图2D中，蚀刻SiN结构206，并且栅极堆叠部分102和SiN层210形成为垂直于鳍结构208。参见图2E，去除硬掩模层104和SiN层210的部分，并且SiN间隔物106形成为沿着栅极堆叠部分102。在图2F中，外延硅（外延Si）层214沉积在剩余的鳍结构205之上，用以并入鳍结构。图2G示出了离子注入的截面图，其在SOI层111中形成源极区域108和漏极区域110。在所示的非限定性实施例中，离子203以关于垂直于源极区域108的线的角度（θ）注入。栅极堆叠部分102和间隔物106部分地阻挡一部分离子203不以很大的浓度沉积在SOI层111的部分212中，并且以倾斜角度（θ）的注入导致重叠的源极区域108和偏移的漏极区域110。注入角度的范围可为0-90度，以及0-90度之间的任何另外的角度。在所示的实施例中示出了20-30度的示范性注入角度。参见图2H，硅化物层216形成在外延Si层214上以及栅极堆叠部分102之上。
图3A示出了由图1的示范性工艺或图2的示范性工艺形成的FinFET器件的截面图。栅极堆叠6或102示出为分别设置在SiN间隔物8或106之间。实际上，在形成SiN间隔物8或106时，它们显示为总体上锥形的上部外形，其中厚度朝着间隔物的顶部逐渐减小。源极（S）和漏极（D）注入300、302可位于下层SOI或体基板材料中。
图3B示出了根据本发明实施例进一步处理的结果，其中去除了SiN间隔物8或106。这可由例如通过采用热磷酸的湿化学蚀刻工艺实现。
图3C示出了沉积层间电介质（ILD）层的结果，其例如为SiN盖层310。可见，SiN盖层310实质上均匀地涂敷FinFET 20或100的结构。然而，根据本发明的实施例，在图3B中SiN间隔物8或106被去除的区域中，夹断（pinch-off）区域312形成为靠近顶部，留下相邻于栅极堆叠6或102的侧壁设置的下层气隙314。气隙314沿着栅极堆叠的侧壁实质上为连续的，除了鳍5或205从硅化物部分10或216延伸进入栅极堆叠6或102的位置外。
在非限定性实施例中，初始SiN间隔物8或106的厚度范围可为约5nm至约10nm，于是变为接近气隙314的宽度。SiN盖层可采用相对低温（例如，约350℃）等离子体增强化学气相沉积（PECVD）工艺沉积。采用低温（~350℃）PECVD工艺的Si3N4是一种适当工艺的非限定性示例，以形成盖层而产生气隙314。
空气的介电常数与约7-7.5的SiN的介电常数相比为大致一致。因此，由气隙314形成的所得间隔物通过减小栅极和源极/漏极之间，即分别在图1和2的示范性FinFET实施例20或100的栅极堆叠6或102与鳍5或205之间的寄生电容而提供增强的电性能。
通常，根据本发明实施例的FinFET 20或100可实施为N型器件或P型器件。栅极堆叠可采用多晶Si或金属制造，可采用任何适当的栅极电介质材料，并且硅化物层可由任何适当类型的硅化物组成。FinFET 20或100可构造为具有通过栅极堆叠宽度的单鳍或沟道结构，或者可有通过栅极堆叠宽度的两个或多个鳍或沟道结构。显然，本发明的示范性实施例应用于多栅极晶体管。另外，应理解的是，本发明的示范性实施例还应用于配线型晶体管，其中沟道结构通过栅极堆叠的宽度，使沟道结构的所有表面（即顶表面、两侧表面和底表面）相邻于栅极堆叠或由其围绕，并且可受到栅极堆叠的电影响。在该实施例中，可有通过栅极堆叠宽度的任何数量的配线型沟道结构。应理解的是，FinFET 20或100，或者更通常的晶体管20或100，不应解释为限于或仅仅为上述的示范性的几何形状、材料、电介质膜、制造工艺、尺寸和/或层厚度。
因此，结合附图和所附权利要求阅读时，考虑到前面的描述，相关技术领域的技术人员可显而易见地进行特种修改和变化。然而，本发明教导的所有这样的和类似的修改仍将落入本发明的范围。

Claims (20)

1.一种晶体管，包括：
栅极结构，设置在基板之上，所述栅极结构具有宽度以及限定所述栅极结构的两个相对侧壁的长度和高度；
至少一个导电沟道，形成在源极区域和漏极区域之间且通过所述栅极结构的所述侧壁；
电介质层，设置在所述栅极结构上及所述导电沟道的在所述栅极结构外侧的部分之上；以及
气隙，在所述电介质层之下，所述气隙设置为相邻于所述栅极结构的所述侧壁。
2.根据权利要求1所述的晶体管，其中所述气隙的宽度为约5nm至约10nm。
3.根据权利要求2所述的晶体管，其中所述气隙从所述气隙的相邻于所述基板的底部到由所述电介质层的桥接所述气隙的顶部的下表面限定的夹断区域实质上为连续的。
4.根据权利要求1所述的晶体管，其中所述电介质层由SiN或Si3N4组成。
5.根据权利要求1所述的晶体管，其中并非所述至少一个导电沟道的所有表面都受到所述栅极结构的电影响。
6.根据权利要求1所述的晶体管，其中所述至少一个导电沟道的所有表面受到所述栅极结构的电影响。
7.一种制造晶体管的方法，包括：
在基板之上形成在源极区域和漏极区域之间的至少一个导电沟道；
形成栅极结构，以设置在所述至少一个导电沟道的一部分之上，所述栅极结构具有宽度和限定所述栅极结构的两个相对侧壁的长度和高度，并且所述栅极结构形成为使得所述至少一个导电沟道通过所述栅极结构的所述侧壁；
在所述栅极结构的所述侧壁上形成间隔物；
在所述至少一个导电沟道之上形成外延硅层；
去除所述间隔物；以及
形成电介质层，以设置在所述栅极结构上以及所述导电沟道的在所述栅极结构外侧的部分之上，从而气隙位于所述电介质层之下，所述气隙设置为在由所述间隔物原来占据的区域中相邻于所述栅极结构的所述侧壁。
8.根据权利要求7所述的方法，其中所述气隙的宽度为约5nm至约10nm。
9.根据权利要求8所述的方法，其中所述气隙从所述气隙的相邻于所述基板的底部到由所述电介质层的桥接所述气隙的顶部的下表面限定的夹断区域实质上为连续的。
10.根据权利要求7所述的方法，其中形成所述电介质层为沉积由SiN或Si3N4组成的层。
11.根据权利要求10所述的方法，其中沉积所述由SiN或Si3N4组成的层采用等离子体增强化学气相沉积工艺实现。
12.根据权利要求11所述的方法，其中所述等离子体增强化学气相沉积工艺在约350℃的温度执行。
13.根据权利要求7所述的方法，其中去除所述间隔物采用湿化学蚀刻工艺实现。
14.根据权利要求7所述的方法，其中并非所述至少一个导电沟道的所有表面都受到所述栅极结构的电影响。
15.根据权利要求7所述的方法，其中所述至少一个导电沟道的所有表面受到所述栅极结构的电影响。
16.一种减小多栅极场效晶体管中的寄生电容的方法，包括：
在源极区域和漏极区域之间制造多个鳍；
制造栅极结构，使所述多个鳍通过所述栅极结构的侧壁；以及
在电介质材料层中包封所述多栅极场效晶体管的至少一部分，使得气隙形成为相邻于所述栅极结构的所述侧壁且在所述电介质材料层之下。
17.根据权利要求16所述的方法，其中包封包括从所述栅极结构的所述侧壁去除间隔物的开始步骤，其中该气隙形成在被去除所述间隔物的区域中。
18.根据权利要求17所述的方法，其中所述间隔物的厚度为约5nm至约10nm，并且其中包封包括采用等离子增强体化学气相沉积工艺沉积由SiN或Si3N4组成的层，该等离子增强体化学气相沉积工艺在约350℃的温度执行。
19.根据权利要求17所述的方法，其中所述间隔物采用湿化学蚀刻工艺去除。
20.根据权利要求16所述的方法，其中所述多栅极场效晶体管是FinFET。
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