CN106898597A - 半导体结构及其制造方法 - Google Patents
半导体结构及其制造方法 Download PDFInfo
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- CN106898597A CN106898597A CN201611066804.7A CN201611066804A CN106898597A CN 106898597 A CN106898597 A CN 106898597A CN 201611066804 A CN201611066804 A CN 201611066804A CN 106898597 A CN106898597 A CN 106898597A
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- conductive plunger
- opening
- layer
- dielectric layer
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Classifications
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- H01L29/41725—Source or drain electrodes for field effect devices
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- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
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Abstract
本发明的实施例提供了半导体结构及其制造方法。半导体结构包括衬底、至少一个第一栅极结构、至少一个第一间隔件、至少一个源漏结构和导电插塞。所述第一栅极结构位于所述衬底上。所述第一间隔件位于所述第一栅极结构的至少一个侧壁上。所述源漏结构邻近所述第一间隔件。所述导电插塞电连接至所述源漏结构,同时在所述导电插塞和所述第一间隔件之间留有间隙。
Description
技术领域
本发明的实施例总体涉及半导体领域,更具体地,涉及半导体结构及其制造方法。
背景技术
半导体器件用于各种电子应用,例如,诸如个人电脑、手机、数码相机和其他电子设备。通过不断减小最小特征尺寸,半导体工业持续提高各种电子部件(例如,晶体管、二极管、电阻器、电容器等)的集成度,这使得更多部件集成到给定区域中。
集成电路中的“互连件”是指连接各种电子部件的导线。除在接触区域上以外,互连导线通过绝缘层与衬底分开。随着部件密度的增大,互连结构的导线的宽度以及导线之间的间隔也按比例变小了。
发明内容
根据本发明的一个方面,提供了一种半导体结构,包括:衬底;至少一个第一栅极结构,位于所述衬底上;至少一个第一间隔件,位于所述第一栅极结构的至少一个侧壁上;至少一个源漏结构,邻近于所述第一间隔件;以及导电插塞,电连接至所述源漏结构,同时在所述导电插塞与所述第一间隔件之间留下间隙。
根据本发明的另一方面,提供了一种半导体结构,包括:衬底;至少一个栅极结构,位于所述衬底上;至少一个源漏结构,位于所述衬底上;至少一个介电层,至少位于所述栅极结构上,并且所述至少一个介电层中具有开口,其中,所述源漏结构通过所述开口露出;以及导电插塞,至少通过所述开口电连接至所述源漏结构,同时所述导电插塞和所述开口的至少一个侧壁之间留下间隙。
根据本发明的又一方面,提供了一种制造半导体结构的方法,所述方法包括:在至少一个栅极结构和至少一个源漏结构上形成介电层;在所述介电层中形成开口以露出所述源漏结构;在所述开口的至少一个侧壁上形成保护层;在所述开口中形成导电插塞,其中,所述导电插塞电连接至所述源漏结构;以及在形成所述导电插塞后,去除所述保护层。
附图说明
当结合附图进行阅读时,根据下面详细的描述可以最佳地理解本发明的各个方面。应该注意,根据工业中的标准实践,各种部件没有被按比例绘制。实际上,为了清楚的讨论,各种部件的尺寸可以被任意增加或减少。
图1至图8是根据本发明的一些实施例的在各个阶段的制造半导体器件的方法的截面图。
具体实施方式
以下公开内容提供了许多不同实施例或实例,用于实现所提供主题的不同特征。下面将描述元件和布置的特定实例以简化本发明。当然这些仅仅是实例并不旨在限定本发明。例如,在以下描述中,在第二部件上方或上形成第一部件可以包括第一部件和第二部件直接接触的实施例,也可以包括形成在第一部件和第二部件之间的附加部件使得第一部件和第二部件不直接接触的实施例。而且,本发明在各个实例中可以重复参考数字和/或字母。这种重复仅是为了简明和清楚,其自身并不表示所论述的各个实施例和/或配置之间的关系。
此外,为便于描述,空间相对术语如“在...之下”、“在...下方”、“下部”、“在...之上”、“上部”等在本文可用于描述附图中示出的一个元件或部件与另一个(或另一些)元件或部件的关系。空间相对术语旨在包括除了附图中所示的方位之外,在使用中或操作中的器件的不同方位。装置可以其他方式定向(旋转90度或在其他方位上),本文使用的空间相对描述符可同样地作相应解释。
除非上下文清楚地表明,否则单数“一”,“一个”和“该”旨在也包括复数形式。应当进一步理解,当在本发明中使用术语“包括”和/或“包含”,或“包括”和/或“包括”或“具有”和/或“有”时,指定阐述的部件、区域、整数、步骤、操作、元件、和/或组件的存在,但不排除附加的一个或多个其他部件、区域、整数、步骤、操作、元件、组件和/或它们的组的存在。
应当理解,当将一个元件称为位于另一元件“上”时,该元件可以直接位于另一元件上或者在该元件和另一元件之间可以存在插入的元件。相反,当将一个元件称为直接位于另一元件“上”时,则不存在插入元件。如本文中所使用的,术语“和/或”包括一个或多个所列举的相关物质的任何和所有组合。
除非另有规定,本文使用的所有术语(包括技术术语和科学术语)具有如本发明所属领域的普通技术人员通常理解的相同的含义。还应该理解,诸如常用字典定义的那些术语应该解释为具有与它们在相关领域和本发明的上下文中的含义一致的含义,而不应该解释为理想化的或过于正式的含义,除非本文明确地加以定义。
图1至图8是根据本发明的一些实施例的制造半导体器件的方法在不同阶段的截面图。
参考图1。形成半导体结构。该半导体结构包括衬底110、栅极结构121和123和至少一个源漏(source drain)结构130。栅极结构121和123分别存在于衬底110上。源漏结构130存在于衬底110上且邻近于栅极结构121和123。换言之,源漏结构130存在于栅极结构121和123之间。应该注意,栅极结构121和123的数量和源漏结构130的数量是说明性的,但不应该限制本发明的各个实施例。本领域的技术人员可以根据实际情况来选择合适数量的栅极结构121和123和源漏结构130。
在一些实施例中,衬底110可由半导体材料制成,并且其中可包括诸如渐变层或埋入氧化物。在一些实施例中,衬底110包括可以未掺杂或掺杂(例如,p型、n型或它们的组合)的块状硅。可以使用适于形成半导体器件的其他材料。例如,锗、石英、蓝宝石和玻璃可选择用于衬底110。可选地,衬底110可以是绝缘体上半导体(SOI)衬底或多层结构中的有源层,诸如形成在块状硅层上的硅锗层。
在一些实施例中,栅极介电层、扩散阻挡层、金属层、阻挡层、润湿层和填充金属的至少一个叠层形成栅极结构121和123中的至少一个。换言之,栅极结构121和123中的至少一个可以包括栅极介电层、扩散阻挡层、金属层、阻挡层、润湿层和填充金属的叠层。
在一些实施例中,栅极介电层包括为介电层的界面层(IL,栅极介电层的下部)。在一些实施例中,IL包括诸如氧化硅层的氧化物层,该氧化物层可以对通过衬底110的热氧化、化学氧化或沉积步骤形成。栅极介电层还可以包括高k介电层(栅极介电层的上部),高k介电层包括高k介电材料,诸如氧化铪、氧化镧、氧化铝或它们的组合。高k介电材料的介电常数(k值)高于约3.9,并且可以高于约7,并且有时高达约21或更高。高k介电层位于IL上方并且可以与IL接触。
在一些实施例中,扩散阻挡层包括TiN、TaN或它们的组合。例如,扩散阻挡层可以包括TiN层(扩散阻挡层的下部)和在TiN层上方的TaN层(扩散阻挡层的上部)。
当栅极结构121和123中的一个形成n型金属氧化物半导体(MOS)器件时,金属层与扩散阻挡层接触。例如,在扩散阻挡层包括TiN层和TaN层的实施例中,金属层可以与TaN层物理接触。在栅极结构121和123中的一个形成p型MOS器件的可选实施例中,附加的TiN层形成在TaN层(在扩散阻挡层中)和覆盖金属层之间,并且与TaN层和覆盖金属层接触。附加的TiN层为pMOS器件提供了合适的功函,其功函高于中间禁带的功函(约4.5电子伏特),该中间禁带的功函在价带的中间和硅的导带中。比中间禁带的功函高的功函被称为p功函,并且具有p功函的各个金属被称为p金属。
金属层为nMOS器件提供合适的功函,该功函比中间禁带的功函低。比中间禁带的功函低的功函被称为n功函,并且具有n功函的相应金属可被称为n金属。在一些实施例中,金属层是功函低于约4.3电子伏特的n金属。金属层的功函也可以在约3.8电子伏特至约4.6电子伏特的范围内。根据一些实施例,金属层可包括铝钛(TiAl)(其可以包括、不含或基本上不含其它元素)。金属层的形成可通过物理汽相沉积(PVD)来实现。根据本发明的一些实施例,金属层在室温下(例如,从约20℃到约25℃)形成。在可选实施例中,在比室温高的升高温度下(例如,高于约200℃)形成金属层。
在一些实施例中,阻挡层可包括TiN。阻挡层可通过原子层沉积(ALD)而形成。
润湿层具有粘附(和润湿)在随后的填充金属的回流期间形成的填充金属的能力。在一些实施例中,润湿层是钴层,可用原子层沉积(ALD)或化学汽相沉积(CVD)来形成润湿层。
填充金属可包括铝、铝合金(例如,铝钛)、钨、或铜,也可用物理汽相沉积(PVD)、化学汽相沉积(CVD)等形成填充金属。可以回流填充金属。润湿层的形成改善了填充金属对下面各层的润湿。
源漏结构130可通过将杂质掺杂至至少一个有源半导体鳍中形成,例如利用光刻技术通过图案化和蚀刻衬底110来形成有源半导体鳍。在所得的MOS器件为nMOS器件的一些实施例中,诸如磷或砷的n型杂质可掺杂在源漏结构130中。在所得的MOS器件是pMOS器件的其他一些实施例中,可在源漏结构130中掺杂诸如硼或BF2的p型杂质。
可选地,源漏结构130可通过例如外延生长来形成。在这些实施例中,源漏结构130可用作源漏应力源,以增强半导体器件的载流子迁移率和器件性能。源漏结构130可用循环沉积和蚀刻(CDE)工艺来形成。CDE工艺包括外延沉积/部分蚀刻工艺,并且重复外延沉积/部分蚀刻工艺至少一次。
在所得的MOS器件为nMOS器件的一些实施例中,源漏结构130可以是n型外延结构。在所得的MOS器件是pMOS器件的一些实施例中,源漏结构130可以是p型外延结构。n型外延结构可以由SIP、SiC、SiPC、Si、III-V族化合物半导体材料或它们的组合制成,而p型外延结构可由SiGe、SiGeC、Ge、Si、III-V族化合物半导体材料或它们的组合制成。在形成n型外延结构期间,诸如磷或砷的n型杂质可在外延进程中掺杂。例如,当n型外延结构包括SiP或SiC时,掺杂n型杂质。此外,在形成p型外延结构期间,诸如硼或BF2的p型杂质可在外延进程中掺杂。例如,当p型外延结构包括SiGe时,掺杂p型杂质。外延工艺包括CVD沉积技术(例如,汽相外延(VPE)和/或超高真空CVD(UHV-CVD))、分子束外延和/或其它合适工艺。源漏结构130可以原位掺杂。如果源漏结构130没有原位掺杂,执行第二注入工艺(即,结注入工艺)以掺杂源漏结构130。可以执行一次或多次退火工艺以活化源漏结构130。该退火工艺包括快速热退火(RTA)和/或激光退火工艺。
此外,间隔件141存在于栅极结构121的侧壁上,并且间隔件143存在于栅极结构123的侧壁上。在一些实施例中,间隔物140和143中的至少一个包括一个或多个层(包括氮化硅、氮氧化硅、氧化硅或其它介电材料)。可用的形成方法包括等离子增强化学汽相沉积(PECVD)、低压化学汽相沉积(LPCVD)、次大气压化学汽相沉积(SACVD)和其他沉积方法。
此外,硬掩模层145存在于栅极结构121的顶表面,而硬掩模层147存在于栅极结构123的顶表面。例如,硬掩模层145和147可以包括氮化硅等。硬掩模层145和147可以用化学汽相沉积(CVD)、物理汽相沉积(PVD)、原子层沉积(ALD)、其它合适的工艺或它们的组合来形成。
然后,在栅极结构121和123以及源漏结构130上形成介电层150。介电层150是层间介电(ILD)层。介电层150由诸如氧化硅、氮化硅、氮氧化硅或它们的组合的介电材料制成。在一些实施例中,介电层150由低k介电材料制成,以改善电阻-电容(RC)延迟。低k介电材料的介电常数小于二氧化硅(SiO2)的介电常数。一种降低介电材料的介电常数的方法是引入碳(C)或氟(F)原子。例如,在SiO2(k=3.9)中,引入C原子以形成氢化的掺碳的氧化硅(SiCOH)(k介于2.7和3.3之间),或引入F原子以形成氟硅酸盐玻璃(FSG)(k介于3.5和3.9之间)减小了SiO2的介电常数。在一些实施例中,例如,低k介电材料是掺杂纳米孔碳的氧化物(CDO)、黑金刚石(BD)、苯并环丁烯(BCB)基聚合物、芳香族(烃)热固性聚合物(ATP)、氢倍半硅氧烷(HSQ)、甲基倍半硅氧烷(MSQ)、聚亚芳基醚(PAE)、掺氮的类金刚石碳(DLC)或它们的组合。例如,介电层150由化学汽相沉积(CVD)、旋涂或它们的组合形成。
参考图2。在介电层150中形成开口151,以露出源漏结构130和间隔件141和143的至少一个的至少一部分。通过光刻和蚀刻工艺形成开口151。光刻和蚀刻工艺包括应用光刻胶、曝光、显影、蚀刻和去除光刻胶。例如,通过旋涂在介电层150上施加光刻胶。然后预烘烤光刻胶以去除过量的光刻胶溶剂。在预烘烤后,将光刻胶暴露于强光的图案。
例如,强光是具有约436纳米波长的G线、具有约365纳米波长的I线、具有约248纳米波长的氟化氪(KrF)准分子激光、具有约193纳米波长的氟化物(ARF)准分子激光、具有约157纳米波长的氟化物(F2)准分子激光或它们的组合。在曝光期间,可用折射率大于1的液体介质填充曝光工具的最后透镜与光刻胶的表面之间的间隔,以增强光刻的分辨率。曝光引起化学变化,使得光刻胶的一些溶解于显影剂。
然后,在显影之前可以实施曝光后烘烤(PEB)以有助于减少由入射光的相消和相长干涉图案而造成的驻波现象。然后将显影剂施加至光刻胶上以去除光刻胶中可溶解于显影剂中的部分。然后,硬烘烤剩余的光刻胶以固化剩余的光刻胶。
蚀刻介电层150的未被剩余的光刻胶保护的部分以形成开口151。介电层150的蚀刻可以是干刻蚀,如反应离子蚀刻(RIE)、等离子体增强(PE)蚀刻或电感应耦合等离子体(ICP)蚀刻。在一些实施例中,当介电层150由氧化硅制成时,可以用氟基RIE来形成开口151。例如,用于干蚀刻介电层150的气体蚀刻剂是CF4/O2。
在形成开口151之后,通过诸如等离子灰化、剥离或它们的组合从介电层150处去除光刻胶。等离子体灰化使用等离子体源以产生诸如氧或氟的单原子活性物质。活性物质与光刻胶结合以形成灰,使用真空泵去除灰。剥离使用诸如丙酮或苯酚(phenol)溶剂的光刻胶剥离剂,以从介电层150处去除光刻胶。
参考图3。保护层160形成在介电层150的顶表面上、开口151的至少一个侧壁上(即,介电层150的至少一个侧壁和露出的间隔件141和143的至少一部分)和露出的源漏结构130上。例如,保护层160可包括氮化硅、氧化硅、氮氧化硅等。使用原子层沉积(ALD)、其它合适工艺或它们的组合形成保护层160。
如图4所示,执行各向异性蚀刻以去除在介电层150和露出的源漏结构130的顶表面上的保护层160同时保护层160仍覆盖开口151的侧壁(即,介电层150和间隔件141和143的侧壁)。因此,源漏结构130从保护层160露出。在一些实施例中,各向异性蚀刻可以是干刻蚀,如反应离子蚀刻(RIE)、等离子体增强(PE)蚀刻或电感应耦合等离子体(ICP)蚀刻。
在图5中,导电层170过填充开口151,然后去除在开口151外面的过量的导电层170。导电层170由金属(如铜(Cu)、铝(Al)、钨(W)、镍(Ni)、钴(Co)、钛(Ti)、铂(Pt)、钽(Ta)或它们的组合)制成。例如,通过电化学沉积、物理汽相沉积(PVD)、化学汽相沉积(CVD)或它们的组合形成导电层170。
然后,通过去除工艺来去除在开口151外面的过量的导电层170。在一些实施例中,例如,通过化学机械抛光(CMP)工艺来去除过载(over load)的导电材料170。在一些实施例中,当导电层170由铜(Cu)制成时,CMP浆料由诸如悬浮研磨颗粒、氧化剂和腐蚀抑制剂的混合物制成,并且CMP浆料是酸性的。在CMP工艺之后,在开口151中形成导电插塞171(导电层170)。导电插塞171电连接至源漏结构130。
参考图6。然后,回蚀介电层150以露出保护层160的至少一部分。介电层150的蚀刻可以是干刻蚀,如反应离子蚀刻(RIE)、等离子体增强(PE)蚀刻或电感应耦合等离子体(ICP)蚀刻。在一些实施例中,当介电层150由氧化硅制成时,可以用氟基RIE来回蚀介电层150。例如,用于干蚀刻介电层150的气体蚀刻剂是CF4/O2。
然后如图6和图7所示,去除保护层160,使得间隙191存在于导电插塞171与开口151的至少一个侧壁(即,介电层150的侧壁,间隔件141和143的侧壁)之间。在一些实施例中,可以执行选择性湿蚀刻工艺以去除保护层160,其中,选择性湿蚀刻工艺是化学蚀刻工艺。湿蚀刻溶液包括热磷酸溶液。湿蚀刻工艺具有可以调节的蚀刻参数,诸如所使用的蚀刻剂、蚀刻温度、蚀刻溶液浓度、蚀刻压力、蚀刻剂流率和其他合适的参数。
参考图7。在介电层150和导电插塞171上形成至少一个停止层180,使得介电层150和导电插塞171被停止层180覆盖。例如,停止层180可包括氮氧化硅、碳化硅、氮氧碳化硅、氮化硅或掺杂碳的氮化硅等。可以使用化学汽相沉积(CVD)、物理汽相沉积(PVD)、原子层沉积(ALD)、其它合适工艺或它们的组合来形成停止层180。
在本发明另一个方面,提供了半导体结构100。半导体结构100包括衬底110、栅极结构121和123、间隔件141和143、源漏结构130和导电插塞171。栅极结构121和123存在于衬底110上。间隔件141存在于栅极结构121的至少一个侧壁上,间隔件143存在于栅极结构123的至少一个侧壁上。源漏结构130邻近间隔件141和143,并且源漏结构130存在于间隔件141和143之间。导电插塞171电连接到源漏结构130,同时在导电插塞171和间隔件141之间以及导电插塞171和间隔件143之间保留间隙191。
半导体结构100还包括介电层150。介电层150存在于栅极结构121和123的至少一个上,并且在其中具有开口151。源漏结构130通过开口151露出,并且导电插塞171的至少一部分存在于开口151中。导电插塞171至少通过开口151电连接至源漏结构130,同时在导电插塞171和开口151的至少一个侧壁之间保留间隙191。
半导体结构100还包括在栅极结构121的顶表面上的掩模层145,以及在栅极结构123的顶表面上的硬掩模层147。换言之,硬掩膜层145存在于栅极结构121和介电层150之间,并且硬掩膜层147存在于栅极结构123和介电层150之间。
此外,间隔件141和143的至少一部分通过开口151露出,同时间隙191还存在于导电插塞171和间隔件141的部分之间以及导电插塞171和间隔件143的部分之间。
间隙191中可具有气体。换言之,间隙191可以是气体填充。本发明的实施例不限制于此。根据实际应用,本领域的普通技术人员可以对间隙191做出适当的修改。
具体地,导电插塞171从开口151处突出。本发明的实施例不限制于此。根据实际应用,本领域的普通技术人员可以对导电插塞171做出适当的修改。
在本发明的一些实施例中,间隙191形成在导电插塞171和间隔件141之间以及导电插塞171和间隔件143之间。换言之,间隙191形成在导电插塞171和开口151的至少一个侧壁之间。由于空气的介电常数是1,其远低于介电材料,所以导电插塞171和栅极结构121和123之间的电隔离将变得更好。因此,器件性能将变得更好并且寄生电容将变得更小。此外,因为器件性能将变更好,减小了光刻、蚀刻工艺和套刻(overlay)控制的负担而没有影响器件的产率。此外,由于寄生电容将变更小,因此可进一步减小半导体结构100的尺寸。
根据本发明的一些实施例,一种半导体结构包括衬底、至少一个第一栅极结构、至少一个第一间隔件、至少一个源漏结构和导电插塞。所述第一栅极结构在所述衬底上。所述第一间隔件在所述第一栅极结构的至少一个侧壁上。所述源漏结构邻近所述第一间隔件。所述导电插塞电连接至所述源漏结构,同时在所述导电插塞和所述第一间隔件之间保留间隙。
在一些实施例中,所述间隙中具有气体。
在一些实施例中,该半导体结构还包括:至少一个第二栅极结构,位于所述衬底上;至少一个第二间隔件,位于所述第二栅极结构的至少一个侧壁上,其中,所述源漏结构位于所述第一间隔件和所述第二间隔件之间。
在一些实施例中,所述间隙还存在于所述导电插塞和所述第二间隔件之间。
在一些实施例中,该半导体结构还包括:介电层,至少位于所述第一栅极结构上,所述介电层中具有开口,其中,所述导电插塞的至少一部分位于所述开口中,并且所述间隙还位于所述导电插塞和所述开口的至少一个侧壁之间。
在一些实施例中,所述导电插塞从所述开口处突出。
在一些实施例中,所述源漏结构包括至少一个源漏应力源。
在一些实施例中,该半导体结构还包括:硬掩模层,位于所述第一栅极结构的顶面上。
根据本发明的一些实施例,一种半导体结构包括衬底、至少一个栅极结构、至少一个源漏结构、至少一个介电层和导电插塞。所述栅极结构位于所述衬底上。所述源漏结构位于所述衬底上。所述介电层至少位于所述栅极结构上,并且其中具有开口,其中,所述源漏结构通过所述开口露出。导电插塞至少通过所述开口电连接到所述源漏结构,同时在所述导电插塞和所述开口的至少一个侧壁之间保留间隙。
在一些实施例中,该半导体结构还包括:至少一个间隔件,位于所述栅极结构的至少一个侧壁上,其中,所述间隔件的至少一部分通过所述开口露出,并且所述间隙还存在于所述导电插塞和所述间隔件的所述部分之间。
在一些实施例中,所述间隙是气体填充。
在一些实施例中,所述导电插塞从所述开口处突出。
在一些实施例中,该半导体结构还包括:硬掩膜层,位于所述栅极结构和所述介电层之间。
根据本发明的一些实施例,一种制造半导体结构的方法,包括以下步骤。形成介电层,所述介电层位于至少一个栅极结构和至少一个源漏结构上。在所述介电层中形成开口以露出所述源漏结构。形成保护层,所述保护层位于所述开口的至少一个侧壁上。在所述开口中形成导电插塞,其中,所述导电插塞电连接至所述源漏结构。在形成导电插塞之后,去除保护层。
在一些实施例中,该方法还包括:在形成所述导电插塞后,回蚀所述介电层以露出所述保护层的至少一部分。
在一些实施例中,所述开口还露出在所述栅极结构的至少一个侧壁上的至少一个侧壁的至少一部分。
在一些实施例中,形成所述保护层还包括在所述间隔件的所述部分上形成所述保护层。
在一些实施例中,形成所述保护层还包括在露出的所述源漏结构上形成所述保护层;以及还包括:在形成所述导电插塞之前,去除在所述源漏结构上的所述保护层的至少一部分,以露出所述源漏结构。
在一些实施例中,该方法还包括:在所述介电层和所述导电插塞上形成至少一个停止层。
在一些实施例中,通过化学蚀刻去除所述保护层。
以上论述了若干实施例的部件,使得本领域的技术人员可以更好地理解本发明的各个方面。本领域技术人员应该理解,他们可以很容易地使用本发明作为基础来设计或更改其他用于达到与本文所介绍实施例相同的目的和/或实现相同优点的工艺和结构。本领域技术人员也应该意识到,这些等效结构并不背离本发明的精神和范围,并且在不背离本发明的精神和范围的情况下,可以进行多种变化、替换以及改变。
Claims (10)
1.一种半导体结构,包括:
衬底;
至少一个第一栅极结构,位于所述衬底上;
至少一个第一间隔件,位于所述第一栅极结构的至少一个侧壁上;
至少一个源漏结构,邻近于所述第一间隔件;以及
导电插塞,电连接至所述源漏结构,同时在所述导电插塞与所述第一间隔件之间留下间隙。
2.根据权利要求1所述的半导体结构,其中,所述间隙中具有气体。
3.根据权利要求1所述的半导体结构,还包括:
至少一个第二栅极结构,位于所述衬底上;
至少一个第二间隔件,位于所述第二栅极结构的至少一个侧壁上,其中,所述源漏结构位于所述第一间隔件和所述第二间隔件之间。
4.根据权利要求3所述的半导体结构,其中,所述间隙还存在于所述导电插塞和所述第二间隔件之间。
5.根据权利要求1所述的半导体结构,还包括:
介电层,至少位于所述第一栅极结构上,所述介电层中具有开口,其中,所述导电插塞的至少一部分位于所述开口中,并且所述间隙还位于所述导电插塞和所述开口的至少一个侧壁之间。
6.一种半导体结构,包括:
衬底;
至少一个栅极结构,位于所述衬底上;
至少一个源漏结构,位于所述衬底上;
至少一个介电层,至少位于所述栅极结构上,并且所述至少一个介电层中具有开口,其中,所述源漏结构通过所述开口露出;以及
导电插塞,至少通过所述开口电连接至所述源漏结构,同时所述导电插塞和所述开口的至少一个侧壁之间留下间隙。
7.根据权利要求6所述的半导体结构,还包括:
至少一个间隔件,位于所述栅极结构的至少一个侧壁上,其中,所述间隔件的至少一部分通过所述开口露出,并且所述间隙还存在于所述导电插塞和所述间隔件的所述部分之间。
8.一种制造半导体结构的方法,所述方法包括:
在至少一个栅极结构和至少一个源漏结构上形成介电层;
在所述介电层中形成开口以露出所述源漏结构;
在所述开口的至少一个侧壁上形成保护层;
在所述开口中形成导电插塞,其中,所述导电插塞电连接至所述源漏结构;以及
在形成所述导电插塞后,去除所述保护层。
9.根据权利要求8所述的方法,还包括:
在形成所述导电插塞后,回蚀所述介电层以露出所述保护层的至少一部分。
10.根据权利要求8所述的方法,其中,所述开口还露出在所述栅极结构的至少一个侧壁上的至少一个侧壁的至少一部分。
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US10164029B2 (en) | 2018-12-25 |
US10483364B2 (en) | 2019-11-19 |
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US20180374923A1 (en) | 2018-12-27 |
US20200066853A1 (en) | 2020-02-27 |
US20170179241A1 (en) | 2017-06-22 |
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CN106898597B (zh) | 2020-10-30 |
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