CN101604678B - 半导体装置、层叠型半导体装置以及内插器基板 - Google Patents

半导体装置、层叠型半导体装置以及内插器基板 Download PDF

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Publication number
CN101604678B
CN101604678B CN2009101498776A CN200910149877A CN101604678B CN 101604678 B CN101604678 B CN 101604678B CN 2009101498776 A CN2009101498776 A CN 2009101498776A CN 200910149877 A CN200910149877 A CN 200910149877A CN 101604678 B CN101604678 B CN 101604678B
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CN
China
Prior art keywords
semiconductor device
semiconductor element
type
mounting portion
semiconductor
Prior art date
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Expired - Fee Related
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CN2009101498776A
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English (en)
Chinese (zh)
Other versions
CN101604678A (zh
Inventor
细野真行
柴田明司
稻叶公男
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Hitachi Cable Ltd
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Hitachi Cable Ltd
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Filing date
Publication date
Application filed by Hitachi Cable Ltd filed Critical Hitachi Cable Ltd
Publication of CN101604678A publication Critical patent/CN101604678A/zh
Application granted granted Critical
Publication of CN101604678B publication Critical patent/CN101604678B/zh
Expired - Fee Related legal-status Critical Current
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/67—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their insulating layers or insulating parts
    • H10W70/688—Flexible insulating substrates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/701—Tape-automated bond [TAB] connectors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/40—Leadframes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/20—Configurations of stacked chips
    • H10W90/291—Configurations of stacked chips characterised by containers, encapsulations, or other housings for the stacked chips
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
    • H10W90/722—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between stacked chips

Landscapes

  • Wire Bonding (AREA)
  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
CN2009101498776A 2006-11-17 2007-11-16 半导体装置、层叠型半导体装置以及内插器基板 Expired - Fee Related CN101604678B (zh)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP2006311850 2006-11-17
JP2006311850A JP5028968B2 (ja) 2006-11-17 2006-11-17 半導体装置、積層型半導体装置およびインターポーザ基板
JP2006-311850 2006-11-17

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
CN2007101927202A Division CN101183670B (zh) 2006-11-17 2007-11-16 半导体装置、层叠型半导体装置以及内插器基板

Publications (2)

Publication Number Publication Date
CN101604678A CN101604678A (zh) 2009-12-16
CN101604678B true CN101604678B (zh) 2012-02-22

Family

ID=39416112

Family Applications (3)

Application Number Title Priority Date Filing Date
CN2009101498776A Expired - Fee Related CN101604678B (zh) 2006-11-17 2007-11-16 半导体装置、层叠型半导体装置以及内插器基板
CN2009101498780A Expired - Fee Related CN101604681B (zh) 2006-11-17 2007-11-16 半导体装置、层叠型半导体装置以及内插器基板
CN2007101927202A Expired - Fee Related CN101183670B (zh) 2006-11-17 2007-11-16 半导体装置、层叠型半导体装置以及内插器基板

Family Applications After (2)

Application Number Title Priority Date Filing Date
CN2009101498780A Expired - Fee Related CN101604681B (zh) 2006-11-17 2007-11-16 半导体装置、层叠型半导体装置以及内插器基板
CN2007101927202A Expired - Fee Related CN101183670B (zh) 2006-11-17 2007-11-16 半导体装置、层叠型半导体装置以及内插器基板

Country Status (5)

Country Link
US (2) US20080116559A1 (https=)
JP (1) JP5028968B2 (https=)
KR (1) KR100892203B1 (https=)
CN (3) CN101604678B (https=)
TW (1) TW200832659A (https=)

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5671681B2 (ja) * 2009-03-05 2015-02-18 ピーエスフォー ルクスコ エスエイアールエルＰＳ４ Ｌｕｘｃｏ Ｓ．ａ．ｒ．ｌ． 積層型半導体装置
US8363418B2 (en) * 2011-04-18 2013-01-29 Morgan/Weiss Technologies Inc. Above motherboard interposer with peripheral circuits
US11309250B2 (en) * 2018-01-17 2022-04-19 Shindengen Electric Manufacturing Co., Ltd. Electronic module
KR102743244B1 (ko) * 2019-02-12 2024-12-18 삼성전자주식회사 인쇄 회로 기판 및 이를 포함하는 반도체 패키지
JP7135999B2 (ja) * 2019-05-13 2022-09-13 株式会社オートネットワーク技術研究所 配線基板
JP7156230B2 (ja) * 2019-10-02 2022-10-19 株式会社デンソー 半導体モジュール
IT202000001819A1 (it) * 2020-01-30 2021-07-30 St Microelectronics Srl Circuito integrato e dispositivo elettronico comprendente una pluralita' di circuiti integrati accoppiati elettricamente tramite un segnale di sincronizzazione
CN112588222B (zh) * 2020-11-25 2022-02-18 浙江大学 声表面波调控孔隙率与排布的多孔聚合物制备装置与方法
CN121040214A (zh) * 2023-05-09 2025-11-28 索尼集团公司 中继部件以及电子设备

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US6111306A (en) * 1993-12-06 2000-08-29 Fujitsu Limited Semiconductor device and method of producing the same and semiconductor device unit and method of producing the same
JPH07201912A (ja) * 1993-12-28 1995-08-04 Hitachi Cable Ltd フィルムキャリア方式半導体装置及びフィルムキャリア
JPH0831868A (ja) * 1994-07-21 1996-02-02 Hitachi Cable Ltd Ｂｇａ型半導体装置
US5747874A (en) * 1994-09-20 1998-05-05 Fujitsu Limited Semiconductor device, base member for semiconductor device and semiconductor device unit
JP2755252B2 (ja) * 1996-05-30 1998-05-20 日本電気株式会社 半導体装置用パッケージ及び半導体装置
JP3195236B2 (ja) * 1996-05-30 2001-08-06 株式会社日立製作所 接着フィルムを有する配線テープ，半導体装置及び製造方法
US6617193B1 (en) * 1997-04-30 2003-09-09 Hitachi Chemical Company, Ltd. Semiconductor device, semiconductor device substrate, and methods of fabricating the same
JP2924854B2 (ja) * 1997-05-20 1999-07-26 日本電気株式会社 半導体装置、その製造方法
JP3639088B2 (ja) * 1997-06-06 2005-04-13 株式会社ルネサステクノロジ 半導体装置及び配線テープ
US6300679B1 (en) * 1998-06-01 2001-10-09 Semiconductor Components Industries, Llc Flexible substrate for packaging a semiconductor component
JP2000077563A (ja) * 1998-08-31 2000-03-14 Sharp Corp 半導体装置およびその製造方法
JP2000260792A (ja) * 1999-03-10 2000-09-22 Toshiba Corp 半導体装置
JP3180800B2 (ja) 1999-04-08 2001-06-25 カシオ計算機株式会社 半導体装置及びその製造方法
JP3722209B2 (ja) * 2000-09-05 2005-11-30 セイコーエプソン株式会社 半導体装置
JP2002289741A (ja) * 2001-03-23 2002-10-04 Nec Kyushu Ltd 半導体装置
JP4103342B2 (ja) * 2001-05-22 2008-06-18 日立電線株式会社 半導体装置の製造方法
JP3705235B2 (ja) * 2002-04-16 2005-10-12 日立電線株式会社 半導体装置の製造方法
JP4225036B2 (ja) 2002-11-20 2009-02-18 日本電気株式会社 半導体パッケージ及び積層型半導体パッケージ
JP3900093B2 (ja) * 2003-03-11 2007-04-04 日立電線株式会社 モールド金型及びそれを用いた半導体装置の製造方法
TW200514484A (en) * 2003-10-08 2005-04-16 Chung-Cheng Wang Substrate for electrical device and methods of fabricating the same
JP4291209B2 (ja) * 2004-05-20 2009-07-08 エルピーダメモリ株式会社 半導体装置の製造方法
US7154175B2 (en) * 2004-06-21 2006-12-26 Intel Corporation Ground plane for integrated circuit package
KR100715316B1 (ko) * 2006-02-13 2007-05-08 삼성전자주식회사 유연성 회로 기판을 이용하는 반도체 칩 패키지 실장 구조

Also Published As

Publication number Publication date
JP5028968B2 (ja) 2012-09-19
TW200832659A (en) 2008-08-01
CN101604681B (zh) 2012-03-14
US20080116559A1 (en) 2008-05-22
TWI363412B (https=) 2012-05-01
US20100171210A1 (en) 2010-07-08
JP2008130678A (ja) 2008-06-05
KR100892203B1 (ko) 2009-04-07
CN101183670A (zh) 2008-05-21
CN101183670B (zh) 2011-06-22
CN101604678A (zh) 2009-12-16
CN101604681A (zh) 2009-12-16
KR20080045079A (ko) 2008-05-22

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Granted publication date: 20120222

Termination date: 20131116