1335649 九、發明說明： 【發明所屬之技術領域】 本發明係有關於一種電路板結構及其製法，尤指一種 嵌埋半導體元件之電路板結構與其製造方法。 【先前技術】 隨著電子產業的蓬勃發展，電子產品在型態上趨於輕 薄短小，在功能上則逐漸邁入高性能、高功能、高速度化 的研發方向。為滿足半導體裝置之高積集度（Integration) 籲以及微型化（Miniaturization)需求，提供多數主被動元件及 線路載接之電路板（Circuit board)亦逐漸由雙層板演變成 多層板（Multi-layer board)，俾於有限的空間下，藉由層間 連接技術（Interlayer connection)擴大電路板上可利用的電 路面積而配合高電子密度之積體電路（Integrated circuit)需 求；且為求提昇單一半導體封裝件之性能與容量，以符合 電子產品小型化、大容量與高速化之發展趨勢。 φ 在電路板製造業界，低成本、高可靠度及高佈線密度 一直是所追求之目標。為達目標，於是發展出一種增層技 術（Build-up)，其係於一核心電路板（Core circuit board)表 面上交互堆疊多層介電層及線路層，再於介電層中形成係 如導電盲孔或電鍍導通孔之導電結構以電性連接各線路 層；為避免電路增層過程中，因熱膨脹係數（Coefficient of thermal expansion, CTE)導致熱應力不均產生輕曲 (Warpage)等問題，通常係於核心板之上下表面同時進行增 層製程，藉以形成一對稱之增層結構，藉以俾免產生板翹。 5 19717 1335649 然而因電路設計之需要，該核心板之上、下表面之作 用通常不同；因此，該核心板上表面之線路分佈與下表面 往往不同，而由於金屬材質之導電跡線與絕緣層及拒銲層 之熱膨係數差異大，此種基板結構於製程中之溫度變化下 易造成基板輕曲（Warpage)現象；當該核心板之一表面之 線路層密度高另一層線路密度時，於製程中之溫度變化如 烘烤（Baking)、封裝膠體固化（Curing)、後續熱循環（Thermal Cycle)作業等環境下，該核心板上、下表面會產生不同之 應力（Thermal Stress)，使該核心板之一表面產生之變形 量或收縮量不同，即導致翹曲現象，嚴重者可能造成基板 層間產生分層（Delamination)。 此外，隨著通訊、網路及電腦等各式可攜式（Portable) • 產品的大幅成長，具有高密度與多接腳化特性的球柵陣列 式（BGA)、覆晶式（Flip chip)、晶片尺寸封裝（CSP，Chip size package)與多晶片模組（MCM, Multi chip module)等封裝件 -:0已曰漸成為半導體市場上的主流，甚而發展出嵌埋半導體 , 元件之核心板結構；其中，在電路板中用以接置半導體元 件之置晶側必須製程可與其搭配的高密度與細線路（Fine circuit)之多層線路以符合高度集積化（Integration)所需，相 對地，在該電路板用以接置於外部電子裝置側，無如同該 置晶側般形成有相同之高佈線密度，如此即易造成翹曲現 象，使得嵌埋於核心板中之半導體元件受熱應力不平均的 影響，造成半導體元件損壞。 請參閱第1A至1E圖所示，係為核心板中接置半導體 6 19717 1335649 元件之製法流程示意圖。 如第1A圖所示，係提供一具有第一表面Ua及第二 ，面lib之核心板u ’且該核心板n具有一貫穿第一及 第一表面lla，llb之開口 11〇，並於該核心板11之第二表 面1 lb形成有一離型膜12以封住該開口 110之一端。 如第圖所示，於該核心板11之開口丨1〇中接置有 -半導體件13 ’該半導體^件13具有—主動面13&及 非=動面13b，於該主動面…具有複數電極墊i3i，且該 半導體70件13係以非主動面nb接置於該開口 中之離 型膜12的表面上。 —如弟ic圖所示，於該核心板u之開口 ιι〇中盥半導 體元件13之間形成有一黏著材料14，俾以將該半導體元 件13固定於該開口 110中。 及本H⑴圖所示’接著移除該核心板11之第二表面nb +導,70件13之非主動面i3b表面之離型臈12。 φ 如第1E圖所示，於該核心板11之第一表面Ua及本 ^兀件13之主動面Ua上形成線路增層結構15，並於 成第二表面UbW ^另-料增層結構15，；該些、㈣增層結構 之缘路至少一介電層151，151，、疊置於該介電層上 I2，152，，以及形成於該介電層中之導電結構 體元件該導電結構出係可電性連接至該半導 之包極墊131，且於該線路增層結 面復包括有複數電性連接―又於該線路= 19717 7 1335649 構15，15’覆盖有一防焊層16，16，，且該防焊層16，16，中形 成有複數開孔160,160’以露出該線路增層結構15，15，外表 面之電性連接墊154，154,。 如前所述，於該核心板u之第一及第二表面lla,ub 因電路設計的需要而分別形成層數及密度不同的線路增層 結構15，15,，如此在製程中容易發生板翹（w—age)或分 =的問題，間接地影響到可靠度及品質。又增層的疊層數 置亦受限於板翹問題而無法做更高階及更多層之組合，而 成為半導體封裝件高積集度化及微型化之阻礙。 因此，如何提出一種嵌埋半導體晶片之電路板結構， 以避免習知電路板結構抗彎曲強度差之缺失，實以成爲目 别業界亟待克服之課題。 ’ 【發明内容】 鑑於珂述習知技術之缺失，本發明之主要目的係提供 一種嵌埋半導體元件之電路板結構及其製法，得提高承載 :魯板之結構強度，以避免產生翹曲的問題。 ： 本發明之又一目的，係在提供一種嵌埋半導體元件之 電路板結構及其製法，得避免電路板產生赵曲造成半導體 元件之損壞。 本發明之再—目的，係在提供一種嵌埋半導體元件之 電路板結構及其製法，得避免電路板產生翹曲以因應非對 稱增層線路之所需^ ^本月之另—目的，係在提供一種喪埋半導體元件之 電路板、’’。構及其製法，得避免翹曲而導致電路板分層的問 19717 8 13356491335649 IX. Description of the Invention: [Technical Field] The present invention relates to a circuit board structure and a method of fabricating the same, and more particularly to a circuit board structure in which a semiconductor component is embedded and a method of fabricating the same. [Prior Art] With the rapid development of the electronics industry, electronic products tend to be light and thin in terms of type, and gradually become a high-performance, high-function, high-speed research and development direction in terms of functions. In order to meet the high integration and miniaturization requirements of semiconductor devices, circuit boards that provide most active and passive components and line-loading have gradually evolved from double-layer boards to multi-layer boards (Multi- Layer board), in a limited space, expands the available circuit area on the board by Interlayer connection to match the high electron density integrated circuit requirements; and to enhance the single semiconductor The performance and capacity of the package to meet the trend of miniaturization, large capacity and high speed of electronic products. φ In the board manufacturing industry, low cost, high reliability and high wiring density have always been the goal. In order to achieve the goal, a build-up technology was developed, which is to stack multiple layers of dielectric layers and circuit layers on the surface of a core circuit board, and then form a system in the dielectric layer. The conductive structure of the conductive blind hole or the plated via hole electrically connects the circuit layers; in order to avoid the problem of the thermal stress unevenness caused by the coefficient of thermal expansion (CTE) during the circuit build-up process, the warpage is caused. Usually, the layer is formed on the lower surface of the core plate at the same time to form a symmetrical layered structure, thereby forcing the board to be warped. 5 19717 1335649 However, due to the design of the circuit, the upper and lower surfaces of the core board usually have different functions; therefore, the line distribution on the surface of the core board is often different from that of the lower surface, and the conductive traces and insulation layers of the metal material are different. And the difference in thermal expansion coefficient of the solder resist layer is large, and the substrate structure is liable to cause a warpage of the substrate under temperature changes in the process; when the density of the circuit layer on one surface of the core board is higher than the density of another layer, In the environment of the process changes such as baking, encapsulating colloid, and subsequent thermal cycle operations, the core plate and the lower surface will have different stresses (Thermal Stress). The surface of one of the core plates has a different amount of deformation or shrinkage, which causes a warp phenomenon, and a serious one may cause delamination between the substrate layers. In addition, with the growth of various portable (portable) products such as communication, network and computer, ball grid array (BGA) and flip chip (Flip chip) with high density and multi-pinning characteristics. Packages such as CSP (Chip size package) and Multi Chip Module (MCM) have become the mainstream in the semiconductor market, and even the embedded core, the core board of components a structure in which a crystallized side for connecting a semiconductor element in a circuit board must have a high-density and fine circuit multilayer circuit with which the process can be matched to meet a high integration requirement, in contrast, The circuit board is used to be connected to the external electronic device side, and the same high wiring density is not formed as the crystallizing side, so that the warpage phenomenon is easily caused, so that the semiconductor component embedded in the core board is not subjected to thermal stress. The average effect causes damage to the semiconductor components. Please refer to Figures 1A to 1E for a schematic diagram of the process flow for connecting the components of the semiconductor 6 19717 1335649 in the core board. As shown in FIG. 1A, a core board u' having a first surface Ua and a second surface lib is provided, and the core board n has an opening 11〇 extending through the first and first surfaces 11a, 11b, and The second surface 1 lb of the core plate 11 is formed with a release film 12 to seal one end of the opening 110. As shown in the figure, a semiconductor device 13 is mounted in the opening 〇1 of the core board 11. The semiconductor component 13 has an active surface 13& and a non-moving surface 13b, and the active surface has a plurality of The electrode pad i3i, and the semiconductor 70 member 13 is attached to the surface of the release film 12 in the opening by the inactive surface nb. - As shown in the figure ic, an adhesive material 14 is formed between the semiconductor elements 13 in the opening of the core board u to fix the semiconductor element 13 in the opening 110. And the second surface nb + of the core plate 11 is removed as shown in the figure H(1), and the release liner 12 of the surface of the inactive surface i3b of the 70 member 13 is removed. As shown in FIG. 1E, a line build-up structure 15 is formed on the first surface Ua of the core board 11 and the active surface Ua of the board member 13, and is formed into a second surface UbW. And (4) the edge of the build-up structure, at least one dielectric layer 151, 151, stacked on the dielectric layer I2, 152, and the conductive structure component formed in the dielectric layer The conductive structure is electrically connected to the semi-conductive pad pad 131, and includes a plurality of electrical connections on the line-increasing junction surface - and the line = 19717 7 1335649 structure 15, 15' covers an anti-proof The solder layers 16, 16, and the solder resist layers 16, 16 are formed with a plurality of openings 160, 160' to expose the line build-up structures 15, 15 and the electrical connection pads 154, 154 of the outer surface. As described above, on the first and second surfaces 11a of the core board u, ub respectively form line buildup structures 15 and 15 having different layers and densities due to circuit design requirements, so that boards are easily generated in the process. The problem of w-age or sub-indirectly affects reliability and quality. The number of stacked layers of the additional layers is also limited by the problem of the warpage and cannot be combined with higher order and more layers, which is a hindrance to the high integration and miniaturization of the semiconductor package. Therefore, how to propose a circuit board structure in which a semiconductor chip is embedded to avoid the lack of bending strength difference of the conventional circuit board structure has become an urgent problem to be overcome in the industry. SUMMARY OF THE INVENTION In view of the absence of the conventional techniques, the main object of the present invention is to provide a circuit board structure in which a semiconductor element is embedded and a method of manufacturing the same, which can improve the structural strength of the load plate to avoid warpage. problem. Another object of the present invention is to provide a circuit board structure in which a semiconductor element is embedded and a method of manufacturing the same, which can avoid damage of the semiconductor element caused by the occurrence of a warpage of the circuit board. A further object of the present invention is to provide a circuit board structure embedded in a semiconductor component and a method of manufacturing the same, which can avoid the warpage of the circuit board to meet the needs of the asymmetric build-up line. Provided is a circuit board for burying semiconductor components, ''. Structure and its method, to avoid warping and cause the board to stratify 19717 8 1335649
為達上違及其它目的，本發明提供一種嵌埋半導體元 2電路板結構m至少二承餘，各該承載板形 至少一開口，至少一半導體元件，係容置於該至少二 承載板的開口中；α及結合材料，係形成於該至少二承載 ^之間以及開口與半導^件之間的間隙中，俾以將該半 =凡件固定於該至少二承載板之開口中，且藉由該結合 I材枓提⑥電路板結構之整體剛性，以避免產生板鍾。 依上述之結構，本發明復揭露—種嵌埋半導體元件之 :::反結構之製法’係包括：提供至少二承載板，且各該 2 =具有至少—相對應之開口 ；於該至少：承載板之間 將^結合材料:以將該至少二承載板結合成—體；以及 —、夕—_導體7C件置於該至少二承載板及結合材料之開 :該半載板及結合材料’使該結合材料形成 ”開口之間的間隙中，以將該半導體元件 疋该至少二承載板開口中，且藉由該結 路板結構之整體剛性，以避免產生板麵。从问電 =餘係為金屬板、m絕緣板及已完 =製程之電路板單元所組频之其中m心 :板係為環氧樹脂、聚乙酿胺、氰脂、FR4、FR5、破：： 脂等所組群but 璃纖維與環氧樹 ^ 、八中一者，該結合材料係塗佈於該二承_ ^間’或該結合材㈣夾置於該二承載板之間，且2 。才科具有相對於該二承載板之開口，俾可藉由該結合： 19717 9 1335649 料以結合二承載板及將該+導體元件固定於該開口中；今 結，料係為封裝材料（Molding c〇mp〇und),例如熱塑: 樹脂（thermal scting)或熱固性樹脂之其中一者。 該半導體元件係具有一主動面及相對之非主動面，且 該主動面具有複數個電極塾，此外於該承載板未形 =料：Γ及半導體元件之主動面上可形成有線路增； ^，I線路增層結構係包括至少—介電層、叠置於該介 电曰上之線路層’以及形成於該介電層中之導電結構，且 该線路增層結構中具有複數導電結構以電性連接至該 ^件之電極塾，又該線路增層結構外表面復包括有複數 電性連㈣’另於該線路增層結構外表面覆蓋有一防焊 層，且該防焊層中形成有複數開孔以露出該線路增層結構 •外^之電性連接塾。再者於該承載板未形成有結合㈣ =表面及半導體元件之非主動面上復可形成有另一線路掸 層結構’且該形成於該半導體元件非主動面上之線路增^ : <吉構之層數係、可不同於形成於該半導體元件主動面上之ς 、路彡曰層、纟《構之層數，以構成非對稱之線路增層結構。 、因此，本發明之嵌埋半導體元件之電路板結構及其製 法中，係將至少二承載板以結合材料結合成一體，藉由該 結合材料提高電路板結構之整體剛性，以增加結構強度， 且該承載板係為金屬板、陶£板、絕緣板、已完成前段線 路製程之電路板單元或其組合，而可成為一複合結構，俾 以提高整體之結構強度，以避免在後續非對稱之線路增層 製程中因熱膨脹係數不同所產生的熱應力造成電路板結構 19717 10 1335649 。所尤曲或刀層的問題，俾可提高電路板結構之可靠度及 • 二’又該半導體元件係嵌埋於抗翹曲之至少二承載板之 =中，传藉由抗變形翹曲結構以避免受熱應力影響受擠 又该至少二承.载板以結合材料結合成—體，藉由該結 5 !!料提高電路板結構之整體剛性，俾以提高整體強度， 1仔於承載板之外表面分別形成非對稱之線路增層結 構’以因應電路設計之所需。 •【實施方式】 乂下係藉由特疋的具體實例說明本發明之實施方 =，悉此技藝之人士可由本說明書所揭示之内容輕易地 瞭解本發明之其他優點與功效。 第2A圖至帛2D目，係詳細說明本發明之嵌埋 +導體兀件之電路板結構及其製法之剖面示意圖。 如第2A圖’首先，係裎 •於該等承載板21，21，各二、至少二承载板21及21，’ } 合形成至少一相對應之開口 210,210’ ’而該承載板21 ^ » p - ^ ^ ，21係為金屬板、陶瓷板、絕緣 板及已元^料路製^電路板單摘組縣之立中-者，又祕緣板係可為環氧樹脂、聚 如、玻璃纖維、㈣H㈣胺氰 纖雉與環氧樹脂等所組群組之其中—者。圾肖 如第⑼圖，於該至少二承載板η，;!，之間形成一結 合材料22，忒結合材料22 你』為封裝材料，例如埶塑性 樹脂或熱固性樹脂之其中一_ 了寸例如…土 r生 者’邊結合材料22係塗佈於該 19717 11 1335649 二承载板21，2Γ之間，或該結合材料22係失置於該二承載 板21，21’之間，且該結合材料22並形成有相對於該二承载 板 21，21’之開口 220。 凊參閱第2Β’圖，係為三層之承載板21，21，,22,，，並於 其間形成有/結合材料22,22，，而成為一三層式之壓合結 構；故本發明並非以兩層或三層式結構為限，得依製程需 要增加受合的數量。 如第2C圖，接著，將一半導體元件23置於該開口 21〇,210’中，然後壓合該二承載板21，21，及結合材料22， 而該結合材料22係為熱塑性樹脂或熱固性樹脂之其中一 者，得依結合材料22之選用而於壓合前或壓合後進行加 熱，以將該結合材料22壓入於該半導體元件23與開口 210,21〇’之間的間隙中，俾以將該半導體元件固定於該 二承載板21，21，之開口 21〇,21〇，中；且該半導體元件23 = 有一主動面23a及非主動面23b，於該主動面23a具有 i❿數電極塾23 1。 :如f 2D圖所示，於該承載板21未形成有結合材料u 1表面2U及半導體元件23之主動面23a上形成線路增層 '纟。構24’該線路增層結構以係包括至少一介電層μ卜疊 =於該介電層上之線路層242’以及形成於該介電層中： $電結構243，且該導電結構243係可電性連接至該半導 體兀件23之電極塾231，又於該線路增層結構外表面 =包括有複數電性連接塾244’另於該線路增層結構^外 表面覆k有-防焊層25，且該防焊層25中形成有複數開 19717 12 1335649 面之電性連接墊 孔250以露出該線路增層結構24外表 244 〇 又於該承載板2 1 ’未形成有結合材料22之另一面 21 a’及半導體元件23之非主動面23b上开ί + Ψ 上化成另一線路增層 、-.。構24,，該線路增層結構24，係包括至少—介電層μ，、 線路層242，、㈣結構243,及電性連㈣⑷，，以曰及一覆 盖於該線路增層結構24,外表面之防桿層&，，且㈣_ 25 ’形成有複數開孔道以露出該線路增層結構μ，表面: ’電性連接墊244，。 +依上述之製法，本發明復提供一種嵌埋半導體元件之 =板結構，係包括：至少二承載板2】,2ι，，各該承载板 . 山形成有至少-開口 210,210，； 一容置於該開口 • 一’210中之半導體70件23;以及結合材料22,係形成於 —承載板21，21’之間以及開σ 21(),21()，與半導體元件23 ，門p求中’以將§亥半導體元件23固定於該二承載板 < ’之開口 21 〇,21 〇’中’且藉由該結合材料22提高電路 :反、，，。構之整體剛性，以避免產生板翹。 —义μ表載板21，21係為金屬板、陶瓷板、絕緣板及已 =人則段線路製程之電路板單元所組群組之其中一者；該 材料係為封裝材料，如熱塑性樹脂或熱固性 中一者。 Λ半^組元件23復包括一主動面23a及非主動面 2 3 b，Ί亥主 2 ^ 面23a具有複數個電極墊231，且於該承載板 形成有結合材料22之表面21a及半導體元件23之主 13 19717 1335649 ，23a上形成有線路增層結構24;又於該承載板2】，未 面° /材料Μ之表面2U，及半導體元件23之非主動 3b上形成有另一線路增層結構μ，·該些線路增層結 、s 24,24係包括至少―介電層241,241，、線路層242,242，、 =結構243,243 ’及電性連接塾糾’⑽，，以及一覆蓋於 ^路增層結構24,24,外表面之防焊層25,25，，且該防谭 5形成有複數開孔250,250,以露出該線路增層結構 _』4,24’表面之電性連接墊244,244,。 、本《明之肷埋半導體元件 < 電路板結構及其製法，係 =硬化後具有相當結構強度之結合材料將至少二承載板结 s成一體，俾以提高該雷路板紝構 一峪槪、構之結構強度，且該承载 屬板、陶究板、絕緣板、已完成前段線路製程之 組合’而可成為一複合結構’俾以提高整 度’以避免在後續非對稱之線路增層製程中因 2脹係數不同所產生的熱應力造成電路板結構產线曲 _或〃刀層的問題，俾可提高電路板結構之可靠度及品質又 該半導體元件係嵌埋於—曲之至少二承載板之=申， 侍错由抗變升地曲結構以避免受熱應力影響受擠 壞。 叩？貝 又該至少二承載板以結合材料結合成一體 整體強度，而得於該二承載板之外表面分別形成非對稱: 線路增層結構，以因應電路設計之所需。 上述貫施例僅例示性說明本發明之原理复 非用於限制本發明。任何熟習此項技藝之人士 刁可在不違 14 19717 1335649 % ., 二本發明之精神及範疇下，對上述實施例進行修飾與改 • ’邊。因此，本發明之權利保護範圍，應如後述之申請專利 範圍所列。 【圖式簡單說明】 第1A至1E圖係為習知半導體元件嵌埋於核心板中 之製法流程示意圖； 第2 A至2D係為本發明之嵌埋半導體元件之電路板結 構及其製法之較佳實施例之剖面示意圖；以及 第2B圖係為第2B圖之另一實施例。 【主要元件符號說明】 11 核心板 11a 第—表面 lib 第二表面 11〇,210,210，，220 開口 12 離型膜 13,23 半導體元件 131,231 電極塾 13a,23a 主動面 13b,23b 非主動面 14 黏考材料 15,15，，24,24， 、線路增層結構 151,15Γ,241,2415 介電層 152,152，,242,2425 線路層 153,153,,243,243, 導電結構 15 19717 1335649 154,154，,244,244， 電性連接墊 16，16，，25,25’ 防焊層 160,160,,250,250, 開孔 21,21,,22,5 承載板 21a，21a， 表面 22,22? 結合材料 16 19717In order to achieve the above, the present invention provides a circuit board structure m with at least two recesses, each of which has at least one opening, at least one semiconductor component, and is disposed on the at least two carrier boards. In the opening, the α and the bonding material are formed in the gap between the at least two carriers and between the opening and the semi-conductor, and the half is fixed in the opening of the at least two carrier plates, And the overall rigidity of the 6-board structure is improved by the combined I material to avoid the generation of the board clock. According to the above structure, the present invention discloses a method for: embedding a semiconductor device::: a method for manufacturing an inverse structure includes: providing at least two carrier plates, and each of the 2 = having at least a corresponding opening; at least: Bonding materials between the carrier plates: combining the at least two carrier plates into a body; and -, the __ conductor 7C members are placed on the at least two carrier plates and the opening of the bonding material: the carrier plates and bonding materials 'Making the bonding material formed in the gap between the openings to enclose the semiconductor component in the at least two carrier openings, and by virtue of the overall rigidity of the routing plate structure, to avoid the occurrence of the board surface. The remaining parts are metal plates, m-insulation boards, and the frequency of the circuit board units that have been finished = process: the board is epoxy resin, polyethylamine, cyanide, FR4, FR5, broken:: fat, etc. The group of but glass fibers and epoxy tree ^, one of the eight, the bonding material is applied between the two bearing _ ^ ' or the bonding material (four) is sandwiched between the two carrier plates, and 2 . The branch has an opening relative to the two carrier plates, and the combination can be made by the combination: 19717 9 1335649 The two carrier plates are combined and the + conductor member is fixed in the opening; in this case, the material is a packaging material, such as one of thermal scting or thermosetting resin. The semiconductor component has an active surface and a relatively non-active surface, and the active surface has a plurality of electrode electrodes, and further, a line increase can be formed on the active surface of the carrier plate and the semiconductor device; The I line build-up structure includes at least a dielectric layer, a circuit layer stacked on the dielectric germanium, and a conductive structure formed in the dielectric layer, and the circuit has a plurality of conductive structures in the build-up structure. Electrically connected to the electrode 塾 of the device, and the outer surface of the circuit build-up structure further comprises a plurality of electrical connections (4), and the outer surface of the circuit-added structure is covered with a solder resist layer, and the solder resist layer is Forming a plurality of openings to expose the electrical connection structure of the wiring build-up structure and the outer layer. Further, the carrier board is not formed with a bonding (4) = surface and the inactive surface of the semiconductor component can be formed with another circuit. Layer structure 'and The number of layers formed on the inactive surface of the semiconductor device may be different from the number of layers formed on the active surface of the semiconductor device, the layer of the crucible, and the number of layers of the structure. The circuit board structure of the embedded semiconductor component of the present invention and the method for manufacturing the same are characterized in that at least two carrier plates are integrated by a bonding material, and the circuit board structure is improved by the bonding material. The overall rigidity is to increase the structural strength, and the carrier plate is a metal plate, a ceramic plate, an insulating plate, a circuit board unit that has completed the front line process, or a combination thereof, and can be a composite structure to improve the overall structure. The structural strength is to avoid the board structure 19917 10 1335649 caused by the thermal stress caused by the difference in thermal expansion coefficient in the subsequent asymmetric line build-up process. The problem of the special curvature or the blade layer can improve the reliability of the circuit board structure and the semiconductor component is embedded in the at least two carrier plates of the warpage resistance, and the anti-deformation warp structure is transmitted. In order to avoid the influence of the thermal stress on the squeeze, the at least two carrier plates are combined by the bonding material, and the overall rigidity of the circuit board structure is improved by the bonding material to improve the overall strength. The outer surfaces form an asymmetric line build-up structure respectively to meet the needs of the circuit design. • [Embodiment] The present invention is described by way of specific examples of the features of the present invention. Those skilled in the art can readily appreciate other advantages and effects of the present invention from the disclosure herein. 2A to 2D are schematic cross-sectional views showing a circuit board structure of the embedded + conductor element of the present invention and a manufacturing method thereof. As shown in Fig. 2A, firstly, the carrier plates 21, 21, each of the two, at least two carrier plates 21 and 21, ' } are formed to form at least one corresponding opening 210, 210'' and the carrier plate 21 ^ » p - ^ ^ , 21 is a metal plate, a ceramic plate, an insulating plate, and a metal plate, a circuit board, a single board group, and a secret edge plate can be epoxy resin, poly, Among the group of glass fiber, (four) H (tetra) amine cyanide fiber and epoxy resin. As shown in the figure (9), a bonding material 22 is formed between the at least two carrier plates η, !!!, and the bismuth bonding material 22 is an encapsulating material, such as one of enamel plastic resin or thermosetting resin. The soil bonder's edge bonding material 22 is applied between the 19917 11 1335649 two carrier plates 21, 2Γ, or the bonding material 22 is lost between the two carrier plates 21, 21', and the combination The material 22 is formed with an opening 220 relative to the two carrier plates 21, 21'.凊Reference to FIG. 2A, which is a three-layer carrier plate 21, 21, 22, and with a bonding material 22, 22 formed therebetween, and becomes a three-layer compression structure; It is not limited to a two- or three-layer structure, and it is necessary to increase the number of combinations according to the process. As shown in FIG. 2C, a semiconductor component 23 is placed in the opening 21, 210', and then the two carrier plates 21, 21, and the bonding material 22 are bonded, and the bonding material 22 is made of a thermoplastic resin or thermosetting. One of the resins may be heated before or after the pressing according to the selection of the bonding material 22 to press the bonding material 22 into the gap between the semiconductor element 23 and the openings 210, 21'. The semiconductor element is fixed to the openings 21〇, 21〇 of the two carrier plates 21, 21; and the semiconductor element 23 = has an active surface 23a and an inactive surface 23b, and the active surface 23a has i❿ Number electrode 塾 23 1. As shown in the f 2D diagram, a line build-up layer 纟 is formed on the carrier sheet 21 on which the surface 2U of the bonding material u 1 and the active surface 23a of the semiconductor element 23 are not formed. The wiring layer structure includes at least one dielectric layer </ RTI> = a wiring layer 242 ′ on the dielectric layer and is formed in the dielectric layer: an electrical structure 243, and the conductive structure 243 The electrode 塾231 is electrically connected to the semiconductor element 23, and the outer surface of the line build-up structure includes a plurality of electrical connections 塾 244' and the outer surface of the line build-up structure is covered with a soldering layer 25, and the solder resist layer 25 is formed with a plurality of electrical connection pad holes 250 of the surface of the 19917 12 1335649 surface to expose the outer surface 244 of the circuit build-up structure 24, and the bonding material is not formed on the carrier board 2 1 ' The other side 21 a' of 22 and the inactive surface 23b of the semiconductor element 23 are opened ί + 上 to form another line build-up layer, -. Structure 24, the line build-up structure 24 includes at least a dielectric layer μ, a circuit layer 242, a (four) structure 243, and an electrical connection (4) (4), covering the line build-up structure 24 with and/or The outer surface of the anti-bar layer &, and (d) _ 25 ' is formed with a plurality of openings to expose the line build-up structure μ, the surface: 'electrical connection pad 244,. According to the above method, the present invention provides a board structure for embedding a semiconductor component, comprising: at least two carrier boards 2, 2, and each of the carrier boards. The mountain is formed with at least an opening 210, 210; In the opening, a semiconductor 70 piece 23; and a bonding material 22 are formed between the carrier plates 21, 21' and the opening σ 21 (), 21 (), and the semiconductor component 23, the gate p In the 'opening of the semiconductor element 23 to the two carrier plates < 'opening 21 〇, 21 〇 'in ' and by the bonding material 22 to improve the circuit: reverse,,,. The overall rigidity of the structure is to avoid the occurrence of warping. - the μμ table carrier 21, 21 is one of a group of metal plates, ceramic plates, insulating plates, and circuit board units that have been used in the human line process; the material is a packaging material such as a thermoplastic resin Or one of thermosetting. The semiconductor component 23 includes an active surface 23a and a non-active surface 23b, and the main surface 2a has a plurality of electrode pads 231, and the surface 21a of the bonding material 22 and the semiconductor component are formed on the carrier. 23 main 13 19717 1335649, 23a is formed with a line build-up structure 24; and on the support plate 2], the surface 2U of the surface/material ,, and the non-active 3b of the semiconductor element 23 are formed with another line. The layer structure μ, the line buildup junctions, the s 24, 24 series include at least a dielectric layer 241, 241, a circuit layer 242, 242, a = structure 243, 243 ' and an electrical connection 塾 ' ' (10), and a cover The road layer structure 24, 24, the outer surface of the solder resist layer 25, 25, and the anti-tan 5 is formed with a plurality of openings 250, 250 to expose the electrical connection pad of the line build-up structure _" 4, 24' surface 244,244,. , "The semiconductor element buried in the Ming Dynasty" circuit board structure and its manufacturing method, the combination material having a considerable structural strength after hardening, at least two load-bearing plate s are integrated, so as to improve the structure of the lightning path plate, The structural strength of the structure, and the combination of the bearing plate, the ceramic board, the insulating board, and the completed front line process can be a composite structure 'to improve the degree' to avoid the subsequent asymmetric layer-adding process In the middle of the circuit due to the difference in the thermal expansion of the thermal expansion caused by the thermal expansion of the circuit board, the reliability of the circuit board structure and the quality of the circuit board are embedded in the The load plate = Shen, the fault is caused by the anti-swelling structure to avoid being crushed by the thermal stress. knock? The at least two carrier plates are combined with the bonding material to form an integral strength, and the outer surfaces of the two carrier plates are respectively formed asymmetric: a line-adding structure to meet the needs of the circuit design. The above-described embodiments are merely illustrative of the principles of the invention and are not intended to limit the invention. Anyone skilled in the art may modify and modify the above embodiments without departing from the spirit and scope of the invention. Therefore, the scope of protection of the present invention should be as set forth in the scope of the patent application to be described later. BRIEF DESCRIPTION OF THE DRAWINGS FIGS. 1A to 1E are schematic diagrams showing a process flow of a conventional semiconductor device embedded in a core board; and FIGS. 2A to 2D are circuit board structures of the embedded semiconductor device of the present invention and a method for manufacturing the same A schematic cross-sectional view of a preferred embodiment; and a second embodiment of FIG. 2B is another embodiment of FIG. 2B. [Main component symbol description] 11 Core board 11a First surface lib Second surface 11〇, 210, 210, 220 Opening 12 Release film 13, 23 Semiconductor component 131, 231 Electrode 塾 13a, 23a Active surface 13b, 23b Inactive surface 14 Sticky Test materials 15, 15, 24, 24, line build-up structure 151, 15 Γ, 241, 2415 dielectric layer 152, 152, 242, 2425 circuit layer 153, 153, 243, 243, conductive structure 15 19717 1335649 154, 154, 244, 244, electricity Connection pads 16, 16, 25, 25' solder masks 160, 160, 250, 250, openings 21, 21, 22, 5 carrier plates 21a, 21a, surface 22, 22? bonding material 16 19717