CN101604663B - 半导体器件的阱区 - Google Patents
半导体器件的阱区 Download PDFInfo
- Publication number
- CN101604663B CN101604663B CN2009101409382A CN200910140938A CN101604663B CN 101604663 B CN101604663 B CN 101604663B CN 2009101409382 A CN2009101409382 A CN 2009101409382A CN 200910140938 A CN200910140938 A CN 200910140938A CN 101604663 B CN101604663 B CN 101604663B
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- CN
- China
- Prior art keywords
- type
- subsurface
- well
- wells
- bias voltage
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
- H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
- H10D62/113—Isolations within a component, i.e. internal isolations
- H10D62/114—PN junction isolations
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C5/00—Details of stores covered by group G11C11/00
- G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
- G11C5/145—Applications of charge pumps; Boosted voltage circuits; Clamp circuits therefor
- G11C5/146—Substrate bias generators
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
- H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
- H10D62/17—Semiconductor regions connected to electrodes not carrying current to be rectified, amplified or switched, e.g. channel regions
- H10D62/393—Body regions of DMOS transistors or IGBTs
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
- H10D84/01—Manufacture or treatment
- H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
- H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
- H10D84/0156—Manufacturing their doped wells
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
- H10D84/01—Manufacture or treatment
- H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
- H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
- H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
- H10D84/0191—Manufacturing their doped wells
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
- H10D84/01—Manufacture or treatment
- H10D84/02—Manufacture or treatment characterised by using material-based technologies
- H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
- H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
- H10D84/80—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs
- H10D84/82—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components
- H10D84/83—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
- H10D84/85—Complementary IGFETs, e.g. CMOS
- H10D84/859—Complementary IGFETs, e.g. CMOS comprising both N-type and P-type wells, e.g. twin-tub
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D89/00—Aspects of integrated devices not covered by groups H10D84/00 - H10D88/00
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D89/00—Aspects of integrated devices not covered by groups H10D84/00 - H10D88/00
- H10D89/211—Design considerations for internal polarisation
- H10D89/213—Design considerations for internal polarisation in field-effect devices
- H10D89/215—Design considerations for internal polarisation in field-effect devices comprising arrangements for charge pumping or biasing substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Semiconductor Integrated Circuits (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Element Separation (AREA)
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US10/334,272 US6936898B2 (en) | 2002-12-31 | 2002-12-31 | Diagonal deep well region for routing body-bias voltage for MOSFETS in surface well regions |
| US10/334,272 | 2002-12-31 |
Related Parent Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB2003801080465A Division CN100502005C (zh) | 2002-12-31 | 2003-12-29 | 半导体器件的阱区 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN101604663A CN101604663A (zh) | 2009-12-16 |
| CN101604663B true CN101604663B (zh) | 2011-08-03 |
Family
ID=32654999
Family Applications (2)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2009101409382A Expired - Fee Related CN101604663B (zh) | 2002-12-31 | 2003-12-29 | 半导体器件的阱区 |
| CNB2003801080465A Expired - Fee Related CN100502005C (zh) | 2002-12-31 | 2003-12-29 | 半导体器件的阱区 |
Family Applications After (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB2003801080465A Expired - Fee Related CN100502005C (zh) | 2002-12-31 | 2003-12-29 | 半导体器件的阱区 |
Country Status (5)
| Country | Link |
|---|---|
| US (9) | US6936898B2 (enExample) |
| JP (1) | JP4688501B2 (enExample) |
| CN (2) | CN101604663B (enExample) |
| AU (1) | AU2003300399A1 (enExample) |
| WO (1) | WO2004061967A2 (enExample) |
Families Citing this family (47)
| Publication number | Priority date | Publication date | Assignee | Title |
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| US7180322B1 (en) | 2002-04-16 | 2007-02-20 | Transmeta Corporation | Closed loop feedback control of integrated circuits |
| US7941675B2 (en) | 2002-12-31 | 2011-05-10 | Burr James B | Adaptive power control |
| US7949864B1 (en) * | 2002-12-31 | 2011-05-24 | Vjekoslav Svilan | Balanced adaptive body bias control |
| US7228242B2 (en) | 2002-12-31 | 2007-06-05 | Transmeta Corporation | Adaptive power control based on pre package characterization of integrated circuits |
| US7953990B2 (en) | 2002-12-31 | 2011-05-31 | Stewart Thomas E | Adaptive power control based on post package characterization of integrated circuits |
| US7205758B1 (en) | 2004-02-02 | 2007-04-17 | Transmeta Corporation | Systems and methods for adjusting threshold voltage |
| US7323367B1 (en) | 2002-12-31 | 2008-01-29 | Transmeta Corporation | Diagonal deep well region for routing body-bias voltage for MOSFETS in surface well regions |
| US6936898B2 (en) * | 2002-12-31 | 2005-08-30 | Transmeta Corporation | Diagonal deep well region for routing body-bias voltage for MOSFETS in surface well regions |
| WO2004070832A1 (ja) * | 2003-02-04 | 2004-08-19 | Matsushita Electric Industrial Co., Ltd. | 半導体集積回路装置 |
| KR100536612B1 (ko) * | 2003-10-09 | 2005-12-14 | 삼성전자주식회사 | 소프트 에러율 내성 및 래치업 내성을 증진시키기 위한 웰구조를 갖는 반도체 장치 및 그 제조 방법 |
| US7174528B1 (en) | 2003-10-10 | 2007-02-06 | Transmeta Corporation | Method and apparatus for optimizing body bias connections in CMOS circuits using a deep n-well grid structure |
| US7049699B1 (en) * | 2003-11-12 | 2006-05-23 | Transmeta Corporation | Low RC structures for routing body-bias voltage |
| US7012461B1 (en) | 2003-12-23 | 2006-03-14 | Transmeta Corporation | Stabilization component for a substrate potential regulation circuit |
| US7129771B1 (en) | 2003-12-23 | 2006-10-31 | Transmeta Corporation | Servo loop for well bias voltage source |
| US7649402B1 (en) | 2003-12-23 | 2010-01-19 | Tien-Min Chen | Feedback-controlled body-bias voltage source |
| US7692477B1 (en) | 2003-12-23 | 2010-04-06 | Tien-Min Chen | Precise control component for a substrate potential regulation circuit |
| US7816742B1 (en) | 2004-09-30 | 2010-10-19 | Koniaris Kleanthes G | Systems and methods for integrated circuits comprising multiple body biasing domains |
| US7645673B1 (en) | 2004-02-03 | 2010-01-12 | Michael Pelham | Method for generating a deep N-well pattern for an integrated circuit design |
| US7759740B1 (en) * | 2004-03-23 | 2010-07-20 | Masleid Robert P | Deep well regions for routing body-bias voltage to mosfets in surface well regions having separation wells of p-type between the segmented deep n wells |
| US7388260B1 (en) | 2004-03-31 | 2008-06-17 | Transmeta Corporation | Structure for spanning gap in body-bias voltage routing structure |
| US7313779B1 (en) | 2004-10-12 | 2007-12-25 | Transmeta Corporation | Method and system for tiling a bias design to facilitate efficient design rule checking |
| US7211870B2 (en) * | 2004-10-14 | 2007-05-01 | Nec Electronics Corporation | Semiconductor device |
| JP2006140448A (ja) * | 2004-10-14 | 2006-06-01 | Nec Electronics Corp | 半導体装置 |
| JP2006120852A (ja) * | 2004-10-21 | 2006-05-11 | Matsushita Electric Ind Co Ltd | 半導体装置及びその製造方法 |
| US7598573B2 (en) * | 2004-11-16 | 2009-10-06 | Robert Paul Masleid | Systems and methods for voltage distribution via multiple epitaxial layers |
| US7667288B2 (en) * | 2004-11-16 | 2010-02-23 | Masleid Robert P | Systems and methods for voltage distribution via epitaxial layers |
| JP2007005763A (ja) * | 2005-05-26 | 2007-01-11 | Fujitsu Ltd | 半導体装置及びその製造方法及びに半導体装置の設計方法 |
| US7217962B1 (en) * | 2005-06-30 | 2007-05-15 | Transmeta Corporation | Wire mesh patterns for semiconductor devices |
| US7661086B1 (en) | 2005-06-30 | 2010-02-09 | Scott Pitkethly | Enhanced clock signal flexible distribution system and method |
| US7730440B2 (en) * | 2005-06-30 | 2010-06-01 | Scott Pitkethly | Clock signal distribution system and method |
| US7305647B1 (en) | 2005-07-28 | 2007-12-04 | Transmeta Corporation | Using standard pattern tiles and custom pattern tiles to generate a semiconductor design layout having a deep well structure for routing body-bias voltage |
| US7462903B1 (en) * | 2005-09-14 | 2008-12-09 | Spansion Llc | Methods for fabricating semiconductor devices and contacts to semiconductor devices |
| US7265041B2 (en) * | 2005-12-19 | 2007-09-04 | Micrel, Inc. | Gate layouts for transistors |
| JP4777082B2 (ja) * | 2006-02-13 | 2011-09-21 | 富士通セミコンダクター株式会社 | 半導体装置及びその製造方法 |
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| JP4819548B2 (ja) | 2006-03-30 | 2011-11-24 | 富士通セミコンダクター株式会社 | 半導体装置 |
| US8451951B2 (en) * | 2008-08-15 | 2013-05-28 | Ntt Docomo, Inc. | Channel classification and rate adaptation for SU-MIMO systems |
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| KR102052307B1 (ko) * | 2011-11-09 | 2019-12-04 | 스카이워크스 솔루션즈, 인코포레이티드 | 전계 효과 트랜지스터 구조 및 관련된 무선-주파수 스위치 |
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Also Published As
| Publication number | Publication date |
|---|---|
| CN101604663A (zh) | 2009-12-16 |
| US20080136499A1 (en) | 2008-06-12 |
| JP4688501B2 (ja) | 2011-05-25 |
| CN100502005C (zh) | 2009-06-17 |
| US20170194421A9 (en) | 2017-07-06 |
| US7211478B1 (en) | 2007-05-01 |
| WO2004061967A2 (en) | 2004-07-22 |
| US20080135905A1 (en) | 2008-06-12 |
| US9251865B2 (en) | 2016-02-02 |
| WO2004061967A3 (en) | 2004-09-16 |
| US7332763B1 (en) | 2008-02-19 |
| US8415730B2 (en) | 2013-04-09 |
| US7863688B2 (en) | 2011-01-04 |
| AU2003300399A1 (en) | 2004-07-29 |
| US20160163793A1 (en) | 2016-06-09 |
| US7645664B1 (en) | 2010-01-12 |
| US7098512B1 (en) | 2006-08-29 |
| AU2003300399A8 (en) | 2004-07-29 |
| CN1732571A (zh) | 2006-02-08 |
| US6936898B2 (en) | 2005-08-30 |
| JP2006512774A (ja) | 2006-04-13 |
| US20040124475A1 (en) | 2004-07-01 |
| US20100072575A1 (en) | 2010-03-25 |
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