CN100435240C - 半导体器件 - Google Patents

半导体器件 Download PDF

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CN100435240C
CN100435240C CNB2004100696230A CN200410069623A CN100435240C CN 100435240 C CN100435240 C CN 100435240C CN B2004100696230 A CNB2004100696230 A CN B2004100696230A CN 200410069623 A CN200410069623 A CN 200410069623A CN 100435240 C CN100435240 C CN 100435240C
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安藤亮一
植本彰
垣内俊雄
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Sanyo Electric Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
    • H01L27/0921—Means for preventing a bipolar, e.g. thyristor, action between the different transistor regions, e.g. Latchup prevention
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
    • H01L27/0928—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors comprising both N- and P- wells in the substrate, e.g. twin-tub

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Abstract

提供一种三重阱构造的CMOS半导体器件，通过防止寄生可控硅的导通来防止发生锁定，可缩小布线面积。该半导体器件包括：P型硅衬底(20)、在P型硅衬底(20)的表面上互相间隔形成的N型的深阱(13)和N型的深阱(14)、在N型的深阱(13)上形成的P型阱(11)、在N型的深阱(14)内形成的N型的浅阱(12)、在P型阱(11)的表面上形成的N沟道型MOS晶体管(Mn)、以及在N型的浅阱(12)的表面上形成的P沟道型MOS晶体管(Mp)。

Description

半导体器件
技术领域
本发明涉及CMOS半导体器件，特别涉及三重阱构造的CMOS半导体器件中的锁定(Latch up)对策。
背景技术
以往已知三重阱构造的CMOS半导体器件。图4是表示这样的三重阱构造的CMOS半导体器件的断面图。
20是P型硅衬底。21是N型的深阱，形成在P型硅衬底20的表面上。22是P型阱，形成在N型的深阱21内。23是N型的浅阱，与P型阱22相邻，形成在N型的深阱21的表面上。24是N+层，形成在N型的深阱21的端部的表面。N+层24被施加电源电位VDD。
由此，在P型阱22的表面上形成N沟道型MOS晶体管Mn，同时在N型的浅阱23的表面上形成P沟道型MOS晶体管Mp。
N沟道型MOS晶体管Mn由在P型阱22的表面上形成的漏极27、栅极氧化膜、栅极电极28、源极29构成。25是P+层，形成在P型阱22的表面。P+层25连接到接地电压VSS，将P型阱22的电位设定为接地电压VSS。
P沟道型MOS晶体管Mp由在N型的深阱21的表面上形成的源极30、栅极氧化膜、栅极电极31、漏极32构成。N+层26连接到电源电位VDD，将N型的浅阱23的电位设定为电源电位VDD。
这样，在现有的三重阱构造的CMOS半导体器件中，在一个N型的深阱21之中形成P型阱22和N型的浅阱23。
再有，作为现有技术文献有以下的专利文献1。
[专利文献1](日本)特开2002-222869号公报
但是，现有的三重阱构造的CMOS半导体器件中，由于寄生性的双极晶体管而形成可控硅，有对锁定弱的问题。下面详细说明该问题。
如图4所示，寄生性的双极晶体管Bip41由N型的浅阱23、源极30、P型阱22构成。N型的浅阱23作为基极、源极30作为发射极、P型阱22作为集电极而形成PNP型双极晶体管Bip41。
此外，寄生性的双极晶体管Bip42由浅的P型阱22、源极29、N型的浅阱23构成。P型阱22作为基极、源极29作为发射极、N型的浅阱23作为集电极而形成NPN型双极晶体管Bip42。
因此，如图5所示，通过寄生性的双极晶体管Bip41和寄生性的双极晶体管Bip42而形成为锁定的原因的寄生可控硅构造。为了防止锁定，以往采用将双极晶体管Bip41、Bip42的基极宽度WB1、WB2(参照图4)加宽的对策。但是，如果加宽基极宽度WB1、WB2，则布线面积增大。
发明内容
因此，本发明的目的在于提供一种三重阱构造的CMOS半导体器件，通过防止寄生可控硅的导通来防止锁定，可缩小布线面积。
本发明的CMOS半导体器件，其特征在于包括：第一导电型半导体衬底；在所述半导体衬底的表面上互相间隔形成的第二导电型的第一阱和第二阱；在所述第一阱内形成的第一导电型的第三阱；在所述第二阱内形成的第二导电型的第四阱；在所述第三阱的表面上形成的第二导电沟道型MOS晶体管；以及在所述第四阱的表面上形成的第一导电沟道型MOS晶体管，其中，所述第二导电型为所述第一导电型相反的导电型，所述第二导电沟道型为与所述第一导电沟道型相反的导电沟道型。
本发明的三重阱构造的CMOS半导体器件通过将N型的深阱21分离，使寄生可控硅不导通，可提高锁定强度。
依据本发明，在三重阱构造的CMOS半导体器件中，可防止锁定，同时可缩小图形面积。
附图说明
图1是本发明的实施方式的三重阱构造的CMOS半导体器件的断面图。
图2是本发明的实施方式的三重阱构造的CMOS半导体器件的断面图。
图3是表示本发明的实施方式的三重阱构造中的寄生性双极晶体管的连接关系的电路图。
图4是现有的三重阱构造的CMOS半导体器件的断面图。
图5是表示现有的三重阱构造中的寄生性双极晶体管的连接关系的电路图。
具体实施方式
下面参照附图详细说明本发明的实施方式。
图1是实施方式的CMOS半导体器件的断面图。
在图1中，对与图4相同的构成部分付与相同的标号并省略其说明。13是N型的深阱，形成在P型硅衬底20的表面上。11是P型阱，形成在N型的深阱13内。14是N型的深阱，形成在P型硅衬底20的表面上。12是N型的浅阱，形成在N型的深阱14内。由此，在P型阱11的表面上形成N沟道型MOS晶体管Mn，在N型的浅阱12的表面上形成P沟道型MOS晶体管Mp。
本实施方式的特征点在于N型的深阱13和N型的深阱14间隔。由此，防止寄生可控硅的导通，可防止锁定。此外，由于不将相当于现有技术的基极宽度WB1、WB2的距离D1、D2加宽(WB1＞D1、WB2＞D2)就可防止锁定，可缩小布线面积。下面详细说明本实施方式中寄生可控硅不导通的原因。
图2是表示形成的寄生性双极晶体管的样子的断面图。图3是表示图2的寄生性双极晶体管的连接的电路图。
在图2、图3中示出寄生性双极晶体管Bip1、寄生性双极晶体管Bip2、寄生性双极晶体管Bip3、寄生性双极晶体管Bip4。
寄生性的双极晶体管Bip1由N型的浅阱12以及N型的深阱14、源极30、P型硅衬底20构成。N型的浅阱12以及N型的深阱14作为基极、源极30作为发射极、P型硅衬底20作为集电极而形成PNP型双极晶体管Bip1。
此外，寄生性的双极晶体管Bip2由P型硅衬底20、N型的深阱13、N型的浅阱12以及N型的深阱14构成。P型硅衬底20作为基极、N型的深阱13作为发射极、N型的浅阱12以及N型的深阱14作为集电极而形成NPN型双极晶体管。
此外，寄生性的双极晶体管Bip3由P型阱11、源极29、N型的深阱13构成。P型阱11作为基极、源极29作为发射极、N型的深阱13作为集电极而形成NPN型双极晶体管Bip3。
此外，寄生性的双极晶体管Bip4由N型的深阱13、P型阱11、P型硅衬底20构成。N型的深阱13作为基极、P型阱11作为发射极、P型硅衬底20作为集电极而形成PNP型双极晶体管Bip4。
如图3所示，由寄生晶体管Bip1和Bip2形成寄生可控硅，但由于其两端电位都是VDD，所以寄生可控硅不导通。因此，可防止锁定的发生，可缩小布线面积。此外，在本实施方式中，两个N型的深阱13、14被以相同电位(电源电位VDD)偏置。
即，本实施方式不是将以相同电位偏置的两个N型的深阱13、14一体化，而是通过相互间隔来防止锁定的发生。

Claims (2)

1.一种CMOS半导体器件，其特征在于包括：
第一导电型半导体衬底；在所述半导体衬底的表面上互相间隔形成的第二导电型的第一阱和第二阱；在所述第一阱内形成的第一导电型的第三阱；在所述第二阱内形成的第二导电型的第四阱；在所述第三阱的表面上形成的第二导电沟道型MOS晶体管；以及在所述第四阱的表面上形成的第一导电沟道型MOS晶体管，
其中，所述第二导电型为所述第一导电型相反的导电型，所述第二导电沟道型为与所述第一导电沟道型相反的导电沟道型。
2.如权利要求1所述的CMOS半导体器件，其特征在于，将所述第一阱和所述第二阱以相同电位偏置。
CNB2004100696230A 2003-08-06 2004-07-15 半导体器件 Expired - Fee Related CN100435240C (zh)

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US7345345B2 (en) 2008-03-18
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KR20050016107A (ko) 2005-02-21
JP5079974B2 (ja) 2012-11-21
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TW200507236A (en) 2005-02-16
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