CN100435240C - 半导体器件 - Google Patents

半导体器件 Download PDF

Info

Publication number
CN100435240C
CN100435240C CNB2004100696230A CN200410069623A CN100435240C CN 100435240 C CN100435240 C CN 100435240C CN B2004100696230 A CNB2004100696230 A CN B2004100696230A CN 200410069623 A CN200410069623 A CN 200410069623A CN 100435240 C CN100435240 C CN 100435240C
Authority
CN
China
Prior art keywords
type
trap
semiconductor device
forms
deep
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
CNB2004100696230A
Other languages
English (en)
Other versions
CN1581354A (zh
Inventor
安藤亮一
植本彰
垣内俊雄
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sanyo Electric Co Ltd
Original Assignee
Sanyo Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sanyo Electric Co Ltd filed Critical Sanyo Electric Co Ltd
Publication of CN1581354A publication Critical patent/CN1581354A/zh
Application granted granted Critical
Publication of CN100435240C publication Critical patent/CN100435240C/zh
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
    • H01L27/0921—Means for preventing a bipolar, e.g. thyristor, action between the different transistor regions, e.g. Latchup prevention
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
    • H01L27/0928—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors comprising both N- and P- wells in the substrate, e.g. twin-tub

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Abstract

提供一种三重阱构造的CMOS半导体器件，通过防止寄生可控硅的导通来防止发生锁定，可缩小布线面积。该半导体器件包括：P型硅衬底(20)、在P型硅衬底(20)的表面上互相间隔形成的N型的深阱(13)和N型的深阱(14)、在N型的深阱(13)上形成的P型阱(11)、在N型的深阱(14)内形成的N型的浅阱(12)、在P型阱(11)的表面上形成的N沟道型MOS晶体管(Mn)、以及在N型的浅阱(12)的表面上形成的P沟道型MOS晶体管(Mp)。

Description

半导体器件
技术领域
本发明涉及CMOS半导体器件，特别涉及三重阱构造的CMOS半导体器件中的锁定(Latch up)对策。
背景技术
以往已知三重阱构造的CMOS半导体器件。图4是表示这样的三重阱构造的CMOS半导体器件的断面图。
20是P型硅衬底。21是N型的深阱，形成在P型硅衬底20的表面上。22是P型阱，形成在N型的深阱21内。23是N型的浅阱，与P型阱22相邻，形成在N型的深阱21的表面上。24是N+层，形成在N型的深阱21的端部的表面。N+层24被施加电源电位VDD。
由此，在P型阱22的表面上形成N沟道型MOS晶体管Mn，同时在N型的浅阱23的表面上形成P沟道型MOS晶体管Mp。
N沟道型MOS晶体管Mn由在P型阱22的表面上形成的漏极27、栅极氧化膜、栅极电极28、源极29构成。25是P+层，形成在P型阱22的表面。P+层25连接到接地电压VSS，将P型阱22的电位设定为接地电压VSS。
P沟道型MOS晶体管Mp由在N型的深阱21的表面上形成的源极30、栅极氧化膜、栅极电极31、漏极32构成。N+层26连接到电源电位VDD，将N型的浅阱23的电位设定为电源电位VDD。
这样，在现有的三重阱构造的CMOS半导体器件中，在一个N型的深阱21之中形成P型阱22和N型的浅阱23。
再有，作为现有技术文献有以下的专利文献1。
[专利文献1](日本)特开2002-222869号公报
但是，现有的三重阱构造的CMOS半导体器件中，由于寄生性的双极晶体管而形成可控硅，有对锁定弱的问题。下面详细说明该问题。
如图4所示，寄生性的双极晶体管Bip41由N型的浅阱23、源极30、P型阱22构成。N型的浅阱23作为基极、源极30作为发射极、P型阱22作为集电极而形成PNP型双极晶体管Bip41。
此外，寄生性的双极晶体管Bip42由浅的P型阱22、源极29、N型的浅阱23构成。P型阱22作为基极、源极29作为发射极、N型的浅阱23作为集电极而形成NPN型双极晶体管Bip42。
因此，如图5所示，通过寄生性的双极晶体管Bip41和寄生性的双极晶体管Bip42而形成为锁定的原因的寄生可控硅构造。为了防止锁定，以往采用将双极晶体管Bip41、Bip42的基极宽度WB1、WB2(参照图4)加宽的对策。但是，如果加宽基极宽度WB1、WB2，则布线面积增大。
发明内容
因此，本发明的目的在于提供一种三重阱构造的CMOS半导体器件，通过防止寄生可控硅的导通来防止锁定，可缩小布线面积。
本发明的CMOS半导体器件，其特征在于包括：第一导电型半导体衬底；在所述半导体衬底的表面上互相间隔形成的第二导电型的第一阱和第二阱；在所述第一阱内形成的第一导电型的第三阱；在所述第二阱内形成的第二导电型的第四阱；在所述第三阱的表面上形成的第二导电沟道型MOS晶体管；以及在所述第四阱的表面上形成的第一导电沟道型MOS晶体管，其中，所述第二导电型为所述第一导电型相反的导电型，所述第二导电沟道型为与所述第一导电沟道型相反的导电沟道型。
本发明的三重阱构造的CMOS半导体器件通过将N型的深阱21分离，使寄生可控硅不导通，可提高锁定强度。
依据本发明，在三重阱构造的CMOS半导体器件中，可防止锁定，同时可缩小图形面积。
附图说明
图1是本发明的实施方式的三重阱构造的CMOS半导体器件的断面图。
图2是本发明的实施方式的三重阱构造的CMOS半导体器件的断面图。
图3是表示本发明的实施方式的三重阱构造中的寄生性双极晶体管的连接关系的电路图。
图4是现有的三重阱构造的CMOS半导体器件的断面图。
图5是表示现有的三重阱构造中的寄生性双极晶体管的连接关系的电路图。
具体实施方式
下面参照附图详细说明本发明的实施方式。
图1是实施方式的CMOS半导体器件的断面图。
在图1中，对与图4相同的构成部分付与相同的标号并省略其说明。13是N型的深阱，形成在P型硅衬底20的表面上。11是P型阱，形成在N型的深阱13内。14是N型的深阱，形成在P型硅衬底20的表面上。12是N型的浅阱，形成在N型的深阱14内。由此，在P型阱11的表面上形成N沟道型MOS晶体管Mn，在N型的浅阱12的表面上形成P沟道型MOS晶体管Mp。
本实施方式的特征点在于N型的深阱13和N型的深阱14间隔。由此，防止寄生可控硅的导通，可防止锁定。此外，由于不将相当于现有技术的基极宽度WB1、WB2的距离D1、D2加宽(WB1＞D1、WB2＞D2)就可防止锁定，可缩小布线面积。下面详细说明本实施方式中寄生可控硅不导通的原因。
图2是表示形成的寄生性双极晶体管的样子的断面图。图3是表示图2的寄生性双极晶体管的连接的电路图。
在图2、图3中示出寄生性双极晶体管Bip1、寄生性双极晶体管Bip2、寄生性双极晶体管Bip3、寄生性双极晶体管Bip4。
寄生性的双极晶体管Bip1由N型的浅阱12以及N型的深阱14、源极30、P型硅衬底20构成。N型的浅阱12以及N型的深阱14作为基极、源极30作为发射极、P型硅衬底20作为集电极而形成PNP型双极晶体管Bip1。
此外，寄生性的双极晶体管Bip2由P型硅衬底20、N型的深阱13、N型的浅阱12以及N型的深阱14构成。P型硅衬底20作为基极、N型的深阱13作为发射极、N型的浅阱12以及N型的深阱14作为集电极而形成NPN型双极晶体管。
此外，寄生性的双极晶体管Bip3由P型阱11、源极29、N型的深阱13构成。P型阱11作为基极、源极29作为发射极、N型的深阱13作为集电极而形成NPN型双极晶体管Bip3。
此外，寄生性的双极晶体管Bip4由N型的深阱13、P型阱11、P型硅衬底20构成。N型的深阱13作为基极、P型阱11作为发射极、P型硅衬底20作为集电极而形成PNP型双极晶体管Bip4。
如图3所示，由寄生晶体管Bip1和Bip2形成寄生可控硅，但由于其两端电位都是VDD，所以寄生可控硅不导通。因此，可防止锁定的发生，可缩小布线面积。此外，在本实施方式中，两个N型的深阱13、14被以相同电位(电源电位VDD)偏置。
即，本实施方式不是将以相同电位偏置的两个N型的深阱13、14一体化，而是通过相互间隔来防止锁定的发生。

Claims (2)

1.一种CMOS半导体器件，其特征在于包括：
第一导电型半导体衬底；在所述半导体衬底的表面上互相间隔形成的第二导电型的第一阱和第二阱；在所述第一阱内形成的第一导电型的第三阱；在所述第二阱内形成的第二导电型的第四阱；在所述第三阱的表面上形成的第二导电沟道型MOS晶体管；以及在所述第四阱的表面上形成的第一导电沟道型MOS晶体管，
其中，所述第二导电型为所述第一导电型相反的导电型，所述第二导电沟道型为与所述第一导电沟道型相反的导电沟道型。
2.如权利要求1所述的CMOS半导体器件，其特征在于，将所述第一阱和所述第二阱以相同电位偏置。
CNB2004100696230A 2003-08-06 2004-07-15 半导体器件 Expired - Fee Related CN100435240C (zh)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP2003288153 2003-08-06
JP288153/2003 2003-08-06
JP288153/03 2003-08-06

Publications (2)

Publication Number Publication Date
CN1581354A CN1581354A (zh) 2005-02-16
CN100435240C true CN100435240C (zh) 2008-11-19

Family

ID=34213282

Family Applications (1)

Application Number Title Priority Date Filing Date
CNB2004100696230A Expired - Fee Related CN100435240C (zh) 2003-08-06 2004-07-15 半导体器件

Country Status (5)

Country Link
US (1) US7345345B2 (zh)
JP (1) JP5079974B2 (zh)
KR (1) KR100749231B1 (zh)
CN (1) CN100435240C (zh)
TW (1) TWI256724B (zh)

Families Citing this family (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4530823B2 (ja) * 2004-12-02 2010-08-25 三洋電機株式会社 半導体装置及びその製造方法
WO2006127751A2 (en) * 2005-05-23 2006-11-30 Amalfi Semiconductor, Inc. Electrically isolated cmos device
CN101238580B (zh) * 2005-08-18 2010-06-16 富士通微电子株式会社 半导体器件及其制造方法
KR100688588B1 (ko) 2006-02-27 2007-03-02 삼성전자주식회사 래치-업의 발생을 방지할 수 있는 ｃｍｏｓ 반도체 장치
JP5036234B2 (ja) 2006-07-07 2012-09-26 三菱電機株式会社 半導体装置
US7847581B2 (en) * 2008-04-03 2010-12-07 Stmicroelectronics (Rousset) Sas Device for protecting an integrated circuit against a laser attack
JP5259246B2 (ja) * 2008-05-09 2013-08-07 ルネサスエレクトロニクス株式会社 半導体装置
DE102008047850B4 (de) * 2008-09-18 2015-08-20 Austriamicrosystems Ag Halbleiterkörper mit einer Schutzstruktur und Verfahren zum Herstellen derselben
JP5896682B2 (ja) 2011-10-18 2016-03-30 ルネサスエレクトロニクス株式会社 半導体集積回路装置
US9287253B2 (en) * 2011-11-04 2016-03-15 Synopsys, Inc. Method and apparatus for floating or applying voltage to a well of an integrated circuit
JP5725230B2 (ja) * 2014-04-09 2015-05-27 株式会社デンソー 半導体装置
JP6118923B2 (ja) * 2016-01-26 2017-04-19 ルネサスエレクトロニクス株式会社 半導体集積回路装置
US9633992B1 (en) * 2016-02-23 2017-04-25 Vanguard International Semiconductor Corporation Electrostatic discharge protection device
CN108878417B (zh) * 2018-07-05 2020-10-30 江南大学 一种高维持mos辅助触发scr结构的瞬态电压抑制器
KR102482194B1 (ko) * 2018-08-24 2022-12-27 삼성전기주식회사 삽입손실이 개선된 cmos 트랜지스터의 배치 구조
CN110534512B (zh) * 2019-09-07 2023-02-07 电子科技大学 一种抗闩锁版图结构

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1228611A (zh) * 1998-03-05 1999-09-15 日本电气株式会社 三重阱结构的半导体集成电路的制造方法
US20020117713A1 (en) * 2001-01-23 2002-08-29 Akio Kitamura Semiconductor integrated circuit device and manufacture method therefore

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62155555A (ja) * 1985-09-18 1987-07-10 Sony Corp 相補型ｍｏｓトランジスタ
US4761571A (en) * 1985-12-19 1988-08-02 Honeywell Inc. Memory circuit enchancement to stablize the signal lines with additional capacitance
JPH05326862A (ja) * 1992-05-14 1993-12-10 Fujitsu Ltd 半導体装置
KR940003026A (ko) * 1992-07-13 1994-02-19 김광호 트리플웰을 이용한 반도체장치
JPH06232355A (ja) * 1993-02-02 1994-08-19 Hitachi Ltd Ｍｏｓ半導体製造装置
JPH08149011A (ja) * 1994-11-18 1996-06-07 Mitsubishi Electric Corp 電流加算型ディジタル／アナログ変換器
JP3419672B2 (ja) 1997-12-19 2003-06-23 富士通株式会社 半導体装置及びその製造方法
JP2000101045A (ja) * 1998-07-23 2000-04-07 Mitsubishi Electric Corp 半導体装置
KR20000041323A (ko) * 1998-12-22 2000-07-15 윤종용 트리플 웰 구조를 갖는 반도체 장치의 제조 방법
US6432761B1 (en) * 1999-10-01 2002-08-13 Microchip Technology Incorporated Apparatus and method for independent threshold voltage control of memory cell and select gate in a split-EEPROM
US6376870B1 (en) * 2000-09-08 2002-04-23 Texas Instruments Incorporated Low voltage transistors with increased breakdown voltage to substrate
US6791883B2 (en) * 2002-06-24 2004-09-14 Freescale Semiconductor, Inc. Program and erase in a thin film storage non-volatile memory

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1228611A (zh) * 1998-03-05 1999-09-15 日本电气株式会社 三重阱结构的半导体集成电路的制造方法
US20020117713A1 (en) * 2001-01-23 2002-08-29 Akio Kitamura Semiconductor integrated circuit device and manufacture method therefore

Also Published As

Publication number Publication date
US7345345B2 (en) 2008-03-18
KR20050016107A (ko) 2005-02-21
KR100749231B1 (ko) 2007-08-13
US20050045953A1 (en) 2005-03-03
CN1581354A (zh) 2005-02-16
TWI256724B (en) 2006-06-11
JP2005072566A (ja) 2005-03-17
TW200507236A (en) 2005-02-16
JP5079974B2 (ja) 2012-11-21

Similar Documents

Publication Publication Date Title
CN100435240C (zh) 半导体器件
US5376816A (en) Bi-cmos integrated circuit device having buried region use in common for bipolar and mos transistors
KR890004472B1 (ko) Cmos 집적회호
JP2959528B2 (ja) 保護回路
KR100243496B1 (ko) 반도체 장치
TW200410393A (en) Electrostatic discharge protection device for mixed voltage interface
KR970053865A (ko) 반도체장치
US5357126A (en) MOS transistor with an integrated protection zener diode
KR100379286B1 (ko) 보호 회로를 구비한 반도체 장치
US6940104B2 (en) Cascaded diode structure with deep N-well and method for making the same
US6855964B2 (en) Triggering of an ESD NMOS through the use of an N-type buried layer
JP2002134752A (ja) 半導体装置
TW426973B (en) Latch up protection circuit and its method suitable for use in multi power supply integrated circuit
JPS6197858A (ja) 半導体装置
US6084272A (en) Electrostatic discharge protective circuit for semiconductor device
JPH044755B2 (zh)
JPS61283158A (ja) 相補型ｍｏｓトランジスタ回路
JPS63252464A (ja) 半導体装置
KR100304950B1 (ko) 씨모스 및 그의 제조방법
CN101271894B (zh) 半导体装置
JPS62123739A (ja) 半導体集積回路装置
JP2726454B2 (ja) Ｂｉ−ＣＭＯＳ型半導体メモリ装置
JPH10223846A (ja) 入出力保護回路
JPH059943B2 (zh)
EP1047133A1 (en) Method for producing devices for control circuits integrated in power devices

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C14 Grant of patent or utility model
GR01 Patent grant
CF01 Termination of patent right due to non-payment of annual fee
CF01 Termination of patent right due to non-payment of annual fee

Granted publication date: 20081119

Termination date: 20210715