CN101199037A - 使用含碳硅和锗化硅外延源/漏极的高性能应力增强金属氧化物半导体场效应晶体管及制造方法 - Google Patents
使用含碳硅和锗化硅外延源/漏极的高性能应力增强金属氧化物半导体场效应晶体管及制造方法 Download PDFInfo
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Abstract
一种半导体器件和制造半导体器件的方法。所述半导体器件包括pFET和nFET的沟道。在pFET沟道的源极和漏极区中选择性地生长SiGe层,且在nFET沟道的源极和漏极区中选择性地生长Si:C层。SiGe和Si:C层匹配下面的Si层的晶格网络以产生应力分量。在一个实施例中,这导致在pFET沟道中的压应力分量和在nFET沟道中的拉应力分量。
Description
技术领域
本发明总体涉及一种半导体器件及制造方法,更具体而言,涉及一种半导体器件及制造方法,其在器件制造过程中在器件中施加拉应力和压应力。
背景技术
半导体器件衬底内的机械应力可以调节器件性能。即,已知半导体器件内的应力提高了半导体器件的特性。因此,为了改善半导体器件的特性,在n型器件(例如,NFET)和/或p型器件(例如,PFET)的沟道中产生了拉应力和/或压应力。然而,相同的应力分量,无论是拉应力或是压应力,有差别地影响n型器件和p型器件的特性。
例如,公知当器件形成于硅层(或盖)上,且该硅层(或盖)外延生长在另一外延生长的SiGe层上,且SiGe层在硅衬底的顶部上应力松弛时,器件表现出更好的性能特性。在该系统中,硅盖经历了双轴拉应变。当未松弛的SiGe层外延生长于硅上时,其将具有与硅衬底一致的晶格常数。在(通过例如高温工艺)松弛之后,SiGe晶格常数接近其本征晶格常数,该本征晶格常数大于硅的晶格常数。完全松弛的SiGe层具有接近其本征值的晶格常数。当在其上外延生长硅层时,硅层与松弛的SiGe层的较大晶格常数一致,且这对于形成于其上的硅层施加了物理双轴应力(例如,扩张)。该施加到硅层的物理应力是有利于形成于其上的器件(例如,CMOS器件)的,因为扩张的硅层增强了N型器件性能,且SiGe层中较高的Ge浓度改善了P型器件性能。
硅衬底上的SiGe中的松弛通过形成错配位错来产生。对于完全松弛的衬底,可以设想有等距分开的错配位错的网格,其松弛了应力。错配位错通过在衬底中提供了额外的硅半平面从而促进了SiGe层中的晶格常数趋向其本征值。然后,调节SiGe/硅界面之间的失配应力,且SiGe晶格常数被允许变大。
然而,该常规方法的问题在于其需要非常厚(例如,大致5000到15000的厚度)的多层SiGe缓冲层以在其表面部分实现错配位错,同时需要避免SiGe层和硅衬底层之间的螺位错,由此在多层SiGe层的表面上实现松弛的SiGe结构。而且,该方法显著增加了制造时间和成本。另外,厚的分层SiGe缓冲层不能容易地应用于绝缘体上硅衬底(SOI)。这是因为对于绝缘体上硅,为了SOI有效的益处,硅厚度必须小于1500。SiGe缓冲层晶格太厚了。
另一问题在于形成于SiGe层和硅外延层之间的错配位错是随机的且是高度不均匀的,且由于异相成核不能被容易地控制,所以错配位错不能被容易地控制。而且,错配位错密度从一个位置到另一位置显著不同。因此,从非均匀的错配位错引起的物理应力趋于在硅外延层中也高度不均匀,且该不均匀应力导致了具有更大可变性的对于性能的不均匀益处。另外,在错配密度高的那些位置,所述缺陷通过短路器件端子和通过其它显著的泄漏机制从而降低了器件性能。
此外,已知在固有具有拉应力的Si上外延生长Si:C。Si:C/Si材料叠层中1%的C含量可以导致在Si:C中500MPa量级的拉应力水平。比较而言,在SiGe/Si系统中,则需要约6%的Ge来导致500MPa的压应力。如Ernst等在VLSI Symp.,2002,p92中所示,可以在外延生长期间,将这1%水平的C引入Si中。在Ernst等的文献中,显示了nFET的Si/Si:C/Si层状沟道。然而,在Ernst等的文献的结构中,在常规的有应变的Si的方法中提供Si:C作为沟道中的叠层。因此,在Ernst等的文献的结构中,Si:C自身被用作部分的沟道。该方法的问题在于迁移率没有被提高,反而根据C含量由散射而被阻碍了。
发明内容
在本发明的第一方面,一种制造半导体结构的方法包括:在衬底中形成p型场效应晶体管(pFET)沟道和n型场效应晶体管(nFET)沟道。在衬底上形成与各自的沟道相关的pFET堆体和nFET堆体。第一材料层提供在与pFET堆体相关的源极/漏极区。第一材料层具有与衬底的基晶格常数不同的晶格常数以在pFET沟道内产生压应力状态。第二材料层提供在与nFET堆体相关的源极/漏极区。第二材料层具有与衬底的基晶格常数不同的晶格常数以在nFET沟道内产生拉应力状态。
在本发明的另一方面中,提供了一种制造半导体结构的方法,所述方法包括:在衬底中形成p型场效应晶体管(pFET)沟道和n型场效应晶体管(nFET)沟道。在衬底上分别形成与pFET沟道和nFET沟道相关的pFET结构和nFET结构。将pFET结构和nFET结构的区域蚀刻到预定的深度。在pFET结构的蚀刻区域中提供了第一材料以在pFET沟道中产生压应力,第一材料具有与衬底的基晶格常数不同的晶格常数。在nFET结构的蚀刻区域中提供了第二材料以在nFET沟道中产生拉应力,第二材料具有与衬底的基晶格常数不同的晶格常数。提供nFET和pFET结构的掺杂源极和漏极区。
在本发明的又一方面中,半导体结构包括半导体衬底,且pFET和nFET形成于衬底中各自的沟道中。pFET沟道的源极和漏极区中的第一材料层具有与衬底的晶格常数不同的晶格常数。nFET沟道的源极和漏极区中的第二材料层具有与衬底的晶格常数不同的晶格常数。
附图说明
图1a到1e示出了根据本发明形成器件的制造工艺;
图2图示了根据本发明的pFET器件中应力的位置;以及
图3图示了根据本发明的nFET器件中应力的位置。
具体实施方式
本发明涉及半导体器件及制造方法,其接近CMOS器件的nFET沟道提供拉应力而接近CMOS器件的pFET沟道提供压应力。在本发明的一个实施例中,纵向拉应力非常接近nFET沟道而同时压应力非常接近pFET沟道。另外,在本发明中,提供了一种工艺和结构来将SiGe和Si:C材料集成入CMOS技术中。
例如,在硅衬底中在源极/漏极(S/D)区中提供了(例如,埋入)有高度拉应力的Si:C膜,以在纵向将拉应力施加到其栅极区下的沟道中的nFET结构上。相似地,在硅衬底中在S/D区中提供了(例如,埋入)有高度压应力的SiGe膜,以在纵向将压应力施加到其栅极区下的沟道中的pFET结构上。相似于SiGe层,Si:C层比较薄(在其临界厚度下),且没有松弛。nFET的晶体管沟道区通过来自Si:C层的应力而产生应变,而pFET的沟道区被提供有来自SiGe的压应力。
因为将SiGe层埋入pFET的S/D区,所以仍可以形成低电阻硅化物。有趣的是,埋入的(例如,表面下或与表面共平面)Si:C膜可以比表面上的Si:C对应部分施加更大的应力,因为该膜表面不是没有应力的。在本发明中,设想Si:C的不同厚度和突起,无论是埋入或与表面共平面或从平面升起。应可以理解通过调整SiGe层中Ge含量的浓度,可调整pFET沟道中的压应力。相似地,通过调整Si:C层中的C浓度,可以调整nFET沟道中的拉应力。这是因为这些材料的晶格常数。
在本发明中,显示了Si:C具有适当的应力,Si:C包含了适当的C含量,且Si:C可以外延和选择性地生长。而且,在本发明中,Si:C不用作沟道下直接构建的叠层,而是作为拉伸状态的nFET S/D区的替代材料,且因此在沟道区中施加了拉伸应力。因此该Si:C膜将拉应力施加到nFET沟道,同时SiGe将压应力施加到pFET沟道。
图1a到1e表现了根据本发明形成器件的制造工艺。在图1a中,提供了绝缘体上硅(SOI)20等。例如使用垫氧化、垫氮化物沉积、基于光刻的构图、由氮化物、氧化物和硅构成的堆体下至埋入氧化物的反应离子蚀刻(RIE)、边缘氧化、衬垫沉积、填充沉积和化学机械抛光,将层20构图以形成浅沟槽隔离(STI)部件25。STI形成工艺在本领域中是公知的。然后剥离垫氮化物。以任何公知的方式,栅极堆体形成于该结构上以形成pFET和nFET,栅极堆体例如包括栅极电介质和多晶硅。按照公知的方式为pFET和nFET形成TEOS盖43和44。
仍参考图1a,使用任何公知的工艺,在pFET和nFET堆体上分别形成分隔物。例如,分隔物38形成于pFET堆体40a的侧壁上,且分隔物42形成于pFET堆体45a的侧壁上。分隔物例如可以是氧化物或氮化物分隔物。
在图1b中,将薄衬垫50毯覆式沉积在例如包括pFET堆体、nFET堆体和其S/D区的结构上方。在一个实施例中,薄衬垫50是Si3N4衬垫或任何根据硬掩模材料的氮化物或氧化物基的材料。薄衬垫的厚度范围大致为5到20nm。薄衬垫50可以作为保护层。然后硬掩模51形成于nFET堆体45a和其S/D区上方。
将pFET堆体40a周围的区域蚀刻到衬垫50。然后将衬垫50蚀刻且相邻于堆体40a形成(蚀刻)S/D区52。根据SOI层的厚度,S/D区52的深度为约20到100nm。在pFET堆体40a的区52中生长有高度压应力的选择性外延SiGe层60,如图1c所示,完全填充S/D蚀刻的区52。SiGe层60可以被生长为约10到100nm的厚度,尽管由本发明也可以设想其它的厚度。在一个实施例中,SiGe层生长为高于栅极氧化物表面的厚度。使用任何公知的工艺,比如例如湿法化学工艺,去除硬掩模和衬垫的剩余部分。在工艺步骤中,在去除硬掩模之前,将掺杂剂离子注入以形成pFET堆体40a附近的S/D区。
独立而言,SiGe一般具有大于SOI的晶格常数。即,SiGe材料的晶格常数与Si的晶格常数不匹配。然而,在本发明的结构中,由于SiGe层的生长,SiGe层的晶格结构将趋于匹配下面的Si的晶格结构。这造成了SiGe层和与之相邻或相近的沟道区具有压应力。在一个实施例中,SiGe层的Ge含量对于Si含量的比例可以大于0%且更大。
仍参考本发明的工艺,在图1d中,例如再次在包括nFET、pFET和其S/D区的结构上方毯覆式沉积薄衬垫50。在一个实施例中,薄衬垫50是Si3N4衬垫或任何根据硬掩模材料的氮化物或氧化物材料。薄衬垫的厚度范围大致为5到20nm。薄衬垫50可以作为保护层。
然后掩模51形成于pFET堆体40a上方,且将nFET堆体45a周围的区域蚀刻到衬垫50。然后将衬垫50蚀刻且相邻于堆体45a形成(蚀刻)S/D区54。根据SOI层的厚度,S/D区54的深度为约20到100nm。可以使用任何公知的工艺来蚀刻区54。
在nFET堆体45a的区54中生长有高度拉应力的选择性外延Si:C层62,如图1e所示,Si:C层62被生长为约10到100nm的厚度。应当理解Si:C层62可以外延生长为其它厚度,如本发明所设想的。在一个实施例中,C含量对于硅含量的比例可以大于0到4%。使用任何公知的工艺,比如例如使用湿法化学工艺,去除抗蚀剂和薄衬垫的剩余部分。
独立而言,Si:C一般具有比下面的Si更小的晶格常数。即,Si:C材料的晶格常数与Si的晶格常数不匹配。然而,在本发明的结构中,由于Si:C层在nFET的堆体45a的S/D区内的生长,Si:C层的晶格结构将趋于匹配下面的Si的晶格结构。这造成Si:C层和与之相邻或相近的沟道区具有拉应力。
在一个实施例中,例如,通过进行RIE、湿法蚀刻或其它工艺或其组合,用于工艺优化以凹进这样的层,Si:C和/或SiGe层可以嵌入器件内。然后,使用任何公知工艺,Si选择性生长在区52和54的上方。然后可使用任何公知工艺进行源极和漏极注入。还可以进行进一步的工艺来构建器件和互连。
如现在可以理解的,Si:C和SiGe层可以被嵌入器件内,或可以与器件共平面,或可以从器件升起。在一个实施例中,Si:C和SiGe膜沉积为10到100nm的厚度,其提供了一种将(压或拉)应力增加到MOSFET的更有成本效率的方法。在升起的实施例中,Si:C和SiGe层可以在器件的表面上方升起约50nm。应认识到通过本发明也可以设想其它的厚度。
而且,还可以用P型掺杂剂原位掺杂SiGe且用n型掺杂剂原位掺杂Si:C来分别形成pFET和nFET的源极和漏极区。
本领域的普通技术人员应还理解可以相等地在图1b和1c所示的工艺步骤之前进行图1d和1e的工艺步骤。而且,可以进行比如例如标准离子注入的进一步工艺步骤来形成pFET和nFET的S/D区。由于在该工艺期间nFET和pFET区中的栅极氧化物作为掩模,通过离子注入形成S/D区是自对准的。
图2图示了根据本发明的pFET器件的应力的位置。如图2所示,直接在具有未松弛SiGe区的pFET下面出现了压应力。更具体而言,在本发明的结构中,SiGe层的晶格结构匹配下面的硅绝缘层的晶格结构。这造成SiGe层及周围区域处于压应力下。
图3图示了根据本发明的nFET器件的应力的位置。如图3所示,在nFET的沟道中出现了拉应力。更具体而言,在本发明的结构中,Si:C层的晶格结构匹配下面的硅绝缘层20的晶格结构以在nFET沟道中形成拉应力分量。
虽然就实施例描述了本发明,但是本领域的技术人员可以认识到本发明可以在修改的情况下且在权利要求的精神和范围内被实践。例如,本发明可以被容易地应用于体衬底。
Claims (21)
1.一种制造半导体结构的方法,包括的步骤为:
在衬底中形成p型场效应晶体管沟道和n型场效应晶体管沟道;
在p型场效应晶体管沟道中形成p型场效应晶体管堆体,在n型场效应晶体管沟道中形成n型场效应晶体管堆体;
在与p型场效应晶体管堆体相关的源极/漏极区提供第一材料层,所述第一材料层具有与所述衬底的基晶格常数不同的晶格常数以在p型场效应晶体管沟道内产生压应力状态;以及
在与n型场效应晶体管堆体相关的源极/漏极区提供第二材料层,所述第二材料层具有与所述衬底的基晶格常数不同的晶格常数以在n型场效应晶体管沟道内产生拉应力状态。
2.根据权利要求1所述的方法,其中所述第一材料层是SiGe,SiGe的Ge含量对于Si的比例大致大于0%。
3.根据权利要求1所述的方法,其中所述第二材料层是Si:C。
4.根据权利要求3所述的方法,其中所述Si:C的C含量为约4%或更小。
5.根据权利要求1所述的方法,其中所述第一材料层是未松弛的SiGe,且所述第二材料层是未松弛的Si:C且形成为约10到100nm之间的厚度。
6.根据权利要求1所述的方法,其中
通过将掩模放置在n型场效应晶体管沟道上方且蚀刻p型场效应晶体管的区域,以及在p型场效应晶体管沟道的区域内选择性地生长所述第一材料层,从而形成所述第一材料层;以及
通过将掩模放置在p型场效应晶体管沟道上方且蚀刻n型场效应晶体管的区域,以及在n型场效应晶体管沟道的区域内选择性地生长所述第二材料层,从而形成所述第二材料层。
7.根据权利要求6所述的方法,还包括的步骤为:
在蚀刻p型场效应晶体管堆体的区域和在选择性地生长所述第一材料层之前,在所述掩模下和所述p型场效应晶体管堆体上方提供保护层;以及
在蚀刻n型场效应晶体管堆体的区域和在选择性地生长所述第二材料层之前,在所述掩模下和所述n型场效应晶体管堆体上方提供保护层。
8.根据权利要求1所述的方法,其中所述第一材料层和所述第二材料层生长为约10到100nm的厚度。
9.根据权利要求1所述的方法,其中所述第一材料层和所述第二材料层嵌入所述层中。
10.一种制造半导体结构的方法,包括的步骤为:
在衬底中形成p型场效应晶体管沟道和n型场效应晶体管沟道;
在所述衬底上分别形成与p型场效应晶体管沟道和n型场效应晶体管沟道相关的p型场效应晶体管结构和n型场效应晶体管结构;
蚀刻p型场效应晶体管结构和n型场效应晶体管结构的区域;
在p型场效应晶体管结构的区域中形成第一材料以在p型场效应晶体管沟道中提供压应力,所述第一材料具有与所述衬底的基晶格常数不同的晶格常数;
在n型场效应晶体管结构的区域中形成第二材料以在n型场效应晶体管沟道中提供拉应力,所述第二材料具有与所述衬底的基晶格常数不同的晶格常数;以及
掺杂p型场效应晶体管结构和n型场效应晶体管结构的源极和漏极区。
11.根据权利要求10所述的方法,其中所述第一材料是SiGe,所述第二材料是Si:C。
12.根据权利要求11所述的方法,其中
所述第一材料在p型场效应晶体管沟道内产生压应力;以及
所述第二材料在n型场效应晶体管沟道内产生拉应力。
13.根据权利要求10所述的方法,其中
通过将保护层放置在n型场效应晶体管结构和p型场效应晶体管结构上方且在p型场效应晶体管沟道的源极和漏极区内生长所述第一材料,从而形成所述第一材料;以及
通过将保护层放置在p型场效应晶体管结构和p型场效应晶体管结构的源极和漏极区以及n型场效应晶体管结构上方,和在n型场效应晶体管沟道的源极和漏极区内生长所述第二材料,从而形成所述第二材料。
14.根据权利要求10所述的方法,其中所述第一材料和所述第二材料嵌入绝缘层中。
15.根据权利要求10所述的方法,其中所述第一材料和所述第二材料升起在绝缘层表面的上方。
16.根据权利要求10所述的方法,其中所述第一材料和所述第二材料生长为约10到100nm的厚度。
17.根据权利要求10所述的方法,其中所述第一材料是未松弛的SiGe。
18.根据权利要求10所述的方法,还包括的步骤为:用p型掺杂剂原位掺杂第一材料和用n型掺杂剂原位掺杂第二材料以分别形成p型场效应晶体管和n型场效应晶体管的源极和漏极区。
19.一种半导体结构,包括:
形成于衬底中的p型场效应晶体管沟道;
形成于所述衬底中的n型场效应晶体管沟道;
在p型场效应晶体管沟道的源极和漏极区中的第一材料层,所述第一材料层具有与所述衬底的晶格常数不同的晶格常数;以及
在n型场效应晶体管沟道的源极和漏极区中的第二材料层,所述第二材料层具有与所述衬底的晶格常数不同的晶格常数。
20.根据权利要求19所述的结构,其中所述第一材料层是SiGe且所述第二材料层是Si:C。
21.根据权利要求19所述的结构,其中所述第一材料层和所述第二材料层分别在p型场效应晶体管沟道和n型场效应晶体管沟道中产生了不同类型的应力。
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JP2007528593A (ja) | 2007-10-11 |
US20070296038A1 (en) | 2007-12-27 |
US20050082616A1 (en) | 2005-04-21 |
TW200525759A (en) | 2005-08-01 |
US9023698B2 (en) | 2015-05-05 |
WO2005043591A2 (en) | 2005-05-12 |
US20120196412A1 (en) | 2012-08-02 |
US8168489B2 (en) | 2012-05-01 |
US8901566B2 (en) | 2014-12-02 |
KR20060090828A (ko) | 2006-08-16 |
US7303949B2 (en) | 2007-12-04 |
US9401424B2 (en) | 2016-07-26 |
TWI351762B (en) | 2011-11-01 |
US20140322873A1 (en) | 2014-10-30 |
EP1676297A4 (en) | 2008-06-25 |
KR100985935B1 (ko) | 2010-10-06 |
US20070264783A1 (en) | 2007-11-15 |
CN100562972C (zh) | 2009-11-25 |
WO2005043591A3 (en) | 2007-06-21 |
EP1676297A2 (en) | 2006-07-05 |
WO2005043591A8 (en) | 2005-11-03 |
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