CN101126794A - 集成电路 - Google Patents
集成电路 Download PDFInfo
- Publication number
- CN101126794A CN101126794A CNA2007101030343A CN200710103034A CN101126794A CN 101126794 A CN101126794 A CN 101126794A CN A2007101030343 A CNA2007101030343 A CN A2007101030343A CN 200710103034 A CN200710103034 A CN 200710103034A CN 101126794 A CN101126794 A CN 101126794A
- Authority
- CN
- China
- Prior art keywords
- circuit
- data
- input
- output
- write data
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000012360 testing method Methods 0.000 claims abstract description 256
- 238000013500 data storage Methods 0.000 claims abstract description 10
- 230000008676 import Effects 0.000 claims description 9
- 230000008859 change Effects 0.000 claims description 2
- 241001269238 Data Species 0.000 description 22
- 238000010586 diagram Methods 0.000 description 22
- 102100027473 Cartilage oligomeric matrix protein Human genes 0.000 description 16
- 101710176668 Cartilage oligomeric matrix protein Proteins 0.000 description 16
- 230000003534 oscillatory effect Effects 0.000 description 12
- 239000000872 buffer Substances 0.000 description 11
- 230000000694 effects Effects 0.000 description 9
- 230000005055 memory storage Effects 0.000 description 7
- 230000000630 rising effect Effects 0.000 description 7
- 239000004065 semiconductor Substances 0.000 description 7
- 230000005540 biological transmission Effects 0.000 description 5
- 230000000052 comparative effect Effects 0.000 description 4
- 230000006870 function Effects 0.000 description 4
- 230000007274 generation of a signal involved in cell-cell signaling Effects 0.000 description 4
- 238000012544 monitoring process Methods 0.000 description 4
- 238000005516 engineering process Methods 0.000 description 3
- 238000000034 method Methods 0.000 description 3
- 206010019133 Hangover Diseases 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 101150016099 omcA gene Proteins 0.000 description 2
- 230000001360 synchronised effect Effects 0.000 description 2
- 239000002699 waste material Substances 0.000 description 2
- 241000269435 Rana <genus> Species 0.000 description 1
- 101100428373 Saccharomyces cerevisiae (strain ATCC 204508 / S288c) POR1 gene Proteins 0.000 description 1
- 101150101561 TOM70 gene Proteins 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 230000003111 delayed effect Effects 0.000 description 1
- 238000007599 discharging Methods 0.000 description 1
- 101150087557 omcB gene Proteins 0.000 description 1
- 101150115693 ompA gene Proteins 0.000 description 1
- 101150090944 otomp gene Proteins 0.000 description 1
- 230000008569 process Effects 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 238000012546 transfer Methods 0.000 description 1
- 230000001960 triggered effect Effects 0.000 description 1
Images
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
- G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
- G11C29/14—Implementation of control logic, e.g. test mode decoders
Abstract
Description
Claims (14)
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2006-223281 | 2006-08-18 | ||
JP2006223281 | 2006-08-18 | ||
JP2006223281A JP5125028B2 (ja) | 2006-08-18 | 2006-08-18 | 集積回路 |
Publications (2)
Publication Number | Publication Date |
---|---|
CN101126794A true CN101126794A (zh) | 2008-02-20 |
CN101126794B CN101126794B (zh) | 2010-10-13 |
Family
ID=39094867
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN2007101030343A Expired - Fee Related CN101126794B (zh) | 2006-08-18 | 2007-04-29 | 集成电路 |
Country Status (3)
Country | Link |
---|---|
US (1) | US7590016B2 (zh) |
JP (1) | JP5125028B2 (zh) |
CN (1) | CN101126794B (zh) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN107229010A (zh) * | 2016-03-25 | 2017-10-03 | 精工爱普生株式会社 | 电路、检测装置、振荡器、电子设备、移动体及检测方法 |
CN104252875B (zh) * | 2009-09-08 | 2019-01-04 | 瑞萨电子株式会社 | 半导体集成电路 |
Families Citing this family (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP2135901A4 (en) | 2007-03-05 | 2013-02-13 | Fujifilm Corp | CONNECTION FOR PHOTORESIST, PHOTORESIST SOLUTION AND USE OF THIS PROCESS |
JP5665263B2 (ja) * | 2008-05-30 | 2015-02-04 | ピーエスフォー ルクスコ エスエイアールエルPS4 Luxco S.a.r.l. | 半導体記憶装置、及び該半導体記憶装置のテスト方法 |
JP5206487B2 (ja) * | 2009-02-25 | 2013-06-12 | 富士通セミコンダクター株式会社 | 半導体集積回路の制御方法および半導体集積回路 |
US7888966B1 (en) | 2010-03-25 | 2011-02-15 | Sandisk Corporation | Enhancement of input/output for non source-synchronous interfaces |
JPWO2012137340A1 (ja) * | 2011-04-07 | 2014-07-28 | 富士通株式会社 | 試験方法および前記試験方法が適用される半導体集積回路 |
US9761303B2 (en) * | 2016-01-28 | 2017-09-12 | Apple Inc. | Storage element with multiple clock circuits |
Family Cites Families (21)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS632200A (ja) * | 1986-06-20 | 1988-01-07 | Fujitsu Ltd | メモリ試験方式 |
KR920007909B1 (ko) * | 1989-11-18 | 1992-09-19 | 삼성전자 주식회사 | 램 테스트시 고속 기록방법 |
JPH0566249A (ja) | 1991-02-15 | 1993-03-19 | Mitsubishi Electric Corp | テスト機能付半導体集積回路 |
JPH063424A (ja) | 1992-06-22 | 1994-01-11 | Mitsubishi Electric Corp | 集積回路装置、および集積回路装置に組込まれるテストデータ発生回路 |
US6182253B1 (en) * | 1997-07-16 | 2001-01-30 | Tanisys Technology, Inc. | Method and system for automatic synchronous memory identification |
KR100308621B1 (ko) * | 1998-11-19 | 2001-12-17 | 윤종용 | 반도체 메모리 장치를 위한 프로그램 가능한 내장 자기 테스트 시스템 |
JP2000207900A (ja) * | 1999-01-12 | 2000-07-28 | Mitsubishi Electric Corp | 同期型半導体記憶装置 |
JP4204685B2 (ja) * | 1999-01-19 | 2009-01-07 | 株式会社ルネサステクノロジ | 同期型半導体記憶装置 |
KR100587264B1 (ko) * | 1999-04-03 | 2006-06-08 | 엘지전자 주식회사 | 주문형 반도체 장치의 내부 메모리 및 내부 메모리 테스트 방법 |
JP2001006396A (ja) * | 1999-06-16 | 2001-01-12 | Fujitsu Ltd | 半導体集積回路 |
JP4315552B2 (ja) | 1999-12-24 | 2009-08-19 | 株式会社ルネサステクノロジ | 半導体集積回路装置 |
JP2002014875A (ja) * | 2000-06-30 | 2002-01-18 | Mitsubishi Electric Corp | 半導体集積回路、半導体集積回路のメモリリペア方法およびその方法をコンピュータに実行させるプログラムを記録したコンピュータ読み取り可能な記録媒体 |
JP2002196045A (ja) * | 2000-12-25 | 2002-07-10 | Toshiba Corp | 半導体集積回路 |
JP2003004809A (ja) * | 2001-06-20 | 2003-01-08 | Toshiba Microelectronics Corp | 半導体集積回路及び高速テストシステム |
JP2004071093A (ja) * | 2002-08-08 | 2004-03-04 | Fujitsu Ltd | 出荷試験が簡単で消費電力を削減した冗長メモリセルアレイ付きメモリ回路 |
KR100450682B1 (ko) * | 2002-08-29 | 2004-10-01 | 삼성전자주식회사 | 테스트 효율을 향상시키기 위한 내부회로를 가지는 반도체메모리 장치 및 그 테스트 방법 |
JP2004198367A (ja) * | 2002-12-20 | 2004-07-15 | Fujitsu Ltd | 半導体装置及びその試験方法 |
JP2004246979A (ja) * | 2003-02-14 | 2004-09-02 | Fujitsu Ltd | 半導体試験回路、半導体記憶装置および半導体試験方法 |
JP2005141797A (ja) * | 2003-11-04 | 2005-06-02 | Fujitsu Ltd | 半導体装置 |
US7325178B2 (en) * | 2003-12-05 | 2008-01-29 | Texas Instruments Incorporated | Programmable built in self test of memory |
US7325176B2 (en) * | 2004-02-25 | 2008-01-29 | Dell Products L.P. | System and method for accelerated information handling system memory testing |
-
2006
- 2006-08-18 JP JP2006223281A patent/JP5125028B2/ja not_active Expired - Fee Related
-
2007
- 2007-04-19 US US11/785,630 patent/US7590016B2/en not_active Expired - Fee Related
- 2007-04-29 CN CN2007101030343A patent/CN101126794B/zh not_active Expired - Fee Related
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN104252875B (zh) * | 2009-09-08 | 2019-01-04 | 瑞萨电子株式会社 | 半导体集成电路 |
CN107229010A (zh) * | 2016-03-25 | 2017-10-03 | 精工爱普生株式会社 | 电路、检测装置、振荡器、电子设备、移动体及检测方法 |
CN107229010B (zh) * | 2016-03-25 | 2021-08-27 | 精工爱普生株式会社 | 电路、检测装置、振荡器、电子设备、移动体及检测方法 |
Also Published As
Publication number | Publication date |
---|---|
JP5125028B2 (ja) | 2013-01-23 |
CN101126794B (zh) | 2010-10-13 |
JP2008047243A (ja) | 2008-02-28 |
US20080043552A1 (en) | 2008-02-21 |
US7590016B2 (en) | 2009-09-15 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
CN101126794B (zh) | 集成电路 | |
US6018478A (en) | Random access memory with separate row and column designation circuits for reading and writing | |
CN101694512B (zh) | 测试电路和片上系统 | |
KR100782495B1 (ko) | 반도체 메모리 장치 및 이 장치의 데이터 라이트 및 리드방법 | |
CN101458971A (zh) | 一种嵌入式存储器的测试系统及测试方法 | |
KR19990013547A (ko) | 개선된 싱크로너스 디램과 로직이 하나의 칩에 병합된 반도체장치 | |
KR100890381B1 (ko) | 반도체 메모리 소자 | |
US20030116763A1 (en) | Semiconductor integrated circuit device | |
KR100212142B1 (ko) | 매크로 명령기능을 가진 동기식 반도체 메모리장치와 매크로 명령의 저장 및 실행방법 | |
CN105654993A (zh) | 用于ddr3 sdram控制器的功能验证方法及平台 | |
JP5186587B1 (ja) | 試験装置および試験方法 | |
JP3681892B2 (ja) | 半導体装置のデータ入出力回路及びデータ入出力方法 | |
KR100237565B1 (ko) | 반도체 메모리장치 | |
CN114461472A (zh) | 一种基于ate的gpu核心全速功能测试方法 | |
CN100492331C (zh) | 存储器访问装置 | |
KR100449638B1 (ko) | 스토리지 커패시터를 포함하는 셀을 갖는 에스램의리프레쉬장치 및 그 방법 | |
JP2004022014A (ja) | 半導体装置およびそのテスト方法 | |
US20230178138A1 (en) | Read clock start and stop for synchronous memories | |
CN115620772B (zh) | 访问字线的方法及字线解码电路结构 | |
KR101907072B1 (ko) | 반도체 메모리 장치 및 그 동작 방법 | |
US20020069311A1 (en) | Bus control device | |
KR20230036356A (ko) | 어드레스 래치, 어드레스 제어회로 및 이를 포함하는 반도체 장치 | |
JP2006317178A (ja) | SiP形態の半導体装置 | |
JPH0262790A (ja) | 半導体記憶回路装置 | |
JP2007141454A (ja) | メモリ素子 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
C06 | Publication | ||
PB01 | Publication | ||
C10 | Entry into substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
ASS | Succession or assignment of patent right |
Owner name: FUJITSU MICROELECTRONICS CO., LTD. Free format text: FORMER OWNER: FUJITSU LIMITED Effective date: 20081024 |
|
C41 | Transfer of patent application or patent right or utility model | ||
TA01 | Transfer of patent application right |
Effective date of registration: 20081024 Address after: Tokyo, Japan, Japan Applicant after: Fujitsu Microelectronics Ltd. Address before: Kanagawa Applicant before: Fujitsu Ltd. |
|
C14 | Grant of patent or utility model | ||
GR01 | Patent grant | ||
ASS | Succession or assignment of patent right |
Owner name: SUOSI FUTURE CO., LTD. Free format text: FORMER OWNER: FUJITSU SEMICONDUCTOR CO., LTD. Effective date: 20150515 |
|
C41 | Transfer of patent application or patent right or utility model | ||
TR01 | Transfer of patent right |
Effective date of registration: 20150515 Address after: Kanagawa Patentee after: Co., Ltd. Suo Si future Address before: Kanagawa Patentee before: Fujitsu Semiconductor Co., Ltd. |
|
CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20101013 Termination date: 20180429 |
|
CF01 | Termination of patent right due to non-payment of annual fee |