CN101084577B - 修整通过组装两晶片构成的结构的方法 - Google Patents
修整通过组装两晶片构成的结构的方法 Download PDFInfo
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- CN101084577B CN101084577B CN200580044108XA CN200580044108A CN101084577B CN 101084577 B CN101084577 B CN 101084577B CN 200580044108X A CN200580044108X A CN 200580044108XA CN 200580044108 A CN200580044108 A CN 200580044108A CN 101084577 B CN101084577 B CN 101084577B
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- wafer
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02002—Preparing wafers
- H01L21/02005—Preparing bulk and homogeneous wafers
- H01L21/02008—Multistep processes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
- H01L21/76254—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T156/00—Adhesive bonding and miscellaneous chemical manufacture
- Y10T156/10—Methods of surface bonding and/or assembly therefor
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Power Engineering (AREA)
- Weting (AREA)
- Micromachines (AREA)
- Bending Of Plates, Rods, And Pipes (AREA)
- Connection Of Plates (AREA)
- Surface Treatment Of Glass (AREA)
- Mechanical Treatment Of Semiconductor (AREA)
Abstract
Description
Claims (17)
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
FR0413979 | 2004-12-28 | ||
FR0413979A FR2880184B1 (fr) | 2004-12-28 | 2004-12-28 | Procede de detourage d'une structure obtenue par assemblage de deux plaques |
PCT/FR2005/051128 WO2006070160A1 (fr) | 2004-12-28 | 2005-12-22 | Procede de detourage d'une structure obtenue par assemblage de deux plaques |
Publications (2)
Publication Number | Publication Date |
---|---|
CN101084577A CN101084577A (zh) | 2007-12-05 |
CN101084577B true CN101084577B (zh) | 2010-06-16 |
Family
ID=34953374
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN200580044108XA Active CN101084577B (zh) | 2004-12-28 | 2005-12-22 | 修整通过组装两晶片构成的结构的方法 |
Country Status (8)
Country | Link |
---|---|
US (2) | US8329048B2 (zh) |
EP (1) | EP1831923B1 (zh) |
JP (1) | JP5197017B2 (zh) |
KR (1) | KR101291086B1 (zh) |
CN (1) | CN101084577B (zh) |
FR (1) | FR2880184B1 (zh) |
SG (1) | SG159493A1 (zh) |
WO (1) | WO2006070160A1 (zh) |
Families Citing this family (47)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
FR2880184B1 (fr) * | 2004-12-28 | 2007-03-30 | Commissariat Energie Atomique | Procede de detourage d'une structure obtenue par assemblage de deux plaques |
WO2008029607A1 (en) * | 2006-09-07 | 2008-03-13 | Nec Electronics Corporation | Manufacturing method of semiconductor substrate and manufacturing method of semiconductor device |
FR2935536B1 (fr) * | 2008-09-02 | 2010-09-24 | Soitec Silicon On Insulator | Procede de detourage progressif |
JP5244650B2 (ja) * | 2009-02-26 | 2013-07-24 | 信越半導体株式会社 | Soiウェーハの製造方法 |
US8476165B2 (en) * | 2009-04-01 | 2013-07-02 | Tokyo Electron Limited | Method for thinning a bonding wafer |
US8633090B2 (en) | 2009-07-10 | 2014-01-21 | Shanghai Simgui Technology Co., Ltd. | Method for forming substrate with buried insulating layer |
FR2954585B1 (fr) | 2009-12-23 | 2012-03-02 | Soitec Silicon Insulator Technologies | Procede de realisation d'une heterostructure avec minimisation de contrainte |
FR2956822A1 (fr) * | 2010-02-26 | 2011-09-02 | Soitec Silicon On Insulator Technologies | Procede d'elimination de fragments de materiau presents sur la surface d'une structure multicouche |
FR2957190B1 (fr) | 2010-03-02 | 2012-04-27 | Soitec Silicon On Insulator | Procede de realisation d'une structure multicouche avec detourage par effets thermomecaniques. |
FR2967295B1 (fr) * | 2010-11-05 | 2013-01-11 | Soitec Silicon On Insulator | Procédé de traitement d'une structure multicouche |
US20120129318A1 (en) * | 2010-11-24 | 2012-05-24 | Semiconductor Energy Laboratory Co., Ltd. | Atmospheric pressure plasma etching apparatus and method for manufacturing soi substrate |
FR2969373B1 (fr) * | 2010-12-20 | 2013-07-19 | St Microelectronics Crolles 2 | Procede d'assemblage de deux plaques et dispositif correspondant |
JP2013008915A (ja) * | 2011-06-27 | 2013-01-10 | Toshiba Corp | 基板加工方法及び基板加工装置 |
JP5946260B2 (ja) * | 2011-11-08 | 2016-07-06 | 株式会社ディスコ | ウエーハの加工方法 |
JP5978764B2 (ja) * | 2012-05-24 | 2016-08-24 | 信越半導体株式会社 | Soiウェーハの製造方法 |
US9343348B2 (en) * | 2012-06-12 | 2016-05-17 | Erich Thallner | Substrate-product substrate combination and device and method for producing a substrate-product substrate combination |
US9064770B2 (en) * | 2012-07-17 | 2015-06-23 | Taiwan Semiconductor Manufacturing Company, Ltd. | Methods for minimizing edge peeling in the manufacturing of BSI chips |
JP5862521B2 (ja) * | 2012-09-03 | 2016-02-16 | 信越半導体株式会社 | Soiウェーハの製造方法 |
FR2995444B1 (fr) * | 2012-09-10 | 2016-11-25 | Soitec Silicon On Insulator | Procede de detachement d'une couche |
CN104658927B (zh) * | 2013-11-19 | 2018-03-30 | 中芯国际集成电路制造(上海)有限公司 | 半导体晶片的键合减薄优化方法 |
CN104733300B (zh) * | 2013-12-23 | 2018-09-25 | 中芯国际集成电路制造(上海)有限公司 | 一种键合晶片的减薄方法 |
FR3036223B1 (fr) * | 2015-05-11 | 2018-05-25 | Commissariat A L'energie Atomique Et Aux Energies Alternatives | Procede de collage direct de substrats avec amincissement des bords d'au moins un des deux substrats |
US10134577B2 (en) * | 2015-05-21 | 2018-11-20 | Globalfoundries Inc. | Edge trim processes and resultant structures |
JP6380245B2 (ja) * | 2015-06-15 | 2018-08-29 | 信越半導体株式会社 | Soiウェーハの製造方法 |
CN105023839A (zh) * | 2015-07-15 | 2015-11-04 | 中国电子科技集团公司第四十六研究所 | 一种制作双层结构硅片的方法 |
US10867836B2 (en) * | 2016-05-02 | 2020-12-15 | Taiwan Semiconductor Manufacturing Co., Ltd. | Wafer stack and fabrication method thereof |
US10204893B2 (en) | 2016-05-19 | 2019-02-12 | Invensas Bonding Technologies, Inc. | Stacked dies and methods for forming bonded structures |
JP6202505B1 (ja) * | 2016-06-17 | 2017-09-27 | 株式会社アイカムス・ラボ | 細胞培養装置 |
US20180019169A1 (en) * | 2016-07-12 | 2018-01-18 | QMAT, Inc. | Backing substrate stabilizing donor substrate for implant or reclamation |
US20180182665A1 (en) | 2016-12-28 | 2018-06-28 | Invensas Bonding Technologies, Inc. | Processed Substrate |
US10580823B2 (en) | 2017-05-03 | 2020-03-03 | United Microelectronics Corp. | Wafer level packaging method |
US10879212B2 (en) * | 2017-05-11 | 2020-12-29 | Invensas Bonding Technologies, Inc. | Processed stacked dies |
FR3076393A1 (fr) * | 2017-12-28 | 2019-07-05 | Commissariat A L'energie Atomique Et Aux Energies Alternatives | Procede de transfert d'une couche utile |
DE102018111200A1 (de) * | 2018-05-09 | 2019-11-14 | United Monolithic Semiconductors Gmbh | Verfahren zur Herstellung eines wenigstens teilweise gehäusten Halbleiterwafers |
US11276676B2 (en) | 2018-05-15 | 2022-03-15 | Invensas Bonding Technologies, Inc. | Stacked devices and methods of fabrication |
WO2020010136A1 (en) | 2018-07-06 | 2020-01-09 | Invensas Bonding Technologies, Inc. | Molded direct bonded and interconnected stack |
WO2020010265A1 (en) | 2018-07-06 | 2020-01-09 | Invensas Bonding Technologies, Inc. | Microelectronic assemblies |
US20200075533A1 (en) | 2018-08-29 | 2020-03-05 | Invensas Bonding Technologies, Inc. | Bond enhancement in microelectronics by trapping contaminants and arresting cracks during direct-bonding processes |
FR3085957B1 (fr) | 2018-09-14 | 2021-01-29 | Commissariat Energie Atomique | Procede de collage temporaire avec adhesif thermoplastique incorporant une couronne rigide |
CN110943066A (zh) * | 2018-09-21 | 2020-03-31 | 联华电子股份有限公司 | 具有高电阻晶片的半导体结构及高电阻晶片的接合方法 |
WO2020150159A1 (en) | 2019-01-14 | 2020-07-23 | Invensas Bonding Technologies, Inc. | Bonded structures |
US11296053B2 (en) | 2019-06-26 | 2022-04-05 | Invensas Bonding Technologies, Inc. | Direct bonded stack structures for increased reliability and improved yield in microelectronics |
US12080672B2 (en) | 2019-09-26 | 2024-09-03 | Adeia Semiconductor Bonding Technologies Inc. | Direct gang bonding methods including directly bonding first element to second element to form bonded structure without adhesive |
CN110739263A (zh) * | 2019-10-28 | 2020-01-31 | 沈阳硅基科技有限公司 | Soi的制造方法 |
US11631647B2 (en) | 2020-06-30 | 2023-04-18 | Adeia Semiconductor Bonding Technologies Inc. | Integrated device packages with integrated device die and dummy element |
US11923205B2 (en) * | 2021-12-17 | 2024-03-05 | United Microelectronics Corporation | Method for manufacturing semiconductor device |
DE102022000424A1 (de) | 2022-02-03 | 2023-08-03 | Azur Space Solar Power Gmbh | Herstellungsverfahren für eine Halbleiterscheibe mit Silizium und mit einer III-N-Schicht |
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CN1225499A (zh) * | 1998-02-04 | 1999-08-11 | 佳能株式会社 | 半导体衬底及其制造方法 |
CN1272684A (zh) * | 1999-02-02 | 2000-11-08 | 佳能株式会社 | 衬底及其制造方法 |
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FR2888400B1 (fr) * | 2005-07-08 | 2007-10-19 | Soitec Silicon On Insulator | Procede de prelevement de couche |
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-
2004
- 2004-12-28 FR FR0413979A patent/FR2880184B1/fr not_active Expired - Fee Related
-
2005
- 2005-12-22 SG SG201000395-2A patent/SG159493A1/en unknown
- 2005-12-22 WO PCT/FR2005/051128 patent/WO2006070160A1/fr active Application Filing
- 2005-12-22 US US11/722,115 patent/US8329048B2/en active Active
- 2005-12-22 EP EP05825588.6A patent/EP1831923B1/fr active Active
- 2005-12-22 CN CN200580044108XA patent/CN101084577B/zh active Active
- 2005-12-22 JP JP2007548879A patent/JP5197017B2/ja active Active
- 2005-12-22 KR KR1020077014025A patent/KR101291086B1/ko active IP Right Grant
-
2012
- 2012-11-20 US US13/682,009 patent/US8628674B2/en active Active
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
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CN1225499A (zh) * | 1998-02-04 | 1999-08-11 | 佳能株式会社 | 半导体衬底及其制造方法 |
CN1272684A (zh) * | 1999-02-02 | 2000-11-08 | 佳能株式会社 | 衬底及其制造方法 |
Non-Patent Citations (2)
Title |
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JP特开平11-67701A 1999.03.09 |
全文. |
Also Published As
Publication number | Publication date |
---|---|
SG159493A1 (en) | 2010-03-30 |
JP2008526038A (ja) | 2008-07-17 |
JP5197017B2 (ja) | 2013-05-15 |
FR2880184B1 (fr) | 2007-03-30 |
WO2006070160A1 (fr) | 2006-07-06 |
US20130078785A1 (en) | 2013-03-28 |
KR101291086B1 (ko) | 2013-08-01 |
CN101084577A (zh) | 2007-12-05 |
KR20070110261A (ko) | 2007-11-16 |
FR2880184A1 (fr) | 2006-06-30 |
US20090095399A1 (en) | 2009-04-16 |
EP1831923B1 (fr) | 2019-05-22 |
EP1831923A1 (fr) | 2007-09-12 |
US8628674B2 (en) | 2014-01-14 |
US8329048B2 (en) | 2012-12-11 |
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