CN101075588A - 半导体结构、半导体晶片及其制造方法 - Google Patents

半导体结构、半导体晶片及其制造方法 Download PDF

Info

Publication number
CN101075588A
CN101075588A CNA2006101690673A CN200610169067A CN101075588A CN 101075588 A CN101075588 A CN 101075588A CN A2006101690673 A CNA2006101690673 A CN A2006101690673A CN 200610169067 A CN200610169067 A CN 200610169067A CN 101075588 A CN101075588 A CN 101075588A
Authority
CN
China
Prior art keywords
stress
wafer
mentioned
substrate
adjustment layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CNA2006101690673A
Other languages
English (en)
Inventor
郑心圃
赵智杰
卢思维
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Taiwan Semiconductor Manufacturing Co TSMC Ltd
Original Assignee
Taiwan Semiconductor Manufacturing Co TSMC Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Taiwan Semiconductor Manufacturing Co TSMC Ltd filed Critical Taiwan Semiconductor Manufacturing Co TSMC Ltd
Publication of CN101075588A publication Critical patent/CN101075588A/zh
Pending legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/562—Protection against mechanical damage
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02126—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
    • H01L21/0214—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC the material being a silicon oxynitride, e.g. SiON or SiON:H
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/304—Mechanical treatment, e.g. grinding, polishing, cutting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/30625—With simultaneous mechanical treatment, e.g. mechanico-chemical polishing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/314—Inorganic layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/314—Inorganic layers
    • H01L21/316—Inorganic layers composed of oxides or glassy oxides or oxide based glass
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/314—Inorganic layers
    • H01L21/318—Inorganic layers composed of nitrides
    • H01L21/3185—Inorganic layers composed of nitrides of siliconnitrides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/32051—Deposition of metallic or metal-silicide layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/563—Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/565—Moulds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/96—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
    • H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
    • H01L21/02274—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition in the presence of a plasma [PECVD]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02282—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process liquid deposition, e.g. spin-coating, sol-gel techniques, spray coating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48105—Connecting bonding areas at different heights
    • H01L2224/48106—Connecting bonding areas at different heights the connector being orthogonal to a side surface of the semiconductor or solid-state body, e.g. parallel layout
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48153—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being arranged next to each other, e.g. on a common substrate
    • H01L2224/48175—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being arranged next to each other, e.g. on a common substrate the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/585—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries comprising conductive layers or plates or strips or rods or rings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01019—Potassium [K]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/0132—Binary Alloys
    • H01L2924/01327—Intermediate phases, i.e. intermetallics compounds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/095—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00 with a principal constituent of the material being a combination of two or more materials provided in the groups H01L2924/013 - H01L2924/0715
    • H01L2924/097—Glass-ceramics, e.g. devitrified glass
    • H01L2924/09701—Low temperature co-fired ceramic [LTCC]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/102—Material of the semiconductor or solid state bodies
    • H01L2924/1025—Semiconducting materials
    • H01L2924/10251—Elemental semiconductors, i.e. Group IV
    • H01L2924/10253—Silicon [Si]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/35—Mechanical effects
    • H01L2924/351—Thermal stress
    • H01L2924/3511—Warping

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Formation Of Insulating Films (AREA)
  • Element Separation (AREA)

Abstract

本发明提供一种具有应力调整层的集成电路及其制造方法，可以避免晶片翘曲及破损。该具有应力调整层的集成电路的制造方法包括：提供具有第一表面及第二表面的半导体基板，其中该半导体基板的厚度大体小于150μm；形成多个膜层于该基板的第一表面，该多个膜层在该半导体基板上施加应力；以及，在该第一表面及第二表面其中之一上形成应力调整层，并补偿或平衡该多个膜层施加在半导体晶片上的该应力。

Description

半导体结构、半导体晶片及其制造方法
技术领域
本发明是有关于一种集成电路，特别是有关于一种具有半导体基板的集成电路及其制造方法。
背景技术
众所周知，大部分集成电路是形成在晶片上，如半导体晶片，其中代表性地为硅晶片。近十年来，所使用的晶片的直径由原本的二英寸演变至八英寸、十二英寸，甚至直径为300厘米的晶片。
目前大部分的集成电路被制造在八寸的晶片上，而大部分的新型加工设备被设计用来将集成电路形成在十二寸的晶片上。
由于晶片上所使用到的区域是圆形面积中所能包含的最大矩形面积，因此当晶片直径增加50％时(由八英寸增加至十二英寸)，能用来制造集成电路的矩形面积会增加至两倍以上。
另一个集成电路装置的加工发展趋势是其封装技术。
随着表面粘结封装及低剖面封装等封装技术的产生，在一部分封装加工中，晶片被进一步研磨以减少晶片的厚度。
基于上述，如何制造出具有高表面积及低厚度的晶片，在半导体加工中逐渐成为重要的研究课题之一。这些研究包括在加工集成电路时，在晶片上形成多个膜层时给晶片造成的压缩应力、或拉伸强度。形成的膜层包括介电层(例如层间介电层(inter-layer dielectric、ILD)、金属间介电层(inter-metaldielectric、IMD))、蚀刻停止层、及保护层等)、传导层(例如掺有杂质的多晶硅层、及金属内连结层。
当集成电路装置具有七、八、甚至更多层的金属内连结层时，加上搭配的层间介电、蚀刻停止层、及保护层，必需形成20甚至更多的膜层于该晶片之上。
然而，如此多的膜层集合起来施加在该薄型化晶片上的应力将造成该晶片产生显著的翘曲，也同时会影响将要形成的集成电路装置。
请参照图1A，该图表示了形成于晶片2上的膜层4施加给该晶片2的应力使得该晶片2翘曲的情况。如上所述，这些膜层在作为底层的晶片2上逐渐累积应力，使得晶片翘曲。另外，图1A的虚线6表示的是一般未翘曲的晶片2的轮廓；图示的翘曲程度是夸张的表示，其目的是表现形成于晶片上的膜层对晶片所产生的翘曲效果。
经过连续加工后的晶片被分割成多个独立的芯片，因此所形成的芯片同样被应力影响。图1B表示了在芯片8上成形的膜层4的应力使得该芯片8翘曲的情况。一般未翘曲的芯片8轮廓如虚线10所示；图示的翘曲程度是夸张的表示，其目的是表现形成于芯片上的膜层对芯片所产生的翘曲效果。
形成于晶片上的膜层所导致的翘曲会产生一些不利的影响。其中之一就是增加晶片处理的困难度及晶片在连续的加工下被损坏的可能性。
此外，该翘曲的晶片8会直接影响到形成于其上的电子装置的电性性质。众所周知，过度的应力(由晶片8翘曲产生)会对MOS晶体管内的半导体膜层的电荷载体的迁移率(mobility)造成不利的影响。
因此，为满足目前半导体元件加工上的需求，发明出避免晶片翘曲的结构及加工方法，是半导体技术的研发重点之一。
发明内容
本发明的目的是提供一种半导体结构及晶片，具有应力调整层，能够有效避免晶片翘曲，保持集成电路的效能。
本发明的目的是这样实现的：一种半导体结构，包含：半导体基板，其厚度大体小于150μm，该半导体基板具有第一表面及第二表面；应力调整层形成在该基板的第一及第二表面其中之一上，以大体补偿或平衡该半导体基板的应力；以及形成于该第一表面上的多个的接合垫。
本发明的另一目的是这样实现的：一种半导体晶片，其厚度大体小于150μm，包含：第一及一第二表面；在该第一表面上形成的多个的薄膜，其中该多个的薄膜在该半导体晶片上累积应力；以及应力调整层，其形成于该第一及第二表面其中之一上，并补偿或平衡该施加在半导体晶片上的该应力。
本发明的再一目的是这样实现的：一种形成半导体结构的方法，具有如下步骤：提供具有第一表面及第二表面的半导体基板，其中该半导体基板的厚度大体小于150μm；在该基板的第一表面上形成有多个膜层，该多个膜层在该半导体基板上施加应力；以及，在该第一表面及第二表面其中之一上形成应力调整层，并补偿或平衡该多个膜层施加在半导体晶片上的该应力。
为使本发明的上述目的、特征能更明显易懂，下文特例举了较佳实施例，并配合附图，详细说明如下：
附图说明
图1A是表示现有半导体晶片因应力而翘曲的剖面示意图。
图1B是表示现有半导体芯片因应力而翘曲的剖面示意图
图2A～图2C是表示本发明的实施例所述的包含应力调整层的晶片的制造流程剖面示意图。
图3A～图3C是表示本发明的实施例所述的包含应力调整层的晶片的仰视图。
图3D是表示本发明的实施例所述的包含应力调整层的晶片的仰视图。
图4A～图4B是表示本发明另一实施例所述的包含应力调整层的晶片的剖面示意图，其中该应力调整层与该集成电路形成在同一侧。
图5A及图5B是剖面结构图，是表示本发明的实施例中所述的晶片以覆晶(flip-chip)方式进行封装。
图6A及图6B是剖面结构图，是表示本发明的实施例中所述的晶片以导线方式进行封装。
图7是说明形成有不同厚度与材质的膜层的晶片，其尺寸与翘曲量的关系的图。
附图标记的简单说明
晶片～2；膜层～4；虚线～6；虚线～10；半导体晶片～12；膜层～9、11、13；薄膜～14；保护层～16；箭头方向～17；应力调整层～18；箭头方向～19；接合垫～20；条状(圆形)沟槽～22；切割线～24；虚线～25；芯片～26；支撑基板～30；焊球～32；胶层～34；接触端～36；导线～38；曲线～101、103、105、109。
具体实施方式
如图2A至图2C，是表示符合本发明所述的显示装置的半导体结构的一较佳实施例的加工流程剖面图。在半导体晶片12上形成有多个膜层9、11、13，其中将上述的该多个的膜层9、11、13总称为薄膜14。  虽然在此例示了三个膜层，但根据本发明的精神，本技术领域的技术人员可将本发明用于其它具有不同膜层数的半导体加工上来形成集成电路。
在此实施例中，该晶片12是硅晶片，其直径可为8英寸、12英寸、或16英寸及其以上。典型的硅晶片12的厚度约为620μm(约31密尔)。在本发明另一实施例中，该晶片12也可以是具有在其上形成的由埋层氧化物构成的薄层的硅晶片，也就是所谓的绝缘层上覆硅(silicon on insulator、SOI)。
薄膜14由多个的膜层构成，该多个的膜层可为典型用于集成电路加工的任何膜层。该薄膜14形成在该晶片12的上表面上，而该晶片12是作为基板。这些多个的膜层11、12、13可例如为用于作为闸电极的掺有杂质的多晶硅(doped polysilicon)、蚀刻停止层、层间介电层(ILD)、金属间介电层(IMDs)、金属电结层、或是相关类似膜层。一般来说，该多个膜层相对顶端是保护层，让所形成的集成电路免受外界的污染或是水气的影响。
一个典型的集成电路一般来说会具有8层金属层以及对应数量的金属间介电层及蚀刻停止层，因此在集成电路的制造过层中，一般会有超过20层以上的膜层形成在晶片表面上，而该不同的膜层是用不同的加工方法形成的，例如化学气象沉积法(CVD)、电压辅助气象沉积法(PEVD)，原子层沉积法(ALD)、溅镀法(sputtering)、电镀法、无电镀法等。
该多个的膜层的形成温度是介于400度左右。在沉积步骤，所形成的膜层不会对其下的膜层施加应力。然而，在沉积完成后，由于温度回归至室温，各膜层及晶片的不同膨胀系数同时施加于该结构体中。因此，可视为是该多个的膜层在位于最底的基晶12上施加了一个总合的应力。如图1A、图1B所示，该应力很容易造成晶片翘曲。该应力有可能为压缩应力或为拉伸应力。一般而言，对于MOS的加工，该多个膜层一般是对该晶片造成拉伸应力。此外，该多个膜层也有可能对该晶片造成压缩应力。如图2A，该晶片具有厚度，一般来说是620μm(31密尔)。然而，以目前技术来说，为利于封装或形成覆晶的结构，一般会对该晶片进行研磨加工以削减其厚度。
如图2B，在该薄膜14的上表面形成有保护层16。值得注意的是，一般来说该保护层16是在该集成电路完成后才形成在该晶片12上的。此外，如图2B，多个的接合垫20形成在该薄膜14最上层的膜层13中。此接合垫20是用来将此集成电路装置与外部的电路结合，一般形成在保护层之前。该保护层16除了可避免形成于基圆上的多个膜层遭受到外界的损害，亦可在进行后续的背面研磨时保护该集成电路。在形成保护层后，如图2C，对该晶片12进行背面研磨，以减少晶片的厚度。该背面研磨可用现有的任何方法，故在此不加赘述。
经过该背面研磨后，该晶片12的厚度可以减少至75μm(3密尔)或是小于50μm(2密尔)，甚至是25μm(1密尔)。值得注意的是该保护层在背面研磨后仍在该多个的膜层上来给该晶片提供支撑力，且避免该晶片因多个膜层所施加的应力而发生翘曲。接着，如图2C，应力调整层18形成于该晶片12的背面或是底部。在此实施例中，该应力调整层18是形成于该晶片12表面，而应力调整层18所形成的表面是形成有该薄膜14的表面的相反侧。在一较佳实施例中，该薄膜14施加拉伸应力于该晶片12上，会造成该晶片12朝箭头方向17翘曲，造成如图1A所示的结果。值得注意的是，由于该保护层16仍形成于该晶片12上，因此该保护层16可避免该翘曲发生。然而，在封装集成电路时，必须除去该保护层16以露出该多个的接触垫。所以，在移除该保护层前必须在该晶片12上形成该应力调整层18。由于该应力调整层18亦同时提供拉伸应力于该晶片12(请见箭头方向19)，因此可以补偿或平衡由薄膜14施加在晶片上的应力。在形成该应力调整层18之后，移除该保护层16并进行后续的封装加工。
本领域的技术人员可利用不同的材料及调整不同的厚度以不同的形成方法来在该晶片12上形成该应力调整层18。由于为了不影响后续的该集成电路的封装及不增加该集成电路的总厚度，因此该应力调整层18的厚度应该是尽可能的小。在本发明一较佳实施例中，该应力调整层18的厚度小于20μm。该应力调整层18的材质可为介电材料，例如氮化硅、氧化硅、氮氧化硅等，形成方式可为现有的任何能够形成介电层的方式。此外，该应力调整层18亦可为low-k介电材料、聚亚酰胺、或是玻璃、塑料、陶瓷、模塑料等。该low-k介电材料可例如为掺杂碳的氧化硅、掺杂氟的氧化硅、或是碳化硅。
在本发明另一实施例中，传导层是例如镍、铬等的，也可作为该应力调整层18。此类材料除了可平衡应力外，还可提供较佳的热传导及晶片的接地电容。一般来说，适合该应力调整层18的材料的形成温度一般需小于400度，这是为避免对先前所形成的集成电路加工造成影响。若形成温度大于400度时，有可能例如造成掺杂离子的迁移。
在移除该保护层16后，即可露出该多个的接合垫20，以利于外部的电路利用导线与该接合垫20电连结。在本发明一较佳实施例中，该集成电路(芯片)也可以用覆晶(flip chip)的方式进行组装。
该应力调整层18可平坦覆盖性地形成在该晶片上，也可进一步图形化。图形化该应力调整层18的目的在于调节施加在该晶片上的应力。图3A是平面示意图，表示未被图形化的应力调整层18。图3B是表示该应力调整层18被进一步图形化以形成多个的圆形沟槽22，以形成不同区块的应力调整层18来调节应力。图3C是表示该应力调整层被进一步图形化以形成多个条状沟槽22，以形成不同区块的应力调整层18来调节应力。在本发明其它较佳实施例中，该应力调整层18被图形化以形成较宽的图形，或是移除位于晶片边缘的应力调整层18，或是根据所形成的芯片区域来图形化该应力调整层18。此外，在图形化该应力调整层18时，也可以根据需要来形成具有不同厚度的应力调整层18。
图3D是该晶片12的俯视图，表示形成于其上的集成电路图形，而图3D也表示图3A～图3C所示的图的相反侧。由图可知，多条切割线24横跨该晶片12，以定义出多个芯片26，该芯片26的长宽t1及t2约为20μm以上。若是施加给该晶片12的应力没有移除的话，同样的应力也会使该芯片26翘曲。根据本发明，由于是在该晶片上进一步形成应力调整层18，因此即使该芯片26的尺寸为20μm×20μm以上，也不会翘曲变形。
图4A表示本发明其它实施例所述的具有应力调整层18的晶片12，值得注意的是，该应力调整层18也可以在与在该晶片12形成该薄膜14的同侧表面。值得注意的是，该应力调整层18是在完成集成电路的加工后形成的，因此该应力调整层18是额外形成的膜层，并非属于该集成电路本身的膜层，也不是保护层。并且，如图4B，该保护层16可进一步形成在该应力调整层18上。在形成该应力调整层18后，该晶片12可进一步进行背面的研磨加工(研磨至虚线25)，以减少其厚度。此外，如图4B，由于在该晶片的多个膜层侧14上形成有该应力调整层18，因此所形成的保护层16的厚度可以比一般的薄。
薄膜14所产生的应力会使晶片12朝箭头方向17翘曲，而该应力调整层18同时给该晶片12提供拉伸应力(箭头方向19)，因此可避免该晶片翘曲。这也是说该应力调整层18所提供的应力作用方向与该薄膜施加给该晶片的应力方向相反。
图5A及图5B是为剖面结构图，表示本发明实施例中所述的晶片以覆晶(flip-chip)方式进行封装。如图5A，如图2C所示的晶片12在移除掉该保护层16后，是反过来被配置在支撑基板30上，其中该晶片12的接合垫20是通过焊料或焊球32与该支撑基板30电连接。当该晶片12顺利地与该支撑基板30接合后，会用填充材(例如树脂)来填充该晶片12与该支撑基板30之间的空隙，因此该填充材也会给该晶片提供应力，避免该晶片12发生翘曲。所以在形成该支撑材后，可以选择将该应力调整层18移除。
如图5B，该应力调整层18具有多个开口，并且在每一开口填有一接合垫20，该接合垫20用来将集成电路与外界电路电连接。当该晶片12顺利地与该支撑基板30接合后，会用填充材(例如树脂)来填充该晶片12与该支撑基板30之间的空隙，因此该填充材也会给该晶片提供应力，从而避免该晶片12发生翘曲。
图6A及图6B为剖面结构图，是表示本发明实施例中所述的晶片以导线方式进行封装。如图6A，该应力调整层18形成于该晶片的背面，并配置在支撑基板30上。其中，胶层34用来将晶片12固定在该支撑基板30上。此外，形成在晶片上的接合垫是利用导线38与外部电路的接触端36(lead finger)电连接。在完成该封装后，在该晶片上可进一步形成塑料或陶瓷材料以保护该晶片12上的集成电路。如图6B，该应力调整层18形成于该晶片12上并与该膜层14同一侧，该应力调整层18具有多个开口，而在每一开口都填入有该接合垫20，该接合垫是利用导线38与外部电路的接触端36(lead finger)电连接。
图7说明形成有不同厚度与材质的膜层的晶片的尺寸与翘曲量的关系。在图7中，NIT是代表该膜层是为硅化氮层、AI是代表该膜层是为铝金属层、及PI是代表该膜层是为聚亚酰胺，在NIT、AI、PI后的数值是代表该应力调整层的厚度；在@后的是该晶片的材质，Si代表硅晶片，而Si后的数值是代表该晶片的厚度。由图中可知，该翘曲量会根据晶片尺寸的增加而增大，如厚度为1密尔的硅晶片的翘曲量(见曲线101及103)，比厚度为29密尔的硅晶片的翘曲量(见曲线105及107)大上百倍以上。
以上说明并非用以限定本发明，本领域的技术人员在不脱离本发明的精神和范围内，当可作些许的更动与润饰，因此本发明的保护范围当视后附的权利要求书所界定的内容为准。

Claims (12)

1.一种半导体结构，其特征在于，包含：
半导体基板，其厚度小于150μm，其中该半导体基板具有第一表面及第二表面；
应力调整层，其形成在该基板的第一及第二表面其中之一上，来补偿或平衡该半导体基板的应力；以及，
多个接合垫，其形成在上述第一表面上。
2.如权利要求1所述的半导体结构，其特征在于，
上述应力调整层具有的应力大于1×108dyne/cm2。
3.如权利要求1所述的半导体结构，其特征在于，
上述应力调整层形成在上述基板的第二表面上。
4.如权利要求1所述的半导体结构，其特征在于，
上述应力调整层形成在上述基板的第一表面上，
上述应力调整层包含多个开口，从该开口露出形成于其下的接触垫。
5.如权利要求1所述的半导体结构，其特征在于，
上述应力调整层的材料是选自由氮化硅、氧化硅、氮氧化硅、聚亚酰胺、玻璃、塑料、陶瓷、模塑料、及其混合物所组成的族群。
6.如权利要求1所述的半导体结构，其特征在于，
上述应力调整层包含电传导层。
7.一种半导体晶片，其厚度小于150μm，其特征在于，包含：
第一及第二表面；
多个薄膜，其形成在上述第一表面上，该多个薄膜在该半导体晶片上累积应力；以及
应力调整层，其形成在上述第一及第二表面之一上，并补偿或平衡施加在半导体晶片上的上述应力。
8.一种形成半导体结构的方法，其特征在于，包含：
提供具有第一表面及第二表面的半导体基板，其中该半导体基板的厚度大体小于150μm；
在该基板的第一表面上形成多个膜层，该多个膜层在该半导体基板上施加应力；以及
在该第一表面及第二表面之一上形成应力调整层，该应力调整层补偿或平衡上述多个膜层施加在半导体晶片上的上述应力。
9.如权利要求8所述的形成半导体结构的方法，其特征在于，
在形成上述应力调整层前，移除一部分的第二表面侧的半导体基板。
10.如权利要求8所述的形成半导体结构的方法，其特征在于，
施加在上述多个膜层上的应力是逐渐累积起来的拉伸张应力，而上述应力调整层提供压缩应力。
11.如权利要求9所述的形成半导体结构的方法，其特征在于，
在移除该部分的基板前，在上述半导体基板的第一基板上配置保护层。
12.如权利要求8所述的形成半导体结构的方法，其特征在于，
上述应力调整层形成在上述基板的第一表面上，且在形成上述应力调整层的步骤中能够包含形成多个的开口，从该开口露出形成在上述应力调整层下的接触垫。
CNA2006101690673A 2006-05-16 2006-12-20 半导体结构、半导体晶片及其制造方法 Pending CN101075588A (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US11/435,436 US7880278B2 (en) 2006-05-16 2006-05-16 Integrated circuit having stress tuning layer
US11/435,436 2006-05-16

Publications (1)

Publication Number Publication Date
CN101075588A true CN101075588A (zh) 2007-11-21

Family

ID=38711256

Family Applications (1)

Application Number Title Priority Date Filing Date
CNA2006101690673A Pending CN101075588A (zh) 2006-05-16 2006-12-20 半导体结构、半导体晶片及其制造方法

Country Status (3)

Country Link
US (7) US7880278B2 (zh)
CN (1) CN101075588A (zh)
TW (1) TWI337374B (zh)

Cited By (24)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101887848A (zh) * 2009-05-13 2010-11-17 硅电子股份公司 包括具有前侧和背侧的硅单晶衬底和沉积于前侧上的SiGe层的晶片的生产方法
CN102344112A (zh) * 2010-07-30 2012-02-08 飞思卡尔半导体公司 形成加帽的微机电系统(mems)器件的方法
CN102414802A (zh) * 2009-05-07 2012-04-11 高通股份有限公司 不连续薄半导体晶片表面特征
CN104871060A (zh) * 2012-12-17 2015-08-26 旭硝子株式会社 光学元件、光学系统以及摄像装置
CN104977736A (zh) * 2014-04-09 2015-10-14 群创光电股份有限公司 具有线宽变化的导电层的显示面板
CN105226029A (zh) * 2014-06-25 2016-01-06 环球晶圆股份有限公司 具压应力之硅基板及其制造方法
CN105448666A (zh) * 2015-12-02 2016-03-30 苏州工业园区纳米产业技术研究院有限公司 利用二氧化硅的应力来改变晶圆硅片基体弯曲度的方法
CN105448762A (zh) * 2014-08-28 2016-03-30 中国科学院微电子研究所 一种衬底翘曲度的调整方法
CN106952812A (zh) * 2017-03-31 2017-07-14 成都海威华芯科技有限公司 一种GaN器件键合方法
CN107845569A (zh) * 2017-11-02 2018-03-27 江苏华功半导体有限公司 一种复合衬底及其制备方法
CN108604572A (zh) * 2015-12-16 2018-09-28 奥斯坦多科技公司 用于改善晶片平面度的方法和由该方法制成的接合晶片组件
CN108649034A (zh) * 2018-05-11 2018-10-12 长江存储科技有限责任公司 半导体结构及其形成方法
CN110383439A (zh) * 2017-03-08 2019-10-25 三菱电机株式会社 半导体装置、其制造方法以及半导体模块
CN110581050A (zh) * 2018-06-07 2019-12-17 东京毅力科创株式会社 处理方法和等离子体处理装置
CN110634389A (zh) * 2019-08-30 2019-12-31 昆山工研院新型平板显示技术中心有限公司 一种基板的制备方法
CN111106073A (zh) * 2018-10-26 2020-05-05 株洲中车时代电气股份有限公司 一种功率半导体器件的低应力薄膜结构
CN111394795A (zh) * 2020-04-10 2020-07-10 哈尔滨科友半导体产业装备与技术研究院有限公司 一种去除籽晶残余应力的退火装置及退火方法
CN111547498A (zh) * 2020-06-01 2020-08-18 上海原能细胞生物低温设备有限公司 一种柔性板架抓取装置及使用方法
WO2020227988A1 (zh) * 2019-05-15 2020-11-19 华为技术有限公司 一种芯片封装装置及其制备方法
CN113035688A (zh) * 2019-12-09 2021-06-25 华润微电子（重庆）有限公司 一种半导体结构及其制作方法
CN113061861A (zh) * 2019-12-13 2021-07-02 中国科学院大连化学物理研究所 一种大曲率光学元件曲率半径控制方法
CN113078093A (zh) * 2021-03-24 2021-07-06 长江存储科技有限责任公司 制造半导体器件的方法、仿形晶圆
CN113555324A (zh) * 2020-04-24 2021-10-26 矽品精密工业股份有限公司 电子封装件
CN118263137A (zh) * 2024-05-29 2024-06-28 浙江创芯集成电路有限公司 半导体结构的形成方法

Families Citing this family (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7880278B2 (en) 2006-05-16 2011-02-01 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated circuit having stress tuning layer
US8212346B2 (en) * 2008-10-28 2012-07-03 Global Foundries, Inc. Method and apparatus for reducing semiconductor package tensile stress
DE102008054069B4 (de) * 2008-10-31 2016-11-10 Globalfoundries Dresden Module One Limited Liability Company & Co. Kg Reduzierte Scheibendurchbiegung in Halbleitern durch Verspannungstechniken im Metallisierungssystem
US20100314725A1 (en) * 2009-06-12 2010-12-16 Qualcomm Incorporated Stress Balance Layer on Semiconductor Wafer Backside
US8476764B2 (en) * 2011-09-18 2013-07-02 Nanya Technology Corp. Bonding pad structure for semiconductor devices
US8927334B2 (en) * 2012-09-25 2015-01-06 International Business Machines Corporation Overcoming chip warping to enhance wetting of solder bumps and flip chip attaches in a flip chip package
US9397051B2 (en) 2013-12-03 2016-07-19 Invensas Corporation Warpage reduction in structures with electrical circuitry
US9768038B2 (en) 2013-12-23 2017-09-19 STATS ChipPAC, Pte. Ltd. Semiconductor device and method of making embedded wafer level chip scale packages
US9312205B2 (en) 2014-03-04 2016-04-12 International Business Machines Corporation Methods of forming a TSV wafer with improved fracture strength
TWI631399B (zh) * 2014-04-09 2018-08-01 群創光電股份有限公司 具有線寬變化的導電層之顯示面板
DE102014116082A1 (de) * 2014-11-04 2016-05-04 Infineon Technologies Ag Halbleitervorrichtung mit einer spannungskompensierten Chipelelektrode
CN104555907B (zh) * 2015-01-29 2017-01-04 苏州晶方半导体科技股份有限公司 键合方法以及键合结构
US10723614B2 (en) * 2017-12-11 2020-07-28 Vanguard International Semiconductor Singapore Pte. Ltd. Devices with localized strain and stress tuning
RU2666173C1 (ru) * 2017-12-20 2018-09-06 Федеральное государственное автономное образовательное учреждение высшего образования "Национальный исследовательский университет "Московский институт электронной техники" Способ изменения радиуса кривизны поверхности пластины для минимизации механических напряжений
IT201800004756A1 (it) 2018-04-20 2019-10-20 Procedimento di realizzazione di un dispositivo semiconduttore sottoposto a sollecitazioni e relativo dispositivo semiconduttore sottoposto a sollecitazioni
JP7115932B2 (ja) * 2018-08-14 2022-08-09 株式会社ディスコ 被加工物の加工方法
CN111834438B (zh) 2019-04-18 2024-05-31 西部数据技术公司 半导体部件背侧上用于减轻堆叠封装中的分层的孔结构
CN111115567B (zh) * 2019-12-25 2023-07-14 北京航天控制仪器研究所 一种用于mems晶圆级封装的应力补偿方法
US11569134B2 (en) * 2020-04-14 2023-01-31 International Business Machines Corporation Wafer backside engineering for wafer stress control
WO2022164693A1 (en) * 2021-01-26 2022-08-04 Tokyo Electron Limited Localized stress regions for three-dimension chiplet formation

Family Cites Families (27)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5016080A (en) * 1988-10-07 1991-05-14 Exar Corporation Programmable die size continuous array
JP3332456B2 (ja) * 1992-03-24 2002-10-07 株式会社東芝 半導体装置の製造方法及び半導体装置
US5452625A (en) 1993-09-29 1995-09-26 United Technologies Corporation Energy storage flywheel device
DE4433833A1 (de) * 1994-09-22 1996-03-28 Fraunhofer Ges Forschung Verfahren zur Herstellung einer dreidimensionalen integrierten Schaltung unter Erreichung hoher Systemausbeuten
JP3071136B2 (ja) 1995-03-07 2000-07-31 シャープ株式会社 端子構造ならびにこれを用いたユニバーサルｌｎｂ
JPH10229059A (ja) * 1997-02-17 1998-08-25 Mitsubishi Electric Corp 半導体装置の製造方法および半導体装置
EP1041610B1 (en) * 1997-10-30 2010-12-15 Sumitomo Electric Industries, Ltd. GaN SINGLE CRYSTALLINE SUBSTRATE AND METHOD OF PRODUCING THE SAME
KR100462980B1 (ko) * 1999-09-13 2004-12-23 비쉐이 메저먼츠 그룹, 인코포레이티드 반도체장치용 칩 스케일 표면 장착 패키지 및 그 제조공정
JP3973340B2 (ja) * 1999-10-05 2007-09-12 Ｎｅｃエレクトロニクス株式会社 半導体装置、配線基板、及び、それらの製造方法
US6403449B1 (en) * 2000-04-28 2002-06-11 Micron Technology, Inc. Method of relieving surface tension on a semiconductor wafer
US6387795B1 (en) 2001-03-22 2002-05-14 Apack Technologies Inc. Wafer-level packaging
US7169685B2 (en) * 2002-02-25 2007-01-30 Micron Technology, Inc. Wafer back side coating to balance stress from passivation layer on front of wafer and be used as die attach adhesive
US6936763B2 (en) 2002-06-28 2005-08-30 Freescale Semiconductor, Inc. Magnetic shielding for electronic circuits which include magnetic materials
US20040018392A1 (en) * 2002-07-26 2004-01-29 Texas Instruments Incorporated Method of increasing mechanical properties of semiconductor substrates
AU2003303784A1 (en) * 2003-01-20 2004-08-13 Systems On Silicon Manufacturing Company Pte Ltd Titanium underlayer for lines in semiconductor devices
JP2005005380A (ja) * 2003-06-10 2005-01-06 Sanyo Electric Co Ltd 半導体装置の製造方法
KR100517075B1 (ko) * 2003-08-11 2005-09-26 삼성전자주식회사 반도체 소자 제조 방법
KR100705937B1 (ko) 2003-12-19 2007-04-11 에스티마이크로일렉트로닉스 엔.브이. 실리콘 질화막의 스트레스를 방지 및 완충하는 패드구조를 구비한 반도체 장치
JP4359535B2 (ja) * 2004-02-06 2009-11-04 アルプス電気株式会社 弾性表面波素子
TWI244725B (en) 2004-05-26 2005-12-01 Advanced Semiconductor Eng Structure and method of forming metal buffering layer
CN101048868B (zh) * 2004-08-20 2010-06-09 佐伊科比株式会社 具有三维层叠结构的半导体器件的制造方法
US7268012B2 (en) * 2004-08-31 2007-09-11 Micron Technology, Inc. Methods for fabrication of thin semiconductor assemblies including redistribution layers and packages and assemblies formed thereby
US7772116B2 (en) * 2005-09-01 2010-08-10 Micron Technology, Inc. Methods of forming blind wafer interconnects
US7863727B2 (en) * 2006-02-06 2011-01-04 Micron Technology, Inc. Microelectronic devices and methods for manufacturing microelectronic devices
US7952213B2 (en) * 2006-03-29 2011-05-31 Macronix International Co., Ltd. Overlay mark arrangement for reducing overlay shift
US7880278B2 (en) * 2006-05-16 2011-02-01 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated circuit having stress tuning layer
TWM481904U (zh) 2014-03-17 2014-07-11 Shengtong Technology Co Ltd 可收合置物籃

Cited By (36)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102414802A (zh) * 2009-05-07 2012-04-11 高通股份有限公司 不连续薄半导体晶片表面特征
CN102414802B (zh) * 2009-05-07 2015-02-18 高通股份有限公司 不连续薄半导体晶片表面特征
CN101887848B (zh) * 2009-05-13 2012-11-14 硅电子股份公司 包括具有前侧和背侧的硅单晶衬底和沉积于前侧上的SiGe层的晶片的生产方法
CN101887848A (zh) * 2009-05-13 2010-11-17 硅电子股份公司 包括具有前侧和背侧的硅单晶衬底和沉积于前侧上的SiGe层的晶片的生产方法
CN102344112A (zh) * 2010-07-30 2012-02-08 飞思卡尔半导体公司 形成加帽的微机电系统(mems)器件的方法
CN102344112B (zh) * 2010-07-30 2016-05-04 飞思卡尔半导体公司 形成加帽的微机电系统(mems)器件的方法
CN104871060A (zh) * 2012-12-17 2015-08-26 旭硝子株式会社 光学元件、光学系统以及摄像装置
US9654676B2 (en) 2012-12-17 2017-05-16 Asahi Glass Company, Limited Optical element, optical system and imaging apparatus
CN104977736A (zh) * 2014-04-09 2015-10-14 群创光电股份有限公司 具有线宽变化的导电层的显示面板
CN105226029B (zh) * 2014-06-25 2018-12-28 环球晶圆股份有限公司 具压应力之硅基板及其制造方法
CN105226029A (zh) * 2014-06-25 2016-01-06 环球晶圆股份有限公司 具压应力之硅基板及其制造方法
CN105448762A (zh) * 2014-08-28 2016-03-30 中国科学院微电子研究所 一种衬底翘曲度的调整方法
CN105448666A (zh) * 2015-12-02 2016-03-30 苏州工业园区纳米产业技术研究院有限公司 利用二氧化硅的应力来改变晶圆硅片基体弯曲度的方法
CN108604572A (zh) * 2015-12-16 2018-09-28 奥斯坦多科技公司 用于改善晶片平面度的方法和由该方法制成的接合晶片组件
CN110383439A (zh) * 2017-03-08 2019-10-25 三菱电机株式会社 半导体装置、其制造方法以及半导体模块
CN110383439B (zh) * 2017-03-08 2023-04-28 三菱电机株式会社 半导体装置、其制造方法以及半导体模块
CN106952812A (zh) * 2017-03-31 2017-07-14 成都海威华芯科技有限公司 一种GaN器件键合方法
CN107845569A (zh) * 2017-11-02 2018-03-27 江苏华功半导体有限公司 一种复合衬底及其制备方法
CN108649034A (zh) * 2018-05-11 2018-10-12 长江存储科技有限责任公司 半导体结构及其形成方法
CN110581050A (zh) * 2018-06-07 2019-12-17 东京毅力科创株式会社 处理方法和等离子体处理装置
CN110581050B (zh) * 2018-06-07 2024-06-11 东京毅力科创株式会社 处理方法和等离子体处理装置
CN111106073A (zh) * 2018-10-26 2020-05-05 株洲中车时代电气股份有限公司 一种功率半导体器件的低应力薄膜结构
CN113169127A (zh) * 2019-05-15 2021-07-23 华为技术有限公司 一种芯片封装装置及其制备方法
CN113169127B (zh) * 2019-05-15 2024-06-25 华为技术有限公司 一种芯片封装装置及其制备方法
WO2020227988A1 (zh) * 2019-05-15 2020-11-19 华为技术有限公司 一种芯片封装装置及其制备方法
CN110634389A (zh) * 2019-08-30 2019-12-31 昆山工研院新型平板显示技术中心有限公司 一种基板的制备方法
CN113035688A (zh) * 2019-12-09 2021-06-25 华润微电子（重庆）有限公司 一种半导体结构及其制作方法
CN113035688B (zh) * 2019-12-09 2023-02-28 华润微电子（重庆）有限公司 一种半导体结构及其制作方法
CN113061861A (zh) * 2019-12-13 2021-07-02 中国科学院大连化学物理研究所 一种大曲率光学元件曲率半径控制方法
CN111394795B (zh) * 2020-04-10 2021-10-15 哈尔滨科友半导体产业装备与技术研究院有限公司 一种去除籽晶残余应力的退火装置及退火方法
CN111394795A (zh) * 2020-04-10 2020-07-10 哈尔滨科友半导体产业装备与技术研究院有限公司 一种去除籽晶残余应力的退火装置及退火方法
CN113555324A (zh) * 2020-04-24 2021-10-26 矽品精密工业股份有限公司 电子封装件
CN111547498A (zh) * 2020-06-01 2020-08-18 上海原能细胞生物低温设备有限公司 一种柔性板架抓取装置及使用方法
CN113078093A (zh) * 2021-03-24 2021-07-06 长江存储科技有限责任公司 制造半导体器件的方法、仿形晶圆
CN113078093B (zh) * 2021-03-24 2022-08-19 长江存储科技有限责任公司 制造半导体器件的方法、仿形晶圆
CN118263137A (zh) * 2024-05-29 2024-06-28 浙江创芯集成电路有限公司 半导体结构的形成方法

Also Published As

Publication number Publication date
US20210375789A1 (en) 2021-12-02
TW200744120A (en) 2007-12-01
US20130140715A1 (en) 2013-06-06
US20070267724A1 (en) 2007-11-22
US11935842B2 (en) 2024-03-19
US9275948B2 (en) 2016-03-01
US20110097893A1 (en) 2011-04-28
US10269730B2 (en) 2019-04-23
TWI337374B (en) 2011-02-11
US8367474B2 (en) 2013-02-05
US20160181209A1 (en) 2016-06-23
US9633954B2 (en) 2017-04-25
US7880278B2 (en) 2011-02-01
US11094646B2 (en) 2021-08-17
US20190252328A1 (en) 2019-08-15
US20170229403A1 (en) 2017-08-10

Similar Documents

Publication Publication Date Title
CN101075588A (zh) 半导体结构、半导体晶片及其制造方法
EP0915503B1 (en) Semiconductor device for use in a light valve device, and process for manufacturing the same
CN1282243C (zh) 具有铜布线的半导体器件
US20120088331A1 (en) Wafer level stack die package
US5003372A (en) High breakdown voltage semiconductor device
CN1913146A (zh) 薄膜导体及其制造方法
CN101038928A (zh) 固体摄像装置及其制造方法
CN1129180C (zh) 半导体器件及其制造方法
CN1805154A (zh) 防止基板变形
EP0936675A3 (en) C-axis oriented thin film ferroelectric transistor memory cell and method of making the same
JP3122213B2 (ja) 被覆または積層ダイヤモンド基板及びその仕上方法
CN1947042A (zh) 热预算解决方案
TW509608B (en) Method for uniform polish in microelectronic device
CN112567521B (zh) 半导体结构及其形成方法
CN1295339A (zh) 具有内在铜离子迁移势垒的低介电常数的介电材料
JP7470070B2 (ja) 半導体装置
JPH10256263A (ja) Ｓｏｉ基板およびその製造方法
CN1855392A (zh) 半导体元件的制造方法及调整元件沟道区晶格距离的方法
CN1231064A (zh) 半导体器件及其制造方法
JPS63237571A (ja) 薄膜トランジスタの製造方法
CN1204616C (zh) 用sige bicmos集成方案制造多晶－多晶电容器的方法
TW200715536A (en) Flash memory structure and method for fabricating the same
CN1855369A (zh) 制造半导体器件的方法
CN1053065C (zh) 集成电路的制造方法
CN1184681C (zh) 双垂直通道薄膜电晶体cmos的制造方法及其产品

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C02 Deemed withdrawal of patent application after publication (patent law 2001)
WD01 Invention patent application deemed withdrawn after publication