TWI337374B - Semiconductor structure, semiconductor wafer and method for fabricating the same - Google Patents

Semiconductor structure, semiconductor wafer and method for fabricating the same Download PDF

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Publication number
TWI337374B
TWI337374B TW095144659A TW95144659A TWI337374B TW I337374 B TWI337374 B TW I337374B TW 095144659 A TW095144659 A TW 095144659A TW 95144659 A TW95144659 A TW 95144659A TW I337374 B TWI337374 B TW I337374B
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Taiwan
Prior art keywords
stress
wafer
adjustment layer
semiconductor
substrate
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TW095144659A
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English (en)
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TW200744120A (en
Inventor
Shin Puu Jeng
Chao Clinton
Szu Wei Lu
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Taiwan Semiconductor Mfg
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Publication of TW200744120A publication Critical patent/TW200744120A/zh
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Publication of TWI337374B publication Critical patent/TWI337374B/zh

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Description

1337374 修正日期：98.12.30 第95144659號專利說明書修正本 九、發明說明： 【發明所屬之技術領域】 本發明是有關於-種積體電路，特别是有關於一種 具有半導體基板之積體電路及其製造方法。 【先前技術】 眾所周知，大部份積體電路係形成在晶圓上，像是 半導體晶8]，代表性地切晶圓。麵十年來，所使用 的晶圓其直徑由原本的二英吋演變至八英吋、十二英 忖’甚至直徑為300釐米的晶圓。 、 目前大份部的積體電路係被製造在八吋的晶圓上， 而大部份新的製賴備純設計絲將積體電路形成於 十一时的晶圓上。 :由於晶圓上所使用到的區域是圓形面積中所能包含 的最的大矩形面積，因此當晶圓直徑增加百分之5〇時（由 八英忖增加至十二英忖），所能用來製造積體電路的矩形 面積會增加至兩倍以上。 另一個積體電路裝置的製程發展趨勢是其封裝技 術。 、 、 隨著表面接著封裝及低剖面封裝等封裝技術的產 -部份的封裝製程中’晶圓被進一步的研 少晶圓的厚度。 。基於上述，如何製造出具有高表面積及低厚度的晶 圓，在半導體製程中逐漸成為重要的研究項目之二。= 0503-A32262TWFl/Ph〇elip 5 1337374 修正日期：98.12.30 第95144659號專利說明書修正本 些研究包括在積體電路製程時，形成複數膜層於晶圓時 對晶圓所造成的壓縮應力、或拉伸強度。形成的膜層包 括介電層（例如層間介電層（inter-layer dielectric、ILD)、 金屬間介電層（inter-metal dielectric、IMD))、姓刻停止 層、及保護層等）、傳導層（例如摻雜之多晶矽層、及金屬 内連結詹。 當先進的積體電路裝置具有七、八、甚至更多層之 金屬内連結層時’加上搭配的層間介電、钱刻停止層、 及保護層’必需形成20甚至更多的膜層於該晶圓片之 然而’如此多膜層所集合施加於該薄型化晶圓上的 應力將造成該晶圓產生顯著的翹曲，也同時影響欲形成 的積體電路裝置。 請參照第1 a圖’係顯示形成於晶圓2上的膜層4其 施加於該晶圓2的應力使得該晶圓2翹曲。如上所述， 這些膜層逐漸累積應力於作為底層之晶圓2，使得晶圓輕 曲。仍請參照第1 a圖，一般未翹曲的晶圓2輪廓係如虛 線6所示；圖示之翹曲程度係為過度表示，目的在表現 形成於晶圓上的膜層對晶圓所產成的鲍曲效果。 自從經過連續製程後的晶圓係分割成複數個獨立的 晶片’因此所形成的晶片同樣被應力所影響。請參照第 1 b圖，係顯示晶片8依形成形上的膜層4的應力使得該 晶片8麵曲。一般未勉曲的晶片8輪廓係如虛線1 〇所示； 圖示之翹曲程度係為過度表示，目的在表現形成於晶片 0503-A32262TWFl/Phoelip 6 1337374 修正日期：98.12.30 第95144659號專利說明書修正本 上的膜層對晶片所產成的翹曲效果。 ⑨形成於晶圓上賴層所造成的-曲會造成幾種不利 的影響。其中之-就是增加晶圓處的困難度及晶圓在連 續的製程下損壞的可能性。 此外’該輕曲的晶圓8會直接影響到形成於其上的 電子裝置的電性性質。料週知的，過度的應力（由晶圓 8龜曲所造成）會對_8電晶體内之半導體膜層其電荷載 體之遷移率（mobility)造成不利的影響。 因此，為符合目前半導體元件製程上的需求，發展 出避免晶圓翹曲的結構及製程方法，是半導體技術的研 發重點之一。 【發明内容】 有鑑於此，本發明的目的係提供一種半導體結構及 晶圓，具有一應力調整層，有效避免晶圓（wafer)翹曲， 推持積體電路的效能。 根據本發明一較佳實施例，該半導體結構包含：一半 導體基板，具有一厚度大體小於150μιη，其中該半導體 基板具有-第-表面及第二表s;—應力調整層形成於 該基板之第-及第二表面其中之一者上，以大體補償或 平衡該半導體基板之—應力；以及複數之接合墊形成於 該第一表面之上。 本發明之另一較佳實施係提供一半導體晶圓，其厚 度大體小於150μιη，包含：一第一及一第二表面、複數 050j-Aj2262TWFl/Phoelip 第95144659號專利說明書修正本 ^ 修正曰期：98.12.30 螬膜（fUm)形成於該第一表面，其 晶=:應:一並補償或平衡該施於半導體 沾j發月之其他較佳實施係提供—種形成半導體結構 含：提供一具有一第一表面及-第二表面之 +導體基板’其中該半導體基板之厚度大體係小於 广、形成複數膜層於該基板之第一表面，該複數膜層 係把加-應力於該半導體基板之上，以及，形成一應力 調整層於該第-表面及第二表面其巾之—者之上，並補 償或平衡該複數膜層施於半導體晶圓上之該應力。 為使士發明之上述目的、特徵能更明顯易懂，下文 特舉較佳實施例，並配合所附圖式，作詳細說明如下： 【實施方式】 叫，閱第2a圖至2c圖，係顯示符合本發明所述之 顯不裝置其半導體結構的—較佳實施例，其製程流程剖 面圖半‘體晶圓12具有複數的膜層9、11、及13形 成於其上’其中在此所述之該複數的膜層9、11、及13 係總稱為薄膜(film or films) 14。雖然在此係以三層 膜層病表示’但減本發明之精神，—習知之此技藝之 人士可將本發明施行至其他具有不同膜層數的半導體製 程上以形成積體電路。 在此一較佳實施例中，該晶圓12係為一矽晶圓，其 0503-A32262TWF1 /Phoelip 1337374 第95丨44659號專利說明書修正本 修正日期：98.12.30 從可為8英吋、12英吋、或16英吋及其以上。血 的矽晶圓12其厚度係約為620 /z IB。在本發明另—較佳趣 施例中，該晶圓12亦可為具有—薄半體層形成於；上二 埋層氧化物所構成的矽晶圓，也就是所謂的絕緣層上覆 石夕（silicon on insulator、SOI)。 薄膜14係為複數之膜層所構成，該複數之膜層可為 典型用於積體電路製程的任何膜層。該薄膜14係形成於 該晶圓12之上表面，而該晶圓12係作為一基板。這些複 數之膜層11、12及13可例如為摻雜之多晶矽（d〇—ped P〇lysilicon)用於作為閘電極、蝕刻停止層、層間介電 層（ILD)、金屬間介電層（IMDs)、金屬電結層、或是相關 類似膜層。一般來說，在該複數膜層對頂端係為一保護 層，用以所形成的積體電路遭受到外界的污染或是水氣 的影響。 ' 一個典型的積體電路一般來說會具有8層金屬層以 及相對應數量的金屬間介電層及蝕刻停止層，因此在積 體電路的製造過層中，一般會有超過2〇層以上的膜層形 成於晶圓表面，而該不同之膜層係以不同的製程方法所 形成，例如化學氣象沉積法（CVD)、電壓輔助氣象沉積法 (PEVD) ’原子層 >儿積法（ald)、进鍍法（SpUttering)、電 鍍法、無電鍍法等。 該複數之膜層之形成溫度係介於400度上下。在沉積 步驟時’所形成之臈層不會對其下之膜層施加應力。然 而’在沉積完成後，由於溫度回歸至室溫，各膜層及晶 0503-A32262TWFl/Ph〇elip 9 1337374 修正日期：98.12.30 第95144659號專利說明書修正本 圓之不同膨脹係數同時施加於該結構體中。因此，該複 數之膜層可視為係施加一總合之應力於位於最底之基晶 12。而該應力报容易造成晶圓翹曲，如第1&圖:1]3圖所示。 該應力有可能為一壓縮應力（c〇mpressi〇n stress)或為 一拉伸應力（tensile stress)。一般而言，對於的製 程，該複數的膜層一般係對該晶圓造成一拉伸應力。此 外，該複數的膜層亦有可能對該晶圓造成一拉伸應力。 請參照第2a圖，該晶圓具有一厚度，一般來說是62〇#m。 然而，以目前技術來說，為利於封裝或形成覆晶的結構， 一般會對該晶圓施以研磨製程以削減其厚度。 請參照第2b圖，形成一保護層16於該薄膜14之上表 面。值得注意的是，一般來說該保護層16係在該積體電 路完成後才加以形成於該晶圓12之上。仍請參照第2b 圖，複數之接合墊20係形成該薄臈14之最上層的膜層13 之間。此接合墊20係用來將此積體電路裝置於外在電路 結合之作，以般係形成於保護層之前。該保護層16除了 可避免形成於基圓上的複數膜層遭受到外界的損害，亦 可在進行後續背面研磨時保護該積體電路。在形成保護 層後’該曰曰日圓12係進行一背面研磨，以減少其晶圓的厚 度，請參照2c圖。該背面研磨可為習知之任何方法，在 此不加贅述。 經過該背面研磨後，該晶圓12之厚度可以減少至 75#m(3mils)或是小於5〇//m(2miis)，甚至是 mil)。值得注意的是該保護層在背面研磨仍在該複數之 0503-A32262TWF1 /Phoelip 10 1337374 修正日期：98.12.30 第95144659號專利說明書修正本 膜層上以提供該晶圓支撐力，且避免該晶 層所施與之應力而㈣。接著，仍請參照g2e圖複= 力調整層18係形成於該晶圓12之背面或是底部。其中， 該應力調整層本身具有一應力大於lxl〇8 dyne/cm2。在此 實施例中，該應力調整層18係形成於之一表面，而應 力調整層18所形成之表面係為形成有該薄賴的表面的 相反側。在一較佳實施例中，該薄膜14係施與一拉伸應 力於該晶圓12,會造成該晶圓12朝箭頭方向17翹曲， 造成如第la圖所示的結果。值得注意的是，由於該保護 層16仍形成於該晶圓12之上，因此該保護層16可避免該 翹曲發生。然而，在進行積體電路的的封裝時，該保護 層16必需去除以露出該複數之接觸墊。所以，在移除該 保護層之前必需形成該應力調整層18於該晶圓12。由於 該，力調整層18亦同時提供一拉伸應力於該晶圓12(請 見箭頭方向19)，因此可以補償或平衡由薄膜14施於晶圓 上之應力。在該應力調整層丨8形成後，移除該保護層 及進行後續的封裝製程。 β一熟知此技藝之人士可利用不同之材料及調整不同 的厚度以不同的形成方法來形成該應力調整層18於該晶 圓12由於考慮到不影響後續該積體電路的封裝及不增 加該積體電料總厚度，因此該應力調整層18之厚度係 ^可犯的小。在本發明一較佳實施例中，該應力調整層 18具有—厚度小於2G#m。該應力調整層18之材質可為 介電材料，例如氮切、氧切、氮氧切等，形成方 0503-Aj2262TWF 1 /Phoelip 11 1J37374 第95144659號專利說明書修正本 修正日期：98.12.30 甩:為S头任何形成介電層的方式。此外’該應力調整 曰：亦I為l0W-k介電材料、聚亞醯胺、或是玻璃、塑膠、 陶瓷、榼封材料（m〇lding c〇mp〇und)等。該介電 ^料可例如為摻雜碳的氧化石夕、摻雜氟的氧化碎、或是 碳化石夕。 ^在本發明另一較佳實施例中，—傳導層像是鎳、鉻 等亦可作為該應力調整層18。該等材料除了可平衡應力 ^，亦可提供較佳之熱傳導及晶圓之接地電容…般來 說，適合該應力調整層18的材料其形成溫度一般需小 = 400度，這是為避免對先前所形成積體電路製程造成 影響。若形成溫度大於4〇〇度時，有可能像是造成摻雜離 子的遷移。 在移除該保護層16後，即可露出該複數之接合墊 2〇，以利於外在電路利用導線與該接合墊2〇電性連結。 在本發明一較佳實施例中，該積體電路（晶片）亦可以覆 晶（flip chip)的方式進行組裝。 該應力調整層18可坦覆性形成於該晶圓之上，亦可 進一步圖形化《圖形化該應力調整層18的目的係在於調 節施加於該晶圓上的應力。請參照第如圖，係為一平面 示意圖，顯示一未被圖形化之應力調整層18。請參照第 3b圖，係顯示該應力調整層18被進一步圖形化以形成複 數之圓形構槽22，以形成不同區塊的應力調整層18來調 節應力。請參照第3c圖’係顯示該應力調整層被進一步 圖形化以形成複數之條狀構槽22，以形成不同區塊的應 0503-A32262TWFl/PhoeIip 12 1337374 第95144659號專利說明書修正本 修正日期：98.12.30 力調整層18來調節應力。在树明其他較佳實施例中， 該應力調整層18被圖形化以形成較寬的圖形，或是移除 位於晶圓邊緣的應力調整層18，或是輯形成之晶片區 域圖形化該應力調整層18。此外，在圖形化該應力調整 層_1可依需要形成具有不同厚度的應力調整層… 請蒼照第湖，係為該晶隨之上示圖，顯示形成 於其上的積體電路圖形，而第3d圖也是顯示第3心圖所 示之平面圖的相反側，中可知，複數條切割線24橫 跨該曰曰圓12，以定義出複數個晶片％，該晶片26的長寬 tl及t2係約為20_或以上。若是施加於該晶㈣的應力 沒有移除的話’同樣的應力亦會使該晶片2_曲。依據 本發明，由於係進一步形成一應力調整層18於該晶圓， 因此即使該晶片26的尺寸大於2〇"mx2〇#m或以上，亦不 會翹曲變形。 清參照第4a圖’係顯示本發明其他較佳實施例所述 之具有應力調整層18的晶圓12，值得注意的是，該應力 調整層18亦可於與該薄膜14形成在該晶圓12的同侧 表面°值得注意的是’該應力調整層18係在完成積體 電路的製程後所形成的，因此該應力調整層18係為一額 =卜开^成的膜層，並非屬於該積體電路本身的膜層，亦不 =作為保護層。而該保護層16可進一步形成於該應力調 正層18之上，請參照第4b圖。在形成該應力調整層18 之後’該晶圓12可進一步進行一背面研磨製程（研磨至 虛線25)，以減少其厚度。此外，請參照第扑圖，由於 〇5〇3-A32262TWFl/Phoelip 13 1337374 第95144659號專利說明書修正本 修正日期：98.12.30 該晶圓之複數膜層侧14以形成有該應力調整層18，因此 所形成的保護層16之厚度可以較一般的來得薄。 薄膜14所造成之應力會使晶圓12朝箭頭方向Η翹 曲，而該應力調整層18係同時提供一拉伸應力於該晶圓 12(箭頭方向19)，因此可避免該晶圓翹曲。這也是$該 應力調整層18所提供的應力作用方向係該薄膜所施加於 該晶圓的應力方向相反。 第5a圖及第5b圖係為剖面結構圖，係顯示本發明較 佳實施例中所述之晶圓以覆晶（n i p _ c h i p)方式^行封 裝。請參照第5a圖，如第2c圖所示之晶圓12在移除掉該 保護層16後，係反過來配置於一支撐基板3〇上，其中該 晶圓12之接合墊20係以該焊料或焊球32與該支擇基板％ 電性連結。當該晶圓12順利與該支撐基板3〇接合後，一 填充材（例如樹脂）會用來填充該晶圓〗2與該支禮基板3 〇 之間的空隙’因此該填充材亦會提供該晶圓一應力，避 免該晶圓12翹曲。所以在形成該支撐材後，可以選擇將 該應力調整層18移除。 請參照第5b圖，該應力調整層18具有複數之開口， 而每一開口係填入一接合墊20，該接合墊2〇係用以將積 體電路與外界電路電性連結。當該晶圓12順利與該支撐 基板30接合後’一填充材（例如樹脂）會用來填充該晶圓 12與該支撐基板30之間的空隙’因此該填充材亦會提供 該晶圓一應力，避免該晶圓12翹曲。 第6a圖及第6b圖為剖面結構圖，係顯示本發明較佳 0503-A32262TWF1 /Phoelip 14 Ϊ337374 修正日期：98.12.30 第95144659號專利說明書修正本 實施例中所述之晶圓以導線方式進行封裝。請參照第h 圖’該應力調整層18係形成於該晶圓之背面，並配置於 一支撑基板30上·其中，一膠層34將係用來將晶圓I〗固 定於該支撐基板30上。此外，形成在晶圓上的接合墊係 利用導線38與外在電路的接觸端36(lea(J finger)電性連 結。在完成該封裝後一塑膠或陶瓷材料可進一步行成於 該晶圓之上用來保s蒦該晶圓12上的積體電路a請夫照第 6b圖，該應力調整層18係形成於該晶圓12上並與該膜層 14同一側’該應力調整層18具有複數之開口，而每一開 口係填入有該接合墊20，該接合墊係利用導線38與外在 電路的接觸端36 (lead finger)電性連結。 請參照第7圖，係說明形成有不同厚度與材質之膜層 的晶圓’其尺寸與輕曲量的關係。在第7圖中，該符號NJT 係代表該膜層係為矽化氮層、AI係代表該膜層係為鋁金 屬層、及pi係代表該膜層係為聚亞醢胺，在νπ、αι、ρι 後的數值係代表該應力調整層的厚度；在@後的係為該晶 圓的材質’ Si代表為石夕晶圓’而Si後的數值係代表該晶 圓的厚度。由圖中可知，該翹曲量會依晶圓的尺寸的增 加而增大，像是厚度為lmi 1的矽晶圓其翹曲量（見曲線 101及103) ’係為厚度為29mil的矽晶圓之翹曲量（見曲線 105及107)來得大上百倍以上。 雖然本發明已以一較佳實施例揭露如上，然其並非 用以限定本發明，任何熟習此技藝者，在不脫離本發明 之精神和範圍内，當可作些許之更動與潤飾，因此本發 〇503-A32262TWFl/Phoelip 1337374 第95144659號專利說明書修正本 修正曰期：98.12.30 明之保護範圍當視後附之申請專利範圍所界定者為準。 16 0503-A32262TWFl/Phoeiip 1337374 修正日期：98.12.30 第95144659號專利說明書修正本 【圖式簡單說明】 第la圖係顯示習知半導 剖面示意圖。 千导媸s曰圓因應力關係而翹曲之 第lb圖係顯示習知半導體 剖面示意圖 々u應力關係而翹曲之 第2 a 2 c圖係顯不本發明一較隹管：始如丄 力锢敏门 权佳貫轭例所述包含應 力調整層之aB 5)的製造流程剖面示意圖。 力調較佳實施例所述包含應 整層·!㈣—龍㈣觸私含應力調 第4a〜4b圖係顯示本發明另一較佳實施例所述包含 晶圓的剖面示意圖，其中該應力調整層係 /、該積體電路形成至同一側。 第5a ®及第5b圖係為剖面結構圖’係顯示本發明 佳實施例中所述之晶圓以覆晶（flip-chip)方式進行封 裝。 —第6a圖及第6b圖為剖面結構圖，係顯示本發明較 佳實施例中所述之晶圓以導線方式進行封裝。 第7圖係說明形成有不同厚度與材質之膜層的晶 圓’其尺寸與翹曲量的關係。 明 膜層〜4 ; 【主要元件符號說 晶圓〜2 ; °5〇3-A32262TWF]/Ph〇e|ip 17 1337374 第95144659號專利說明書修正本 虛線〜6 ; 半導體晶圓〜12 ; 薄膜〜14 ; 箭頭方向〜17 ; 箭頭方向〜19 ; 條狀（圓形）構槽〜22 ; 虛線〜2 5， 支撐基板〜30 ; 膠層〜34 ; 導線〜38 ; 曲線〜101、103、105、 修正日期：98.12.30 虛線〜10 ; 膜層〜9、11、及13 ; 保護層〜16 ; 應力調整層〜18 ; 接合墊〜20 ; 切割線〜24 ; 晶片〜26 ; 焊球〜32 ; 接觸端〜36 ; 109 ° 0503-A32262TWFI/Phoelip 18

Claims (1)

  1. I33737r4 _f * 修正
    第95M4659號申請專利範圍修正本 十、申請專利範圍： ]· 一種半導體結構包含： 半導體基板，具有一厚度大體小於150 "，其中 該半導體基板具有_第_表面及—第二表面；〃 一一應力調整層形成於該基板之第—及第二表面其中 ，者上’以大體補償或平衡該半導體基板之-應力， :、該應力調整層具有複數之圓形構槽，以調節應力； 以及 複數之接合墊形成於該第一表面之上。 2·如申請專利範圍第1項所述之半導體結構， 該應力調整層具有—厚度小於2一。 -中 3.如申請專利範圍第w所述之半導體結構， “力調整層本身具有一應力大於i⑽8 dyne/cm2。 %申請專利範圍第1項所述之半導體結構，其中 遠半¥體基板具有—厚度小於乃㈣。 " 令半5導^77專㈣圍第4項所述之半導#結構，其中 該丰v組基板具有一厚度小於5〇#m。 兮《Λ· ^請專㈣㈣1賴述之半導體結構，且中 忒應力凋整層係形於該基板之第二表面上。 /、 Μ料利觀第1韻述之半導體結構，1中 “應力調整層係形成於該基板之第—表面上，^ =力調整層包含複數之開σ露出該形成於其下的接觸 8·如申請專利範圍第i項所述之半導體結構，其中 0503.A32262TWF,/Ph〇ei Φ 19 1337374 第95腦9綱树祕正本 修正w 該應力調整層之材料係擇自於由氮化矽、氧化矽、氮氧 化矽氮氧化矽、聚亞醯胺、玻璃、塑膠、陶瓷、模封材 料（molding compound)、及其混合物所組成之族群。 9. 如申請專利範圍第丨項所述之半導體結構，其中 該應力調整層包^—電性傳導層。 10. —種半導體晶圓，其厚度大體小於15〇以m，包 含： 一第一及一第二表面； 複數薄膜形成於該第一表面，其中該複數之薄膜累 積一應力於該半導體晶圓；以及 、’' 一應力調整層形成於該第一及第二表面其中之一之 上，並補償或平衡該施於半導體晶圓上之該應力，其中 該應力调整層具有複數之圓形構槽，以調節應力。 n.如申請專利範圍第10項所述之半導體晶圓，其 中該半導體晶圓具有—直徑大體為12英吋。 12..如申請專利範圍第1〇項所述之半導體晶圓，其 中該半導體晶圓具有一直徑大體為16英吋。 13. 、如申請專利範圍帛10項所述之半導體晶圓，其 中該半導體晶圓具有_厚度大體小於75"m。 14. 如申請專利範圍帛13項所述之半導體晶圓，其 中該半導體晶圓具有-厚度大體小於50㈣。 1日5. -種半導體結構的製造方法，包含： 提供具有一第-纟面及一第二表面之半導體基 板’其中該半導體基板之厚度大體係小於150"m; 0503-A32262TWFl/Phoelip 20 ^37374 修正日期：99.5.25 第95144659號申請專利範圍修正本 升/成複數膜層於該基板之第一表面，該複數膜層係 施加一應力於該半導體基板之上；以及 、 形成一應力調整層於該第一表面及第二表面其中之 一者之上，並補償或平衡該複數膜層施於半導體晶圓上 之該應力，其中該應力調整層具有複數之圓形構槽。 16.如申請專利範圍第15項所述之半導體結構的製 造方法’在形成該應力調整層前，更包含··
    移除一部份之第二表面側的半導體基板。 ^ Π.如申請專利範圍第16項所述之半導體結構的製 以方法，其中該半導體基板在移除步驟後，具有一厚产 大體小於75 ym。 X ^丨8.如申請專利範圍第15項所述之半導體結構的製 4方法其中該複數膜層所施加之應力係為一逐漸累積 之拉伸張應力，而該應力調整層係提供一壓縮應力。
    &丨9.如申請專利範圍第16項所述之半導體結構的製 4方法其中在移除該部份之基板前，配置一保護芦 該半導體基板之第—表面。 曰、 ^ 20.如申請專利範圍第16項所述之半導體結構的製 &方法’其中該應力調整層係形成於該基板之第一表 面，且在形成該應力調整層的的步驟中可包含形成複數 之開口路出該形成於該應力調整層之下的接觸墊。 ^〇3-A32262TWF,/ph〇e|ip 21 1337374 第95144659號專利說明書修正本 修正曰期：98.12.30 七、指定代表圖： (一） 本案指定代表圖為：第（2c)圖。 (二） 本代表圖之元件符號簡單說明： 半導體晶圓〜12 ; 膜層〜9、11、及13 ; 薄膜〜14 ; 保護層〜16 ; 箭頭方向〜17 ; 應力調整層〜18 ; 箭頭方向〜19 ; 接合墊*〜20。 八、本案若有化學式時，請揭示最能顯示發明特徵的化學式： 0503-A32262TWFl/Phoelip 4
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