WO2024088211A1 - 封装结构、封装结构的制备方法和电子设备 - Google Patents

封装结构、封装结构的制备方法和电子设备 Download PDF

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Publication number
WO2024088211A1
WO2024088211A1 PCT/CN2023/125922 CN2023125922W WO2024088211A1 WO 2024088211 A1 WO2024088211 A1 WO 2024088211A1 CN 2023125922 W CN2023125922 W CN 2023125922W WO 2024088211 A1 WO2024088211 A1 WO 2024088211A1
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WIPO (PCT)
Prior art keywords
chip
conductive member
layer
wiring layer
groove
Prior art date
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PCT/CN2023/125922
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English (en)
French (fr)
Inventor
金豆
Original Assignee
维沃移动通信有限公司
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Filing date
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Application filed by 维沃移动通信有限公司 filed Critical 维沃移动通信有限公司
Publication of WO2024088211A1 publication Critical patent/WO2024088211A1/zh

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49838—Geometry or layout
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H01L23/13—Mountings, e.g. non-detachable insulating substrates characterised by the shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/18—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Definitions

  • the present invention relates to the field of semiconductor packaging technology, and in particular to a packaging structure, a method for preparing the packaging structure, and electronic equipment.
  • Fan-out packaging technology gets rid of the range limitation of conventional chips and can integrate multiple chips in the package.
  • the chip is mounted in the groove of the substrate with the chip facing upward in the packaging structure, that is, the electrical connection surface of the chip faces the notch direction of the groove of the substrate, so as to realize the electrical connection between the chip and other circuit structures.
  • the packaging structure In order to eliminate the step difference between the chip in the groove and the substrate at the notch of the groove, it is necessary to lay a thicker insulating dielectric layer on the surface of the notch of the groove to eliminate the difference. Laying a thicker insulating dielectric layer on the surface of the notch of the groove will cause the packaging structure to have a larger overall thickness.
  • the invention discloses a packaging structure, a method for preparing the packaging structure and an electronic device, so as to solve the problem of large overall thickness of the packaging structure in the related art.
  • the present application discloses a packaging structure, including a substrate, a first chip, a first conductive
  • the substrate comprises a first conductive member and a first filling glue layer
  • the substrate is provided with a groove
  • the bottom wall of the groove is provided with a first wiring layer
  • the first chip is provided in the groove
  • the first surface of the first chip is electrically connected to the first wiring layer
  • one end of the first conductive member is electrically connected to the first wiring layer
  • the first filling glue layer is filled in the groove
  • the first filling glue layer is flush with the surface where the notch of the groove is located
  • the other end of the first conductive member and the second surface of the first chip are both exposed in the first filling glue layer, and are both flush with the surface where the notch of the groove is located
  • the first surface of the first chip and the second surface of the first chip are opposite to each other
  • the first surface of the first chip is the electrical connection surface of the first chip.
  • the present application discloses an electronic device, comprising the packaging structure described in the first aspect.
  • the present application discloses a method for preparing a packaging structure, comprising:
  • a groove is formed on the substrate
  • a grinding process is performed on the side of the first filling glue layer facing away from the substrate so that the first filling glue layer is flush with the surface where the notch of the groove is located, and the other end of the first conductive part and the second surface of the first chip are exposed from the first filling glue layer, wherein the first surface of the first chip is opposite to the second surface of the first chip.
  • the package structure disclosed in the embodiment of the present application is provided with a first wiring layer on the bottom wall of the groove opened on the substrate, so that the first surface of the first chip can be electrically connected to the first wiring layer, one end of the first conductive member is electrically connected to the first wiring layer, and then after the first filling glue layer is filled in the groove, the first conductive member is electrically connected to the first wiring layer.
  • the other end of the electrical component and the second surface of the first chip are exposed in the first filling glue layer.
  • the side of the first filling glue layer facing away from the first chip can be polished to make the second surface of the first chip, the other end of the first conductive component and the first filling glue layer flush, thereby avoiding the formation of a step difference between the first chip and the notch of the groove.
  • the packaging structure can be thinned by polishing, thereby solving the problem of thick packaging structure in related technologies.
  • FIG1 is a schematic diagram of a packaging structure disclosed in an embodiment of the present invention.
  • FIG2 is a partial schematic diagram of FIG1 ;
  • FIG3 is a schematic diagram of a structure in which a groove is provided on a substrate
  • FIG4 is a schematic diagram of preparing a first wiring layer and a first conductive member on the bottom wall of a groove
  • FIG5 is a schematic diagram showing electrical connection between a first chip and a first wiring layer
  • FIG6 is a schematic diagram after the first filling glue layer is filled
  • FIG7 is a schematic diagram of the first filling rubber layer after grinding
  • FIG8 is a schematic diagram after the first dielectric layer and the second wiring layer are provided.
  • FIG9 is a schematic diagram showing electrical connection between the second chip and the second wiring layer
  • FIG10 is a schematic diagram after the second conductive member is provided.
  • FIG11 is a schematic diagram after setting a second filling glue layer
  • FIG12 is a schematic diagram of the second filling rubber layer after grinding
  • FIG. 13 is a flow chart of a method for preparing a packaging structure.
  • references numerals 110-base, 111-groove, 120 - first chip, 130 - first conductive member, 140 - first filling glue layer, 150 - first wiring layer, 210 - first dielectric layer, 220 - second wiring layer, 310 - second chip, 320 - second filling glue layer, 330 - second conductive member, 410 - second dielectric layer, 420 - third wiring layer, 510 - a third conductive element.
  • an embodiment of the present invention discloses a packaging structure, and the disclosed packaging structure includes a substrate 110 , a first chip 120 , a first conductive member 130 and a first filling glue layer 140 .
  • the substrate 110 is provided with a groove 111, and the bottom wall of the groove 111 is provided with a first wiring layer 150.
  • the first wiring layer 150 can be a single layer or multiple layers. There is no specific restriction on the number of layers of the first wiring layer 150, and wiring can be performed according to actual conditions.
  • the first chip 120 is provided in the groove 111, and the first surface of the first chip 120 is electrically connected to the first wiring layer 150. The first surface of the first chip 120 is the electrical connection surface of the first chip 120.
  • the first surface of the first chip 120 and the first wiring layer 150 can both be provided with micro-bumps, and the micro-bumps on the first surface of the first chip 120 are used to bond with the micro-bumps of the first wiring layer 150 to achieve electrical connection between the first chip 120 and the first wiring layer 150.
  • the first conductive member 130 is electrically connected to the first wiring layer 150, and the first filling glue layer 140 is filled in the groove 111, and the first filling glue layer 140 is flush with the surface where the notch of the groove 111 is located, so that the first filling glue layer 140 wraps the first conductive member 130 and the portion of the first chip 120 located in the groove 111 to package the first chip 120.
  • the first conductive member 130 can be a copper column, and of course, the first conductive member can also be other conductive members.
  • the other end of the first conductive member 130 and the second surface of the first chip 120 are exposed in the first filling glue layer 140 and are flush with the surface where the notch of the groove 111 is located.
  • the other end of the first conductive member 130 is used to be electrically connected to other external circuits or components, so that the first chip 120 passes through the first chip 120 in sequence.
  • the first surface of the substrate 120 , the first wiring layer 150 , and the first conductive member 130 are electrically connected to other external circuits or components.
  • the first surface of the first chip 120 and the second surface of the first chip 120 are opposite to each other, and the first surface of the first chip 120 is the electrical connection surface of the first chip 120.
  • the second surface of the first chip 120 can be used to encapsulate the circuit structure in the first chip 120, and does not constitute the circuit structure of the first chip 120.
  • the second surface of the first chip 120 can be at a distance from the circuit structure of the first chip 120, so that the second surface of the first chip 120 can be polished.
  • a groove 111 is etched on the substrate 110, the size of the groove 111 is larger than the size of the first chip 120, a first wiring layer 150 is prepared on the bottom wall of the first groove 111, and a first conductive member 130 is prepared; then, the first surface of the first chip 120 is electrically connected to the first wiring layer 150, and the first conductive member 130 is located between the first chip 120 and the side wall of the groove 111; after the first chip 120 is electrically connected to the first wiring layer 150, a colloid is filled into the groove 111 to form a first filling glue layer 140.
  • the second surface of the first chip 120 can be higher than the surface where the notch of the groove 111 is located, or it can be lower than the surface where the notch of the groove 111 is located, the first filling glue layer 140 at least covers the notch of the groove 111, and the first filling glue layer 140 can also be higher than the surface where the notch of the groove 111 is located to form a glue layer.
  • the side of the first filling glue layer 140 facing away from the substrate 110 is polished to expose the other end of the first conductive member 130 from the first filling glue layer 140 for electrical connection with other circuit structures.
  • polishing the layer of the first filling glue layer 140 facing away from the substrate 110 can reduce the overall thickness of the packaging structure, and the first chip 120 is flush with the surface where the notch of the groove 111 is located without any step difference.
  • the package structure disclosed in the embodiment of the present application is provided with a first wiring layer 150 on the bottom wall of the groove 111 opened on the substrate 110, so that the first surface of the first chip 120 can be electrically connected to the first wiring layer 150, and one end of the first conductive member 130 is electrically connected to the first wiring layer 150, and then after the first filling glue layer 140 is filled in the groove 111, the other end of the first conductive member 130 and the second surface of the first chip 120 are exposed in the first filling glue layer 140.
  • the connecting surface can be processed by grinding the side of the first filling glue layer 140 facing away from the first chip 120 to make the second surface of the first chip 120, the other end of the first conductive member 130 and the first filling glue layer 140 flush, thereby avoiding the formation of a step difference between the first chip 120 and the notch of the groove 111.
  • the packaging structure can be thinned by grinding, thereby solving the problem of thick packaging structure in related technologies.
  • the second surface of the first chip 120 can be ground to make the first chip 120 thinner. The thinner first chip 120 is also beneficial to the heat dissipation of the first chip 120.
  • the packaging structure may also include a first dielectric layer 210 and a second wiring layer 220.
  • the first dielectric layer 210 may be disposed on the substrate 110 and cover the notch of the groove 111.
  • the second wiring layer 220 may be disposed in the first dielectric layer 210.
  • the other end of the first conductive member 130 may be electrically connected to the second wiring layer 220.
  • the first dielectric layer 210 By arranging the first dielectric layer 210 on the substrate 110, and the first dielectric layer 210 covers the notch of the groove 111, the first dielectric layer 210 can further protect the first chip 120, so that the first chip 120 can be better packaged in the groove 111, and by arranging the second wiring layer 220 in the first dielectric layer 210, the second wiring layer 220 can be protected by the first dielectric layer 210, and after the other end of the first conductive member 130 is electrically connected to the second wiring layer 220, the other end of the first conductive member 130 can have a more flexible electrical connection method with other circuit structures through the second wiring layer 220.
  • Multiple grooves 111 may be arranged at intervals, multiple first chips 120 may be arranged in a one-to-one correspondence in multiple grooves 111, and multiple first conductive members 130 surrounding the corresponding first chip 120 may be arranged in each groove 111, and the other ends of the multiple first conductive members 130 are electrically connected through the second wiring layer 220.
  • the multiple first chips 120 may be different chips, and of course, the multiple first chips 120 may also be the same chip.
  • a plurality of grooves 111, a plurality of first chips 120 and a plurality of first conductive members 130 are provided.
  • the plurality of first chips 120 are provided in a one-to-one correspondence in the plurality of grooves 111.
  • Each groove 111 is provided with a plurality of first conductive members 130 surrounding the corresponding first chip 120.
  • the other ends of the first chips 120 are electrically connected through the second wiring layer 220 , so that the plurality of first chips 120 can be electrically connected through the second wiring layer 220 .
  • the package structure may optionally further include a second chip 310, which may be disposed on a side of the first dielectric layer 210 away from the first chip 120, and the second chip 310 may be electrically connected to the second wiring layer 220.
  • the second chip 310 and the first chip 120 may be electrically connected through the second wiring layer 220.
  • the second chip 310 is arranged on the side of the first dielectric layer 210 away from the first chip 120, so that the integration capability of the packaging structure is higher, and the second chip 310 is electrically connected to the second wiring layer 220, so that the electrical connection between the second chip 310 and the first chip 120 can be achieved, thereby realizing information interaction between multiple chips.
  • the second chip 310 is arranged on the side away from the first chip 120, which can avoid the problem of the first chip 120 and the second chip 310 being arranged on the same side, resulting in a longer overall length of the packaging structure.
  • the packaging structure can also include a second filling glue layer 320 and a second conductive member 330.
  • the second filling glue layer 320 is connected to the first dielectric layer 210 and covers the second chip 310 and the second conductive member 330.
  • the first end of the second conductive member 330 is electrically connected to the second wiring layer 220.
  • the second surface of the second chip 310 and the second end of the second conductive member 330 are exposed on the surface of the second filling glue layer 320.
  • the second surface of the second chip 310 is opposite to the first surface of the second chip 310.
  • the first surface of the second chip 310 is the electrical connection surface of the second chip 310.
  • the second surface of the second chip 310 is at a distance from the circuit structure of the second chip 310.
  • the second surface of the second chip 310 can be polished to be thinned, or other processes can be performed on the second surface of the second chip 310.
  • a second filling adhesive layer 320 is provided to cover the second chip 310 and the second conductive member 330.
  • the second filling adhesive layer 320 can cover the second surface of the second chip 310 and the second end of the second conductive member 330 and then perform a film treatment to The second surface of the second chip 310 and the second end of the second conductive member 330 are exposed on the surface of the second filling layer 320.
  • the second filling layer 320 when the second filling layer 320 is filled, the second surface of the second chip 310 and the second end of the second conductive member 330 are directly exposed on the surface of the second filling layer 320.
  • the side of the second filling layer 320 facing away from the first filling layer 140 can be polished so that the second surface of the second chip 310 and the second end of the second conductive member 330 are exposed on the surface of the second filling layer 320. This can ensure that the second surface of the second chip 310 and the second end of the second conductive member 330 are flush with the second filling layer 320.
  • the thickness of the second filling layer 320 can be reduced by polishing, thereby reducing the overall thickness of the packaging structure.
  • the first surface of the second chip 310 is electrically connected to the second wiring layer 220
  • the second filling glue layer 320 is connected to the first dielectric layer 210 and covers the second chip 310 and the second conductive member 330
  • the first end of the second conductive member 330 is electrically connected to the second wiring layer 220
  • the second surface of the second chip 310 and the second end of the second conductive member 330 are exposed on the surface of the second filling glue layer 320, so that the second filling glue layer 320 can protect the second chip 310
  • the second end of the second conductive member 330 is exposed on the second filling glue layer 320, so that the second wiring layer 220 can be electrically connected to the external circuit.
  • the second conductive member 330 may be a copper core ball.
  • the copper core ball may include a copper ball, a nickel-plated layer, and a tin-plated layer.
  • the nickel-plated layer and the tin-plated layer may be coated on the copper ball to form a composite copper core ball.
  • the packaging structure may also include a second dielectric layer 410 and a third wiring layer 420.
  • the second dielectric layer 410 may be disposed in the second filling glue layer 320 and cover the second surface of the second chip 310 and the second end of the second conductive member 330.
  • the third wiring layer 420 may be disposed in the second dielectric layer 410, and the second end of the second conductive member 330 is electrically connected to the third wiring layer 420.
  • the second dielectric layer 410 can cover the second surface of the second chip 310 and the second end of the second conductive member 330 to better package the second chip 310 and the second conductive member 330, and can also protect the second chip 310 and the second conductive member 330.
  • the third wiring layer 420 is provided in the second dielectric layer 410, so that the second dielectric layer 410 can protect the third wiring layer 420.
  • the second end of the second conductive member 330 is connected to the third wiring layer 420.
  • the line layer 420 is electrically connected, so that the connection method between the second end of the second conductive member 330 and the external circuit structure is more flexible.
  • the package structure may optionally further include a third conductive member 510, which may be disposed on a side of the second dielectric layer 410 away from the first conductive member 130, and a first end of the third conductive member 510 may be electrically connected to the third wiring layer 420.
  • the third conductive member 510 may be a solder ball, a wire, or the like.
  • the third conductive member 510 By disposing the third conductive member 510 on the side of the second dielectric layer 410 away from the first conductive member 130 , the first end of the third conductive member 510 is electrically connected to the third wiring layer 420 , thereby facilitating electrical connection of the packaging structure with an external circuit structure through the third conductive member 510 .
  • the substrate 110 may be a silicon wafer, which can not only improve the strength of the package structure, but also solve the problem of thermal expansion mismatch between the resin molding compound and the chip when the resin molding compound is used as the substrate 110 in the related art.
  • the present application also discloses an electronic device, and the disclosed electronic device includes the packaging structure in the above embodiment.
  • the electronic device adopts the above packaging structure, it can be beneficial to the design of the electronic device to be light and thin.
  • the electronic device may be a mobile phone, a tablet, a game console, etc. There is no specific restriction on the electronic device here.
  • the present application further discloses a method for preparing a packaging structure, and the disclosed preparation method includes:
  • a groove 111 is formed on a substrate 110 .
  • the first surface of the first chip 120 is opposite to the second surface of the first chip 120 .
  • the components of the packaging structure in the method for preparing the packaging structure disclosed in the present application are the same or similar to the components in the above embodiments, and they can be referenced to each other, and will not be described in detail here.
  • the present application can perform a grinding process on the side of the first filling glue layer 140 facing away from the substrate 110, so that the first chip 120 can be flush with the surface where the notch of the groove 111 is located, thereby avoiding the formation of a step difference between the first chip 120 and the plane where the notch of the groove 111 is located.
  • the grinding process can also make the packaging structure thinner, and the thinner first chip 120 is beneficial to the heat dissipation of the first chip 120.
  • the disclosed method for preparing the packaging structure further includes:
  • Step A1 preparing a first dielectric layer 210 and a second wiring layer 220 on the substrate 110, wherein the first dielectric layer 210 covers the notch of the groove 111, the second wiring layer 220 is located in the first dielectric layer 210, and the other end of the first conductive member 130 is electrically connected to the second wiring layer 220.
  • Step A2 disposing the second chip 310 on a side of the first dielectric layer 210 away from the first chip 120 , and electrically connecting a first surface of the second chip 310 to the second wiring layer 220 .
  • Step A3 preparing a second conductive member 330 , wherein a first end of the second conductive member 330 is electrically connected to the second wiring layer 220 .
  • Step A4 prepare a second filling glue layer 320 on the first dielectric layer 210 , and the second filling glue layer 320 covers the second chip 310 and the second conductive member 330 .
  • Step A5 grinding the side of the second filling glue layer 320 away from the substrate 110, so that the second surface of the second chip 310, the second end of the second conductive member 330 and the second filling glue layer 320 are flush, and the second surface of the second chip 310 and the second end of the second conductive member 330 are exposed on the second filling glue layer 320.
  • the filling layer 320 is provided.
  • the first surface of the second chip 310 is opposite to the second surface of the second chip 310 .
  • the first dielectric layer 210 By arranging the first dielectric layer 210 on the substrate 110, and the first dielectric layer 210 covers the notch of the groove 111, the first dielectric layer 210 can further protect the first chip 120, so that the first chip 120 can be better packaged in the groove 111, and by arranging the second wiring layer 220 in the first dielectric layer 210, the second wiring layer 220 can be protected by the first dielectric layer 210, and after the other end of the first conductive member 130 is electrically connected to the second wiring layer 220, the other end of the first conductive member 130 can be electrically connected to other circuit structures through the second wiring layer 220 more flexibly.
  • the integration capability of the packaging structure is higher, and the second chip 310 is electrically connected to the second wiring layer 220, so that the electrical connection between the second chip 310 and the first chip 120 can be achieved, thereby realizing information interaction between multiple chips.
  • the second chip 310 is arranged on the side away from the first chip 120, which can avoid the problem of the first chip 120 and the second chip 310 being arranged on the same side, resulting in a longer overall length of the packaging structure.
  • the first surface of the second chip 310 is electrically connected to the second wiring layer 220
  • the second filling glue layer 320 is connected to the first dielectric layer 210, and covers the second chip 310 and the second conductive member 330
  • the first end of the second conductive member 330 is electrically connected to the second wiring layer 220
  • the second surface of the second chip 310 and the second end of the second conductive member 330 are exposed on the surface of the second filling glue layer 320, so that the second filling glue layer 320 can protect the second chip 310
  • the second end of the second conductive member 330 is exposed on the second filling glue layer 320, so that the second wiring layer 220 can be electrically connected to the external circuit.
  • the disclosed preparation method further includes:
  • Step B1 preparing a second dielectric layer 410 and a third wiring layer 420 on the second filling glue layer 320, wherein the second dielectric layer 410 covers the second surface of the second chip 310 and the second end of the second conductive member 330, the third wiring layer 420 is arranged in the second dielectric layer 410, and the second end of the second conductive member 330 is electrically connected to the third wiring layer 420.
  • the second dielectric layer 410 can cover the second surface of the second chip 310 and the second end of the second conductive member 330 to better package the second chip 310 and the second conductive member 330, and can also further protect the second chip 310 and the second conductive member 330.
  • the third wiring layer 420 is provided in the second dielectric layer 410, so that the second dielectric layer 410 can protect the third wiring layer 420, and the second end of the second conductive member 330 is electrically connected to the third wiring layer 420, so that the second end of the second conductive member 330 is more flexibly connected to the external circuit structure.

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
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  • Wire Bonding (AREA)

Abstract

本发明公开一种封装结构、封装结构的制备方法和电子设备，所公开的封装结构包括基体、第一芯片、第一导电件和第一填充胶层，基体开设有凹槽，凹槽的底壁设有第一布线层，第一芯片设于凹槽，第一芯片的第一表面与第一布线层电连接，第一导电件的一端与第一布线层电连接，第一填充胶层填充于凹槽内，且第一填充胶层与凹槽的槽口所在的表面平齐，第一导电件的另一端和第一芯片的第二表面均显露于第一填充胶层，且均与凹槽的槽口所在的表面平齐，第一芯片的第一表面和第一芯片的第二表面相背，第一芯片的第一表面为第一芯片的电连接面。

Description

封装结构、封装结构的制备方法和电子设备
相关申请的交叉引用
本申请要求在2022年10月27日提交中国专利局、申请号为202211323801.2、发明名称为“封装结构、封装结构的制备方法和电子设备”的中国专利申请的优先权，该中国专利申请的全部内容通过引用包含于此。
技术领域
本发明涉及半导体封装技术领域，尤其涉及一种封装结构、封装结构的制备方法和电子设备。
背景技术
随着电子技术的发展，半导体封装趋于向高密度、低功耗和小型化的方向发展。扇出性封装技术摆脱了常规芯片对范围的限制，可以在封装体内集成多个芯片。
在相关技术中，封装结构中采用芯片面朝上的方式贴装于基体的凹槽内，即芯片的电连接面朝向基体的凹槽的槽口方向，以便于实现芯片与其他电路结构的电连接。为了消除凹槽内的芯片与基体在凹槽的槽口处形成台阶差异，需要在形成凹槽的槽口的表面铺设一层较厚的绝缘介质层以消除差异。通过在凹槽的槽口的表面铺设一层较厚的绝缘介质层会导致封装结构存在整体厚度较大的问题。
发明内容
本发明公开一种封装结构、封装结构的制备方法和电子设备，以解决相关技术中封装结构整体厚度较大的问题。
为了解决上述技术问题，本发明是这样实现的：
第一方面，本申请公开一种封装结构，包括基体、第一芯片、第一导电 件和第一填充胶层，所述基体开设有凹槽，所述凹槽的底壁设有第一布线层，所述第一芯片设于所述凹槽，所述第一芯片的第一表面与所述第一布线层电连接，所述第一导电件的一端与所述第一布线层电连接，所述第一填充胶层填充于所述凹槽内，且所述第一填充胶层与所述凹槽的槽口所在的表面平齐，所述第一导电件的另一端和所述第一芯片的第二表面均显露于所述第一填充胶层，且均与所述凹槽的槽口所在的表面平齐，所述第一芯片的所述第一表面和所述第一芯片的所述第二表面相背，所述第一芯片的所述第一表面为所述第一芯片的电连接面。
第二方面，本申请公开一种电子设备，包括第一方面所述的封装结构。
第三方面，本申请公开一种封装结构的制备方法，包括：
在基体上开设凹槽；
在所述凹槽的底壁制备第一布线层；
将第一芯片设置于所述凹槽内，且所述第一芯片的第一表面与所述第一布线层电连接；
制备第一导电件，其中，所述第一导电件的一端与所述第一布线层电连接；
在所述凹槽内填充胶体以形成第一填充胶层，且所述第一填充胶层至少覆盖所述凹槽的槽口所在的表面；
对所述第一填充胶层的背离所述基体的一侧进行磨片处理，以使所述第一填充胶层与所述凹槽的槽口所在的表面平齐，且所述第一导电件的另一端和所述第一芯片的第二表面显露于所述第一填充胶层，其中，所述第一芯片的所述第一表面与所述第一芯片的所述第二表面相背。
本发明采用的技术方案能够达到以下技术效果：
本申请实施例公开的封装结构通过在基体上开设的凹槽的底壁设置第一布线层，使得第一芯片的第一表面可以与第一布线层电连接，第一导电件的一端与第一布线层电连接，进而在凹槽内填充第一填充胶层后，使得第一导 电件的另一端和第一芯片的第二表面显露于第一填充胶层，由于第一芯片的第二表面不是电连接面，从而可以通过对第一填充胶层的背离第一芯片的一侧进行磨片处理，以使第一芯片的第二表面、第一导电件的另一端和第一填充胶层平齐，避免第一芯片与凹槽的槽口形成台阶差异，进而通过磨片处理可以对封装结构进行减薄，从而可以解决相关技术中封装结构较厚的问题。
附图说明
图1为本发明实施例公开的封装结构的示意图；
图2为图1的局部示意图；
图3为在基体上开设凹槽的结构示意图；
图4为在凹槽的底壁制备第一布线层和第一导电件的示意图；
图5为第一芯片与第一布线层电连接的示意图；
图6为填充第一填充胶层后的示意图；
图7为对第一填充胶层磨片后的示意图；
图8为设置第一介质层和第二布线层后的示意图；
图9为第二芯片与第二布线层电连接的示意图；
图10为设置第二导电件后的示意图；
图11为设置第二填充胶层后的示意图；
图12为第二填充胶层磨片后的示意图；
图13为一种封装结构的制备方法的流程图。
附图标记说明：
110-基体、111-凹槽、
120-第一芯片、130-第一导电件、140-第一填充胶层、150-第一布线层、
210-第一介质层、220-第二布线层、
310-第二芯片、320-第二填充胶层、330-第二导电件、
410-第二介质层、420-第三布线层、
510-第三导电件。
具体实施方式
为使本发明的目的、技术方案和优点更加清楚，下面将结合本发明具体实施例及相应的附图对本发明技术方案进行清楚、完整地描述。显然，所描述的实施例仅是本发明的一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。
以下结合附图，详细说明本发明各个实施例公开的技术方案。
请参考图1至图12，本发明实施例公开一种封装结构，所公开的封装结构包括基体110、第一芯片120、第一导电件130和第一填充胶层140。
基体110开设有凹槽111，凹槽111的底壁设有第一布线层150。第一布线层150可以是一层，也可以是多层，这里对第一布线层150的层数不做具体的限制，可以根据实际情况进行布线。第一芯片120设于凹槽111，第一芯片120的第一表面与第一布线层150电连接，第一芯片120的第一表面为第一芯片120的电连接面。第一芯片120的第一表面和第一布线层150均可以设有微凸块，第一芯片120的第一表面的微凸块用于与第一布线层150的微凸块键合，以实现第一芯片120与第一布线层150的电连接。
第一导电件130的一端与第一布线层150电连接，第一填充胶层140填充于凹槽111内，且第一填充胶层140与凹槽111的槽口所在的表面平齐，以使第一填充胶层140包裹第一导电件130和第一芯片120的位于凹槽111内的部分以对第一芯片120进行封装。第一导电件130可以是铜柱，当然，第一导电件也可以是其他导电件。
第一导电件130的另一端和第一芯片120的第二表面均显露于第一填充胶层140，且均与凹槽111的槽口所在的表面平齐，第一导电件130的另一端用于与外部其他电路或构件电连接，以使第一芯片120依次通过第一芯片 120的第一表面、第一布线层150、第一导电件130与外部其他电路或构件电连接。
第一芯片120的第一表面和第一芯片120的第二表面相背，第一芯片120的第一表面为第一芯片120的电连接面。第一芯片120的第二表面可以用于封装第一芯片120内的电路结构，不构成第一芯片120的电路结构，第一芯片120的第二表面距离第一芯片120的电路结构可以具有一段距离，从而可以对第一芯片120的第二表面进行磨片处理。
在具体的工艺过程中，在基体110上刻蚀凹槽111，凹槽111的尺寸大于第一芯片120的尺寸，在第一凹槽111的底壁制备第一布线层150，并制备第一导电件130；之后将第一芯片120的第一表面与第一布线层150电连接，第一导电件130位于第一芯片120和凹槽111的侧壁之间；在第一芯片120与第一布线层150电连接后，向凹槽111内填充胶体以形成第一填充胶层140。在制备的过程中，第一芯片120与第一布线层150电连接后，第一芯片120的第二表面可以是高于凹槽111的槽口所在的表面，也可以是低于凹槽111的槽口所在的表面，第一填充胶层140至少覆盖凹槽111的槽口，第一填充胶层140也可以高于凹槽111的槽口所在的表面形成一层胶层。在形成第一填充胶层140后，对第一填充胶层140的背离基体110的一侧进行磨片处理，将第一导电件130的另一端显露于第一填充胶层140用于与其他电路结构电连接，同时，对第一填充胶层140的背离基体110的一层进行磨片处理可以使封装结构整体的厚度减小，且第一芯片120与凹槽111的槽口所在的表面平齐而不会存在台阶差异。
本申请实施例公开的封装结构通过在基体110上开设的凹槽111的底壁设置第一布线层150，使得第一芯片120的第一表面可以与第一布线层150电连接，第一导电件130的一端与第一布线层150电连接，进而在凹槽111内填充第一填充胶层140后，使得第一导电件130的另一端和第一芯片120的第二表面显露于第一填充胶层140，由于第一芯片120的第二表面不是电 连接面，从而可以通过对第一填充胶层140的背离第一芯片120的一侧进行磨片处理，以使第一芯片120的第二表面、第一导电件130的另一端和第一填充胶层140平齐，避免第一芯片120与凹槽111的槽口形成台阶差异，进而通过磨片处理可以对封装结构进行减薄，从而可以解决相关技术中封装结构较厚的问题，而且，可以对第一芯片120的第二表面进行磨片以使第一芯片120较薄，较薄的第一芯片120还有利于第一芯片120的散热。
一种可选的实施例，封装结构还可以包括第一介质层210和第二布线层220，第一介质层210可以设于基体110，且覆盖凹槽111的槽口，第二布线层220可以设于第一介质层210内，第一导电件130的另一端可以与第二布线层220电连接。
通过在基体110上设置第一介质层210，且第一介质层210覆盖凹槽111的槽口，使得第一介质层210可以对第一芯片120进一步进行防护，从而使得第一芯片120可以较好的封装于凹槽111内，通过将第二布线层220设置于第一介质层210内，使得第二布线层220可以通过第一介质层210进行防护，而且在第一导电件130的另一端与第二布线层220电连接后，使得第一导电件130的另一端通过第二布线层220可以与其它电路结构具有更灵活的电连接方式。
在一些实施例中，凹槽111、第一芯片120和第一导电件130均可以为多个。多个凹槽111可以间隔设置，多个第一芯片120可以一一对应地设于多个凹槽111，每个凹槽111内均可以设有围绕相应的第一芯片120的多个第一导电件130，多个第一导电件130的另一端通过第二布线层220电连接。具体的，多个第一芯片120可以是不同的芯片，当然，多个第一芯片120也可以是相同的芯片。
本申请实施例通过设置多个凹槽111、多个第一芯片120和多个第一导电件130，多个第一芯片120一一对应地设于多个凹槽111，每个凹槽111内均设有围绕相应的第一芯片120的多个第一导电件130，多个第一导电件130 的另一端通过第二布线层220电连接，使得多个第一芯片120可以通过第二布线层220实现电连接。
为了进一步提高封装结构的集成能力，可选的，封装结构还可以包括第二芯片310，第二芯片310可以设于第一介质层210的背离第一芯片120的一侧，第二芯片310可以与第二布线层220电连接。第二芯片310和第一芯片120可以通过第二布线层220电连接。
本申请实施例通过在第一介质层210的背离第一芯片120的一侧设置第二芯片310，使得封装结构的集成能力较高，而且第二芯片310与第二布线层220电连接，可以实现第二芯片310与第一芯片120之间的电连接，从而实现多个芯片之间的信息交互，将第二芯片310设置于背离第一芯片120的一侧，可以避免第一芯片120和第二芯片310同侧设置造成封装结构整体长度较长的问题。
进一步的，第二芯片310的第一表面可以与第二布线层220电连接，第二芯片310的第二表面可以为电连接面，封装结构还可以包括第二填充胶层320和第二导电件330，第二填充胶层320与第一介质层210连接，且包覆第二芯片310和第二导电件330，第二导电件330的第一端与第二布线层220电连接，第二芯片310的第二表面与第二导电件330的第二端显露于第二填充胶层320的表面，第二芯片310的第二表面与第二芯片310的第一表面相背，第二芯片310的第一表面为第二芯片310的电连接面，第二芯片310的第二表面与第二芯片310的电路结构具有一段距离，可以对第二芯片310的第二表面进行磨片处理以进行减薄，或在第二芯片310的第二表面进行其他工艺。
在具体的工艺过程中，在第二芯片310的第一表面与第二布线层220电连接，第二导电件330的第一端与第二布线层220电连接后，设置第二填充胶层320包覆第二芯片310和第二导电件330，第二填充胶层320可以将第二芯片310的第二表面及第二导电件330的第二端包覆后再进行膜片处理以 使第二芯片310的第二表面与第二导电件330的第二端显露于第二填充胶层320的表面，也可以是在填充第二填充胶层320时，第二芯片310的第二表面和第二导电件330的第二端直接露出于第二填充胶层320的表面；在设置完第二填充胶层320后，对第二填充胶层320的背离第一填充胶层140的一侧可以进行磨片处理，使得第二芯片310的第二表面与第二导电件330的第二端显露于第二填充胶层320的表面，可以保证第二芯片310的第二表面、第二导电件330的第二端均与第二填充胶层320平齐，而且还可以通过磨片使得第二填充胶层320的厚度较小，从而可以减小封装结构整体的厚度。
通过第二芯片310的第一表面与第二布线层220电连接，第二填充胶层320与第一介质层210连接，且包覆第二芯片310和第二导电件330，第二导电件330的第一端与第二布线层220电连接，第二芯片310的第二表面与第二导电件330的第二端显露于第二填充胶层320的表面，使得第二填充胶层320可以对于第二芯片310进行防护，而且第二导电件330的第二端显露于第二填充胶层320，从而可以实现第二布线层220与外部电路的电连接。
可选的，第二导电件330可以为铜核球。具体的，铜核球可以包括铜球、镀镍层和镀锡层。镀镍层和镀锡层可以包覆在铜球上形成一种复合式的铜核球。
可选的，封装结构还可以包括第二介质层410和第三布线层420，第二介质层410可以设于第二填充胶层320，且覆盖第二芯片310的第二表面和第二导电件330的第二端，第三布线层420可以设于第二介质层410内，第二导电件330的第二端与第三布线层420电连接。
通过设置第二介质层410和第三布线层420，使得第二介质层410可以覆盖于第二芯片310的第二表面和第二导电件330的第二端以对第二芯片310和第二导电件330进行较好封装，而且还可以对第二芯片310和第二导电件330进行防护。第三布线层420设于第二介质层410内，使得第二介质层410可以对第三布线层420进行防护，第二导电件330的第二端与第三布 线层420电连接，使得第二导电件330的第二端与外部电路结构的连接方式更灵活。
为了便于封装结构与外部电路结构的电连接，可选的，封装结构还可以包括第三导电件510，第三导电件510可以设于第二介质层410的背离第一导电件130的一侧，第三导电件510的第一端可以与第三布线层420电连接。具体的，第三导电件510可以是焊球、电线等。
通过在第二介质层410的背离第一导电件130的一侧设置第三导电件510，第三导电件510的第一端与第三布线层420电连接，从而便于封装结构通过第三导电件510与外部电路结构电连接。
具体的，基体110可以是硅片。通过将基体110设置为硅片，不仅可以提高封装结构的强度，还可以解决相关技术中采用树脂塑封料作为基体110存在的树脂塑封料与芯片之间热膨胀不匹配的问题。
本申请还公开一种电子设备，所公开的电子设备包括上述实施例中的封装结构。在电子设备采用上述封装结构的情况下，可以有利于电子设备轻薄化的设计。
电子设备可以是手机、平板、游戏机等，这里对电子设备不做具体的限制。
参考图13，本申请还公开一种封装结构的制备方法，所公开的制备方法包括：
S101，在基体110上开设凹槽111。
S102，在凹槽111的底壁制备第一布线层150。
S103，将第一芯片120设置于凹槽111内，且第一芯片120的第一表面与第一布线层150电连接。
S104，制备第一导电件130，其中，第一导电件130的一端与第一布线层150电连接。
S105，在凹槽111内填充胶体以形成第一填充胶层140，且第一填充胶 层140至少覆盖凹槽111的槽口。
S106，对第一填充胶层140的背离基体110的一侧进行磨片处理，以使第一填充胶层140与凹槽111的槽口所在的表面平齐，且第一导电件130的另一端和第一芯片120的第二表面显露于第一填充胶层140。
其中，第一芯片120的第一表面与第一芯片120的第二表面相背。
本申请公开的封装结构的制备方法中的封装结构的各部件与上述实施例中的各部件具有相同或相似之处，彼此可以相互参照，这里不再赘述。
本申请通过在填充完第一填充胶层140后，可以对第一填充胶层140的背离基体110的一侧进行磨片处理，可以使得第一芯片120与凹槽111的槽口所在的表面平齐，从而避免第一芯片120与凹槽111的槽口所在的平面形成台阶差异，而且磨片处理还可以使封装结构减薄，而且较薄的第一芯片120有利于第一芯片120的散热。
可选的，在对第一填充胶层140的背离基体110的一侧进行磨片处理后，所公开的封装结构的制备方法还包括：
步骤A1，在基体110上制备第一介质层210和第二布线层220，其中，第一介质层210覆盖凹槽111的槽口，第二布线层220位于第一介质层210内，第一导电件130的另一端与第二布线层220电连接。
步骤A2，将第二芯片310设置于第一介质层210的背离第一芯片120的一侧，且第二芯片310的第一表面与第二布线层220电连接。
步骤A3，制备第二导电件330，其中，第二导电件330的第一端与第二布线层220电连接。
步骤A4，在第一介质层210上制备第二填充胶层320，第二填充胶层320覆盖第二芯片310和第二导电件330。
步骤A5，对第二填充胶层320的背离基体110的一侧进行磨片处理，以使第二芯片310的第二表面、第二导电件330的第二端和第二填充胶层320平齐，且第二芯片310的第二表面和第二导电件330的第二端显露于第二填 充胶层320。
其中，第二芯片310的第一表面与第二芯片310的第二表面相背。
本申请实施例公开的封装结构的各部件与上述实施例中的各部件具有相同或相似之处，彼此可以相互参照，这里不在赘述。
通过在基体110上设置第一介质层210，且第一介质层210覆盖凹槽111的槽口，使得第一介质层210可以对第一芯片120进一步进行防护，从而使得第一芯片120可以较好的封装于凹槽111内，通过将第二布线层220设置于第一介质层210内，使得第二布线层220可以通过第一介质层210进行防护，而且在第一导电件130的另一端与第二布线层220电连接后，使得第一导电件130的另一端通过第二布线层220可以与其它电路结构的电连接方式更灵活。
通过在第一介质层210的背离第一芯片120的一侧设置第二芯片310，使得封装结构的集成能力较高，而且第二芯片310与第二布线层220电连接，可以实现第二芯片310与第一芯片120之间的电连接，从而实现多个芯片之间的信息交互，将第二芯片310设置于背离第一芯片120的一侧，可以避免第一芯片120和第二芯片310同侧设置造成封装结构整体长度较长的问题。通过第二芯片310的第一表面与第二布线层220电连接，第二填充胶层320与第一介质层210连接，且包覆第二芯片310和第二导电件330，第二导电件330的第一端与第二布线层220电连接，第二芯片310的第二表面与第二导电件330的第二端显露于第二填充胶层320的表面，使得第二填充胶层320可以对于第二芯片310进行防护，而且第二导电件330的第二端显露于第二填充胶层320，从而可以实现第二布线层220可以与外部电路电连接。
可选的，在对第二填充胶层320的背离基体110的一侧进行磨片处理，以使第二芯片310的第二表面、第二导电件330的第二端和第二填充胶层320平齐，且第二芯片310的第二表面和第二导电件330的第二端显露于第二填充胶层320之后，所公开的制备方法还包括：
步骤B1，在所述第二填充胶层320上制备第二介质层410和第三布线层420，其中，第二介质层410覆盖第二芯片310的第二表面和第二导电件330的第二端，第三布线层420设于第二介质层410内，第二导电件330的第二端与第三布线层420电连接。
通过设置第二介质层410和第三布线层420，使得第二介质层410可以覆盖于第二芯片310的第二表面和第二导电件330的第二端以对第二芯片310和第二导电件330进行较好封装，而且还可以对第二芯片310和第二导电件330进行进一步的防护。第三布线层420设于第二介质层410内，使得第二介质层410可以对第三布线层420进行防护，第二导电件330的第二端与第三布线层420电连接，使得第二导电件330的第二端与外部电路结构的连接更灵活。
本发明上文实施例中重点描述的是各个实施例之间的不同，各个实施例之间不同的优化特征只要不矛盾，均可以组合形成更优的实施例，考虑到行文简洁，在此则不再赘述。
上面结合附图对本发明的实施例进行了描述，但是本发明并不局限于上述的具体实施方式，上述的具体实施方式仅仅是示意性的，而不是限制性的，本领域的普通技术人员在本发明的启示下，在不脱离本发明宗旨和权利要求所保护的范围情况下，还可做出很多形式，均属于本发明的保护之内。

Claims (10)

  1. 一种封装结构，包括基体(110)、第一芯片(120)、第一导电件(130)和第一填充胶层(140)，其中：
    所述基体(110)开设有凹槽(111)，所述凹槽(111)的底壁设有第一布线层(150)，所述第一芯片(120)设于所述凹槽(111)，所述第一芯片(120)的第一表面与所述第一布线层(150)电连接，所述第一导电件(130)的一端与所述第一布线层(150)电连接，所述第一填充胶层(140)填充于所述凹槽(111)内，且所述第一填充胶层(140)与所述凹槽(111)的槽口所在的表面平齐；
    所述第一导电件(130)的另一端和所述第一芯片(120)的第二表面均显露于所述第一填充胶层(140)，且均与所述凹槽(111)的槽口所在的表面平齐，所述第一芯片(120)的所述第一表面和所述第一芯片(120)的所述第二表面相背，所述第一芯片(120)的所述第一表面为所述第一芯片(120)的电连接面。
  2. 根据权利要求1所述的封装结构，其中，所述封装结构还包括第一介质层(210)和第二布线层(220)，所述第一介质层(210)设于所述基体(110)，且覆盖所述凹槽(111)的槽口，所述第二布线层(220)设于所述第一介质层(210)内，所述第一导电件(130)的另一端与所述第二布线层(220)电连接。
  3. 根据权利要求2所述的封装结构，其中，所述凹槽(111)、所述第一芯片(120)和所述第一导电件(130)均为多个，多个所述凹槽(111)间隔设置，多个所述第一芯片(120)一一对应地设于多个所述凹槽(111)，每个所述凹槽(111)内均设有围绕相应的所述第一芯片(120)的多个所述第一导电件(130)，多个所述第一导电件(130)的另一端通过所述第二布线层(220)电连接。
  4. 根据权利要求2所述的封装结构，其中，所述封装结构还包括第二芯 片(310)，所述第二芯片(310)设于所述第一介质层(210)的背离所述第一芯片(120)的一侧，所述第二芯片(310)与所述第二布线层(220)电连接。
  5. 根据权利要求4所述的封装结构，其中，所述第二芯片(310)的第一表面与所述第二布线层(220)电连接，所述封装结构还包括第二填充胶层(320)和第二导电件(330)，所述第二填充胶层(320)与所述第一介质层(210)连接，且包覆所述第二芯片(310)和所述第二导电件(330)，所述第二导电件(330)的第一端与所述第二布线层(220)电连接，所述第二芯片(310)的第二表面与所述第二导电件(330)的第二端显露于所述第二填充胶层(320)的表面，所述第二芯片(310)的所述第二表面与所述第二芯片(310)的所述第一表面相背，所述第二芯片(310)的所述第一表面为所述第二芯片(310)的电连接面。
  6. 根据权利要求5所述的封装结构，其中，所述封装结构还包括第二介质层(410)和第三布线层(420)，所述第二介质层(410)设于所述第二填充胶层(320)，且覆盖所述第二芯片(310)的所述第二表面和所述第二导电件(330)的第二端，所述第三布线层(420)设于所述第二介质层(410)内，所述第二导电件(330)的第二端与所述第三布线层(420)电连接。
  7. 根据权利要求6所述的封装结构，其中，所述封装结构还包括第三导电件(510)，所述第三导电件(510)设于所述第二介质层(410)的背离所述第一导电件(130)的一侧，所述第三导电件(510)的第一端与所述第三布线层(420)电连接。
  8. 一种电子设备，包括权利要求1至7任一项所述的封装结构。
  9. 一种封装结构的制备方法，包括：
    在基体(110)上开设凹槽(111)；
    在所述凹槽(111)的底壁制备第一布线层(150)；
    将第一芯片(120)设置于所述凹槽(111)内，且所述第一芯片(120) 的第一表面与所述第一布线层(150)电连接；
    制备第一导电件(130)，其中，所述第一导电件(130)的一端与所述第一布线层(150)电连接；
    在所述凹槽(111)内填充胶体以形成第一填充胶层(140)，且所述第一填充胶层(140)至少覆盖所述凹槽(111)的槽口；
    对所述第一填充胶层(140)的背离所述基体(110)的一侧进行磨片处理，以使所述第一填充胶层(140)与所述凹槽(111)的槽口所在的表面平齐，且所述第一导电件(130)的另一端和所述第一芯片(120)的第二表面显露于所述第一填充胶层(140)，其中，所述第一芯片(120)的所述第一表面与所述第一芯片(120)的所述第二表面相背。
  10. 根据权利要求9所述的封装结构的制备方法，其中，
    在所述对所述第一填充胶层(140)的背离所述基体(110)的一侧进行磨片处理后，所述制备方法还包括：
    在所述基体(110)上制备第一介质层(210)和第二布线层(220)，其中，所述第一介质层(210)覆盖所述凹槽(111)的槽口，所述第二布线层(220)位于所述第一介质层(210)内，所述第一导电件(130)的另一端与所述第二布线层(220)电连接；
    将第二芯片(310)设置于所述第一介质层(210)的背离所述第一芯片(120)的一侧，且所述第二芯片(310)的第一表面与所述第二布线层(220)电连接；
    制备第二导电件(330)，其中，所述第二导电件(330)的第一端与所述第二布线层(220)电连接；
    在所述第一介质层(210)上制备第二填充胶层(320)，所述第二填充胶层(320)覆盖所述第二芯片(310)和所述第二导电件(330)；
    对所述第二填充胶层(320)的背离所述基体(110)的一侧进行磨片处理，以使所述第二芯片(310)的第二表面、所述第二导电件(330)的第二 端和所述第二填充胶层(320)平齐，且所述第二芯片(310)的所述第二表面和所述第二导电件(330)的第二端显露于所述第二填充胶层(320)，所述第二芯片(310)的所述第一表面与所述第二芯片(310)的所述第二表面相背。
PCT/CN2023/125922 2022-10-27 2023-10-23 封装结构、封装结构的制备方法和电子设备 WO2024088211A1 (zh)

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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104600039A (zh) * 2014-12-26 2015-05-06 南通富士通微电子股份有限公司 双面互联扇出工艺
CN110335852A (zh) * 2019-07-18 2019-10-15 上海先方半导体有限公司 一种扇出封装结构及封装方法
CN111613585A (zh) * 2020-05-28 2020-09-01 华进半导体封装先导技术研发中心有限公司 芯片封装结构及方法
CN113257778A (zh) * 2021-07-06 2021-08-13 江苏长晶科技有限公司 一种3d堆叠且背部导出的扇出型封装结构及其制造方法
CN115513168A (zh) * 2022-10-27 2022-12-23 维沃移动通信有限公司 封装结构、封装结构的制备方法和电子设备

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104600039A (zh) * 2014-12-26 2015-05-06 南通富士通微电子股份有限公司 双面互联扇出工艺
CN110335852A (zh) * 2019-07-18 2019-10-15 上海先方半导体有限公司 一种扇出封装结构及封装方法
CN111613585A (zh) * 2020-05-28 2020-09-01 华进半导体封装先导技术研发中心有限公司 芯片封装结构及方法
CN113257778A (zh) * 2021-07-06 2021-08-13 江苏长晶科技有限公司 一种3d堆叠且背部导出的扇出型封装结构及其制造方法
CN115513168A (zh) * 2022-10-27 2022-12-23 维沃移动通信有限公司 封装结构、封装结构的制备方法和电子设备

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