CN1295339A - 具有内在铜离子迁移势垒的低介电常数的介电材料 - Google Patents
具有内在铜离子迁移势垒的低介电常数的介电材料 Download PDFInfo
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Abstract
提供了一种用来防止含有铜区域的半导体结构中的铜离子迁移的层间介质。本发明的层间介质包含介电常数为3.0或更小的介电材料以及能够高度键合铜离子又可溶解在介电材料中的添加剂。低k介质中添加剂的存在,使得能够免去诸如SiO2或Si3N4之类的常规无机势垒材料。
Description
本发明涉及到集成电路(IC),确切地说是涉及到能够降低或消除IC中的铜(Cu)离子迁移的层间介质。本发明的层间介质包含被修正成包括具有高的Cu离子亲和力又可溶解在介电母体中的添加剂的低介电常数介电材料(k为3.0或更小)。
在采用铜(Cu)线和有机低k介质作为层间介质的现今的IC芯片设计中,Cu离子迁移势垒通常由诸如氮化硅或二氧化硅之类的高介电常数(k大于3.0)无机介质制成。通常位于层间介质与Cu线之间的这些无机介质,被用来降低或消除电偏压下的Cu离子迁移。在IC芯片长时间工作的典型工作条件下,能够出现电偏压下的铜离子迁移。铜离子迁移引起的电路短路决定了芯片的使用寿命。目前,铜离子迁移势垒具有与之相关的高的介电常数。通常,现有技术的铜离子迁移势垒的介电常数大于3.0,最好是7.0或更大。使用这样高的介电常数的铜离子迁移势垒,对于当前这一代的IC芯片是不实际的;其使用增大了IC芯片的总的介电常数,亦即离子迁移势垒层的介电常数加上层间介质(ILD)的介电常数乘以它们的各个厚度。ILD的介电常数越高,芯片的性能就越低。
如上所述,现有技术的铜离子迁移势垒被结合低k ILD使用。制造分立的介电势垒层不仅增大了总的介电常数,损害了芯片性能,而且增加了额外的工艺步骤,增加了复杂性和芯片制造成本。
迄今尚未实现仅仅由低k ILD作为铜离子迁移势垒的成功使用,因为这种材料容易使铜离子迁移。尽管有这一问题,但低k介质由于其使用不明显增大整个IC芯片的介电常数而极具优点。因此,在降低或消除含有铜布线的IC芯片中的铜离子迁移方面,有必要开发能够用作层间介质和铜离子迁移势垒二者的新的低k介质。
本发明的目的是提供一种能够用作层间介质又能够降低和/或消除含有铜布线的IC芯片中的铜离子迁移的低k介电材料。
本发明的另一目的是提供一种提高高速IC芯片的寿命的低k介电材料。
本发明的又一目的是提供一种容易制造又不增加IC制造中的额外工艺步骤和成本的低k介电材料(用作层间介质和铜离子迁移势垒二者)。
本发明的再一目的是提供铜离子迁移已经被明显地降低或消除了的IC芯片。
借助于使用其中包括先天地防止铜离子在其中迁移的变性剂的低k介电材料,能够达到本发明的这些和其它的目的和优点。用这种介电材料作为层间介质,免除了对使用分立的无机势垒层来防止铜离子迁移的需要。无机铜离子迁移势垒层的免除,减少了工艺步骤和IC加工成本,并且避免了使用会提高IC芯片总介电常数的高介电材料。具体地说,本发明的一种情况涉及到包含介电常数为3.0或更小的一种新的层间介质,所述介电材料包括具有键合(或络合)铜离子的高亲和力又可溶解在所述介电材料中的添加剂。此添加剂在介电材料中的存在,使本发明的层间介质能够被用作防止铜离子迁移的势垒层而不明显地提高ILD的介电常数。
本发明的另一情况涉及到其中包括上述层间介质的半导体结构,确切地说是IC芯片。具体地说,本发明提供了一种IC结构,它包含:衬底、制作在所述衬底上的本发明的层间介质、制作在所述层间介质上或所述层间介质中的铜区域、以及制作在所述铜区域上的钝化层。最终的IC芯片互连结构可能包含许多层间介质层以及信号或参考平面图形和铜通孔。
本发明的进一步目的是提供一种制作其中包含本发明的层间介质的IC结构的方法。根据本发明的这一情况,此方法包含:在衬底表面上制作本发明的层间介质;在所述层间介质上或所述层间介质中制作铜区域;以及在所述铜区域上制作钝化层。
结合分立的无机离子迁移势垒层使用本发明的层间介质,也在本发明的范围内。在本发明的这一可选实施例中,可以明显地减小无机势垒层的厚度,致使结构的总介电常数不比层间介质的介电常数明显增大。虽然分立的无机铜离子迁移势垒层的使用不是必须的,但可以用来提供对铜离子迁移的额外防止。
图1a-1b是本发明的半导体结构的剖面图,其中层间介质12被夹在衬底10与铜区域14之间。在图1a中,铜被制作在层间介质上;而在图1b中,铜被制作在层间介质之中。
图2是图1a结构的剖面图,它包括可选的无机势垒层16和可选的钝化层18。
图3剖面图示出了在测量Cu和Al迁移过程中用于本发明的电容器结构。
图4a-4b是图3所述结构的锯齿电压扫描(TVS)曲线图,4a中的金属是Cu,而4b中的金属是Al。示出了未改进的层间介质(比较例)和改进过的介质(本发明)二者。
图5是未改进的层间介质和根据本发明的改进过的层间介质的电容(C)对电压(V)曲线。
现参照本申请的附图来更详细地描述本发明,本发明提供了一种其中具有用于键合铜离子的添加剂的新的层间介质。要指出的是,在这些附图中,相同的参考号被用来表示相同的和/或相应的元件。
首先参照图1a-1b,示出了其中能够包含本发明的层间介质的基本半导体结构。具体地说,图1a-1b的半导体结构包含衬底10、制作在衬底10上的本发明的层间介质12、以及制作在所述本发明的层间介质上或所述本发明的层间介质之中的铜区域14。
衬底10可以是半导体芯片、晶片或其上能够制作铜布线层的互连结构。衬底可以由诸如Si、Ge、GaAs、InAs、InP或其它Ⅲ/Ⅴ族化合物之类的半导体材料组成,或包含这种半导体材料。衬底中可以包含有源器件区、布线区、隔离区等。为了清晰起见,在附图中未示出这些区域,但认为包括在衬底10中。
将层间介质12涂敷到衬底10的至少一个表面。用标准的淀积技术将层间介质12涂敷到衬底10的一个表面,这些淀积技术包括:化学汽相淀积、溅射、等离子体辅助化学汽相淀积、旋涂、以及其它类似的淀积工艺。对于本发明来说,并不苛求层间介质的厚度,但通常是涂敷到厚度约为0.1-1.0微米。
层间介质12与现有技术层间介质的差别在于,它包含其数量能够键合铜离子又仍然使添加剂能够溶解在介质母体中的添加剂。具体地说,层间介质12包含低介电常数介质和添加剂。此处用术语“低介电常数”来表示介电常数即k值为3.0或更小,最好是小于2.6的介质。
可以用于本发明的适当的低k介质,包括k值在上述范围内的任何一种常规有机介电材料。一些能够用于本发明的有机介电材料的示例性例子包括但不局限于:聚酰亚胺、聚酰胺、金刚石、类金刚石碳、含硅的聚合物、聚芳基醚(热凝的或非热凝的)、paralyene聚合物、以及介电常数为3.0或更小的其它类似有机介质。
结合低k介电材料使用的添加剂必须满足下面二个条件:(ⅰ)必须能够与铜离子形成强键,亦即,必须对铜离子具有高的亲和力,从而与铜离子形成强络合物;以及(ⅱ)必须可溶解在低k介电材料中,从而基本上均匀地分布在整个介质母体中。可以结合低k介质使用的示例性添加剂包括:巯基化合物、硫化合物、硫醚化合物、氰化合物、多齿配位体、聚合物、以及其它对铜具有强键合亲和力的类似的添加剂。要指出的是,术语“化合物”包括上述各个添加剂的衍生物。用于本发明的最佳添加剂是酞菁化合物。
在用能够提供添加剂被均匀地分布在低k介质母体中的预先混合的层间介质组分的常规溶液化学方法淀积添加剂之前,添加剂被加入到低k介质。具体地说,借助于将添加剂溶解在介质或介质产物母体组成的溶液中,得到预先混合。也可以使用获得上述预先混合的其它可能的方法。
要指出的是,用于本发明的添加剂的数量应该足以满足上述的条件(ⅰ)-(ⅱ)。亦即,添加剂的数量必须提供足够的铜离子键合,同时仍然可溶解在介质母体中。若使用的添加剂的数量不超过10-8克分子,则可以达到这些条件。添加剂的数量最好使低k介电材料的整个母体中的添加剂为大约10-6-10-8克分子。还要指出的是,用于本发明的添加剂的数量基本上不提高低k材料的介电常数。
然后,如图1a所示,在层间介质上制作铜区域14,或如图1b所示,在层间介质之中制作铜区域14。借助于在其上淀积铜层的方法,可以如图1a所示被图形化或不被图形化的铜区域,被制作在层间介质的表面上。利用能够在层间介质的表面上形成铜层的常规淀积工艺来进行铜淀积。能够用于铜层制作的适当的淀积工艺的例子包括:化学汽相淀积、等离子体辅助化学汽相淀积、溅射、蒸发、电镀、以及其它类似的淀积工艺。铜区域的总厚度对于本发明是不苛求的,但铜区域14的厚度通常约为0.1-2微米。若希望图形化的铜区域,则可以利用常规的光刻、反应离子刻蚀和其它的腐蚀工艺来获得图形化。
图1b示出了本发明的又一个实施例,其中的铜区域14制作在层间介质12中。利用能够首先在层间介质中制作沟槽(或通孔)、用铜填充此沟槽、以及如有必要则对不是淀积在沟槽中的铜进行抛光的常规工艺,来制作此结构。可以用常规的光刻和腐蚀(例如反应离子刻蚀)来制作沟槽和通孔,然后利用上述的铜淀积工艺中的任何一种工艺,用铜填充此沟槽。可以用化学机械抛光或研磨方法来进行抛光。
图2示出了本发明的另外一些实施例,其中采用了可选的无机势垒层16和钝化层18。虽然示出的是采用二者的情况,但仅仅采用钝化层和无机势垒层中的一个的情况也在本发明的范围内。还有可能使用这些元件组成的多层,或结合图1b所示的结构使用这些元件组成的多层。
在采用诸如SiO2或Si3N4之类的无机势垒层(16)的情况下,通常用诸如化学汽相淀积之类的常规淀积工艺,在层间介质12与铜区域14之间制作无机势垒层(16)。无机势垒层16可以被图形化或不被图形化。
本发明的层间介质和无机势垒层二者的存在,提供了对铜离子迁移的双重防止。要指出的是,由于本发明的层间介质中固有地含有对铜具有强的键合亲和力的添加剂,故无机势垒层的厚度能够从700nm(现有技术的代表性数值)减小到350nm或更小。在厚度为350nm或更小时,结构的总介电常数丝毫不受影响。
当使用钝化层18时,它被制作来隔离铜区域14;因此,可以制作在铜区域14的顶部和/或其任何暴露的侧壁上。能够用于本发明的适当的钝化材料包括:聚酰亚胺、多晶硅、SiO2、Si3N4、诸如Ti、Ta、TaN和WN之类的金属势垒、以及能够使铜与其上可能制作的覆盖层彼此绝缘的其它类似的材料。钝化层的厚度对本发明来说是不苛求的,但这种层的厚度通常为大约200埃到大约1微米。
下面的例子被用来说明本发明并演示由于使用本发明而能够得到的一些优点。
例子
在此例子中,对含有本发明的层间介质的结构,亦即含有酞菁衍生物即2,9,16,23-四-叔丁基-29H,31H酞菁作为添加剂的热凝聚芳基醚的结构,进行了下列研究,并对含有常规的未被改进的层间低k介质(没有添加剂的热凝聚芳基醚)的结构进行了比较。
偏压热应力(BTS)测试
BTS测试被用作上述层间介质的退化的加速可靠性测试方法。
为了测量通过上述介电材料的金属离子迁移,使用了图3所示的电容器结构。具体地说,图3所示的结构包含底部W电极50、Si衬底52、层间介质54、Cu或Al电极56、以及Si3N4层58。
在测试中,大约2MV/cm的电压被施加在图3的结构上。若击穿电压低于2MV/cm,则使用更低的电压。在施加电压之后,此结构被加热到大约300℃的温度,停留大约10分钟。
栅上的偏压可以是正的或负的。为了驱使铜离子进入并通过层间介质,偏压是正的。反偏压被用来检查此过程是否可逆。样品在冷却过程中通常保持在偏压下。
在BTS之后,可以用下列电学测试方法来评估离子迁移引起的样品中可能已经发生的变化。
电容-电压(CV)测试
CV测试也称为CV偏移测试,提供了一种观察绝缘体中离子输运结果的快速灵敏方法。此测试在室温下进行。
在CV测试中,器件的ac电容被测量成室温下dc偏压改变的函数。这些测试条件通常不干扰BTS过程中样品达到的状态。将记录到的电容-电压(CV)曲线与BTS之前得到的曲线进行比较。平带电压曲线中的负的偏移表示多半已经发生了阳离子迁移。
离子之类的可移动电荷可存在于绝缘体中。在BTS之后,这些电荷能够到达Si/绝缘体界面。这些额外的电荷是外加场电压的附加物,而且是CV曲线沿电压轴向更负的电压偏移的根源。
C-V偏移起源于绝缘体中离子空间电荷分布的变化。亦即,所有的可移动空间电荷导致C-V偏移。于是,绝缘体中明显数量的原有电荷(杂质)的存在就能够掩没从电极注入离子到绝缘体中所引起的迁移。
测得的平带电压偏移可以被用作漂移进入介质的电荷的数量的量度。这些电荷可以是绝缘体不稳定性和/或碱金属迁移的结果。利用下面公式有可能计算到达热氧化物/Si界面的离子浓度:
[ion+]=-(Cox/q)△VFB
其中Cox是单位面积的介质叠层电容,而q是电荷。用作为时间和温度的函数的下述△VFB,可以获得介质中的离子漂移速率和对应的激活能。由于介质中大量离子的存在改变了受力过程中介质中的电场而必须忽略大的△VFB值(大的定义是任意的),故在稍后的过程中有一些任意性。在介质中存在钠之类的杂质的情况下,曾经试图忽略初始的更迅速的VFB变化,希望随后的依赖时间的平带电压偏移仅仅表示从电极注入的离子。虽然在没有势垒层的结构中,只要从电极注入明显数量的离子,这一过程可能是可接受的,但对于具有势垒层的结构,这似乎太不准确了。能够不任意地分开各个离子的过程显然是更好的。
若根据在给定的提高的温度下暴露于偏压各种时间长度或在不同的温度下暴露固定的时间的样品的C-V偏移,则能够研究离子迁移过程的动力学。例如,平带电压偏移相对于受力时间绘出。从这些曲线的斜率能够求出铜离子的漂移速率(单位为离子/cm2sec)。
在某些应力情况下(例如改变应力或界面缺陷的生长),CV曲线的形状在BTS之后能够改变。此时,即使没有发生离子迁移,也可能出现明显的CV偏移。由于介质中的损伤的退火,也能够出现CV偏移。如果在测量第一CV平带曲线之前,样品被退火而没有偏压,则可以排除后者。在所有的上述情况下,都在BTS前后的曲线的中间电容处测量电压偏移△V。为了避免这种误解,报道密度状态是有用的。这一数值给出了CV曲线的定性量度。此时,可以监视CV由于受力过程中界面态产生而引起的拉长。从这种观察中能够确保给定的观察到的CV偏移与电荷迁移有关,而不是上述的其它现象。
锯齿电压扫描(TVS)
这一测试是新近才发展的,目的是避免CV测试的某些缺陷。虽然CV测试是在室温下进行,但TVS在偏压温度,亦即离子可移动的温度下进行。于是,在外加dc电压下,离子的运动产生电流,在电压由正改变到负时,此电流改变。运动的离子依赖于外加电压。例如,随着电压下降,碱性离子引起的电流首先被观察到。这随之以铜离子,这随之以在这些条件下被激活的氢离子运动;这是在先前受力过程中发生的顶部上的二次质子运动。
若BTS测试先于TVS测试,则固有的正电荷(杂质)的很大一部分已经被推到绝缘体/硅界面,致使观察到的电流由测试时从电极注入到绝缘体的电容器的位移电流顶部的离子造成。由铜离子迁移造成的这一电流本身表现为氢离子运动引起的电流上的肩部。
结果
图4a示出了对照介质与具有铜电极的结构的含有可溶解的酞菁衍生物添加剂的介质之间的比较。当电压从正改变到负时,此对照显示一个大的尖锐的钠离子峰,随之以一个大的宽的铜离子峰。在比较中,被修正的膜在较低的电压下表现降低了的钠峰和降低了很多的铜峰。从铜峰下的面积,可以计算出在相同的应力条件下,对照显示的铜扩散率比被修正的PAE高4倍(对照为1.2×1012,修正的膜为3×1011)。对铝电极测得的同一个TVS曲线(图4b)再次示出了钠离子向较低电压方向的偏移,还表明了钠的扩散率下降。此实验表明,图4a中-40V处的峰起源于铜离子迁移。修正的和对照的介质的C-V曲线(图5)表明被修正的膜更稳定,亦即,在烘焙过程中产生更少的电荷。但电容更大,可能是修正的膜的介电常数微量增大造成的。
虽然根据其最佳实施例已经特别地描述了本发明,但本技术领域熟练人员可以理解,可以作出形式和细节方面的上述和其它改变而不超越本发明的构思与范围。因此认为本发明不局限于所述的准确形式而是在所附权利要求的范围内。
Claims (32)
1.一种能够降低或消除铜离子迁移的层间介质,它包含介电常数为3.0或更小的介电材料以及添加剂,所述添加剂能够键合铜离子,可溶解在所述介电材料中并基本上均匀地分布在整个所述介电材料中。
2.权利要求1的层间介质,其中所述介电材料是有机介电材料。
3.权利要求2的层间介质,其中所述有机介质选自聚酰亚胺、聚酰胺、金刚石、类金刚石碳、含硅的聚合物、聚芳基醚和paralyene聚合物构成的组。
4.权利要求1的层间介质,其中所述添加剂选自巯基化合物、硫化合物、硫醚化合物、氰化合物、多齿配位体和聚合物构成的组。
5.权利要求4的层间介质,其中所述添加剂是酞菁化合物。
6.权利要求1的层间介质,其中所述添加剂的量为10-8克分子或更少。
7.权利要求6的层间介质,其中所述添加剂的量为大约10-6到大约10-8克分子。
8.一种半导体结构,它包含衬底、制作在所述衬底上的权利要求1的层间介质、以及与所述层间介质接触的铜区域。
9.权利要求8的半导体结构,还包含制作在所述铜区域上的钝化层。
10.权利要求8的半导体结构,其中所述铜区域制作在所述层间介质上或制作在形成于所述层间介质中的沟槽内。
11.权利要求8的半导体结构,其中所述介电材料是有机介电材料。
12.权利要求11的半导体结构,其中所述有机介质选自聚酰亚胺、聚酰胺、金刚石、类金刚石碳、含硅的聚合物、聚芳基醚和paralyene聚合物构成的组。
13.权利要求8的半导体结构,其中所述添加剂选自巯基化合物、硫化合物、硫醚化合物、氰化合物、多齿配位体和聚合物构成的组。
14.权利要求13的半导体结构,其中所述添加剂是酞菁化合物。
15.权利要求8的半导体结构,其中所述添加剂的量为10-8克分子或更少。
16.权利要求15的半导体结构,其中所述添加剂的量为大约10-6到大约10-8克分子。
17.权利要求8的半导体结构,其中所述层间介质的厚度约为0.1-1.0微米。
18.权利要求8的半导体结构,还包含制作在所述层间介质与所述铜区域之间的可选的无机势垒层。
19.权利要求18的半导体结构,其中所述可选的无机势垒层是SiO2或Si3N4。
20.权利要求18的半导体结构,其中所述可选的无机势垒层的厚度为大约200埃到大约1微米。
21.权利要求8的半导体结构,其中所述衬底是半导体芯片、晶片或互连结构。
22.权利要求8的半导体结构,其中所述衬底包含或含有选自Si、Ge、GaAs、InAs、InP和其它Ⅲ/Ⅴ族化合物的半导体材料。
23.权利要求8的半导体结构,其中所述铜区域被图形化或未被图形化。
24.一种制作半导体结构的方法。它包含:
在衬底表面上制作权利要求1的层间介质;以及
制作与所述层间介质接触的铜区域。
25.权利要求24的方法,还包含在所述铜区域上制作可选的钝化层。
26.权利要求24的方法,其中所述层间介质在被制作在所述衬底上之前,用溶液化学方法制作。
27.权利要求24的方法,其中所述介电材料是有机介电材料。
28.权利要求27的方法,其中所述有机介质选自聚酰亚胺、聚酰胺、金刚石、类金刚石碳、含硅的聚合物、聚芳基醚和paralyene聚合物构成的组。
29.权利要求1的方法,其中所述添加剂选自巯基化合物、硫化合物、硫醚化合物、氰化合物、多齿配位体和聚合物构成的组。
30.权利要求29的方法,其中所述添加剂是酞菁化合物。
31.权利要求24的方法,其中所述添加剂的量为10-8克分子或更少。
32.权利要求31的方法,其中所述添加剂的量为大约10-6到大约10-8克分子。
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US09/371,340 US6414377B1 (en) | 1999-08-10 | 1999-08-10 | Low k dielectric materials with inherent copper ion migration barrier |
US09/371,340 | 1999-08-10 |
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CN104502424A (zh) * | 2014-08-19 | 2015-04-08 | 北京大学 | 一种基于电解液-氧化层-半导体结构的铜离子检测方法 |
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KR100382738B1 (ko) * | 2001-04-09 | 2003-05-09 | 삼성전자주식회사 | 반도체 소자의 메탈 컨택 형성 방법 |
US20050163985A1 (en) * | 2003-10-22 | 2005-07-28 | Dorfman Benjamin F. | Synergetic SP-SP2-SP3 carbon materials and deposition methods thereof |
US7176119B2 (en) | 2004-09-20 | 2007-02-13 | International Business Machines Corporation | Method of fabricating copper damascene and dual damascene interconnect wiring |
JP4904482B2 (ja) * | 2005-01-18 | 2012-03-28 | 国立大学法人東北大学 | 半導体装置 |
KR100735482B1 (ko) | 2006-08-29 | 2007-07-03 | 동부일렉트로닉스 주식회사 | 반도체 소자 및 그 제조방법 |
US8407871B2 (en) | 2009-07-06 | 2013-04-02 | Delphi Technologies, Inc. | Method of manufacturing a shapeable short-resistant capacitor |
JP6020239B2 (ja) * | 2012-04-27 | 2016-11-02 | 東京エレクトロン株式会社 | 成膜方法及び成膜装置 |
US9484136B2 (en) * | 2012-09-04 | 2016-11-01 | Analog Devices Global | Magnetic core for use in an integrated circuit, an integrated circuit including such a magnetic core, a transformer and an inductor fabricated as part of an integrated circuit |
US11404197B2 (en) | 2017-06-09 | 2022-08-02 | Analog Devices Global Unlimited Company | Via for magnetic core of inductive component |
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JPS6373660A (ja) * | 1986-09-17 | 1988-04-04 | Fujitsu Ltd | 半導体装置 |
JP2817217B2 (ja) * | 1989-06-30 | 1998-10-30 | 日本電気株式会社 | 金属・半導体接合を有する半導体装置およびその製造方法 |
JP3061059B2 (ja) * | 1989-08-07 | 2000-07-10 | ジャパンゴアテックス株式会社 | Icパッケージ |
JP3401993B2 (ja) | 1995-05-26 | 2003-04-28 | ソニー株式会社 | 層間絶縁膜および層間絶縁膜の形成方法 |
JP3465411B2 (ja) * | 1995-05-30 | 2003-11-10 | ソニー株式会社 | 半導体装置の層間絶縁膜 |
US5760480A (en) * | 1995-09-20 | 1998-06-02 | Advanced Micro Devics, Inc. | Low RC interconnection |
JP4082626B2 (ja) * | 1996-11-19 | 2008-04-30 | 松下電器産業株式会社 | 層間絶縁膜形成用材料及び層間絶縁膜 |
KR20000020900A (ko) * | 1998-09-24 | 2000-04-15 | 정선종 | 자동 등록 기능을 갖는 댁내 통신 장치 및 그에 적용되는 등록방법 |
JP3916195B2 (ja) | 1999-02-15 | 2007-05-16 | 株式会社東芝 | 銅の拡散を抑制した構造の半導体装置とその製造方法、及び拡散した銅の検出方法 |
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CN104502424B (zh) * | 2014-08-19 | 2019-08-02 | 北京大学 | 一种基于电解液-氧化层-半导体结构的铜离子检测方法 |
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