JP5110490B2 - 層間絶縁膜および配線構造と、それらの製造方法 - Google Patents
層間絶縁膜および配線構造と、それらの製造方法 Download PDFInfo
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- JP5110490B2 JP5110490B2 JP2009528143A JP2009528143A JP5110490B2 JP 5110490 B2 JP5110490 B2 JP 5110490B2 JP 2009528143 A JP2009528143 A JP 2009528143A JP 2009528143 A JP2009528143 A JP 2009528143A JP 5110490 B2 JP5110490 B2 JP 5110490B2
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- film
- interlayer insulating
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- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
- H01L23/5329—Insulating materials
- H01L23/53295—Stacked insulating layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Description
2 第1の層間絶縁膜
3 第1の接着層
4 第2の層間絶縁膜
5 第2の接着層
6 硬質マスク
121 フルオロカーボン膜(CFx膜)
122 絶縁性塗布膜
141 フルオロカーボン膜
142 絶縁性塗布膜
7 ビアホール
7´、9´ バリアー層
8 電極
9 溝
10、20 多層配線構造
11 配線導体(Cu)
21 バリアーキャップ層
22 SiCOによって形成された層間絶縁膜
25 バリアー層
27 ビアホール
28 配線
29 溝
27´ バリアー層
28´ 配線導体
29´ バリアー層
30 プラズマ処理装置
31 絶縁体板
32 アンテナ
33 上段シャワープレート
34 プラズマ発生領域
35 下段シャワープレート
37 処理室
41 マイクロ波
43 ガス導入管
Claims (25)
- 下部電極または配線層と上部配線層との間に設けられた層間絶縁膜であって、比誘電率kが2.5以下である絶縁性塗布膜を少なくとも一部に含み、前記絶縁性塗布膜はその表面の平坦度がRaで1nm以下、ピーク・トウ・バレイ値で20nm以下であることを特徴とする層間絶縁膜。
- 下部電極または配線層と上部配線層との間に設けられた層間絶縁膜であって、主たる絶縁膜としてフルオロカーボン膜を含み、絶縁性塗布膜が前記フルオロカーボン膜の上に設けられ、前記フルオロカーボン膜の比誘電率kは、1.8〜2.2であることを特徴とする層間絶縁膜。
- 請求項2に記載の層間絶縁膜において、前記フルオロカーボン膜は、原子比でF/Cが0.8乃至1.1の範囲内でFおよびCを含有することを特徴とする層間絶縁膜。
- 請求項2又は3に記載の層間絶縁膜において、前記フルオロカーボン膜の厚さは、50〜500nmであることを特徴とする層間絶縁膜。
- 請求項2乃至4の内のいずれか一つに記載の層間絶縁膜において、前記絶縁性塗布膜の厚さは前記フルオロカーボン膜の厚さの1/10以下であることを特徴とする層間絶縁膜。
- 請求項2乃至4の内のいずれか一つに記載の層間絶縁膜において、前記絶縁性塗布膜の厚さは前記フルオロカーボン膜の厚さの1/5以下であることを特徴とする層間絶縁膜。
- 請求項2乃至4の内のいずれか一つに記載の層間絶縁膜において、前記絶縁性塗布膜の厚さは前記フルオロカーボン膜の厚さの1/3以下であることを特徴とする層間絶縁膜。
- 請求項2乃至7の内のいずれか一つに記載の層間絶縁膜において、前記フルオロカーボン膜は、Arガス、XeガスおよびKrガスの少なくとも一つを用いて発生させたプラズマ中でCおよびFを含む少なくとも一種のガスを用いてCVDによって形成されたものであることを特徴とする層間絶縁膜。
- 請求項1に記載の層間絶縁膜において、前記絶縁性塗布膜が主たる絶縁膜であることを特徴とする層間絶縁膜。
- 請求項2乃至8の内のいずれか一つに記載の層間絶縁膜において、前記絶縁性塗布膜の比誘電率kは、2.5以下であることを特徴とする層間絶縁膜。
- 請求項1乃至10の内のいずれか一つに記載の層間絶縁膜において、前記絶縁性塗布膜は、SiとCとOとを、原子比でO>Si>1/2Cとなるように含有していることを特徴とする層間絶縁膜。
- 請求項1乃至11の内のいずれか一つに記載の層間絶縁膜において、前記絶縁性塗布膜は金属有機化合物および金属無機化合物の少なくとも一方と溶媒とを含む液体状の塗布膜を乾燥、焼成して得た膜であることを特徴とする層間絶縁膜。
- 請求項1乃至11の内のいずれか一つに記載の層間絶縁膜において、前記絶縁性塗布膜は金属有機化合物および金属無機化合物の少なくとも一方と溶媒とを含む液体状の塗布膜を乾燥し600℃以下で焼成して得た膜であることを特徴とする層間絶縁膜。
- 請求項1乃至11の内のいずれか一つに記載の層間絶縁膜において、前記絶縁性塗布膜は金属有機化合物および金属無機化合物の少なくとも一方と溶媒とを含む液体状の塗布膜を乾燥し400℃以下で焼成して得た膜であることを特徴とする層間絶縁膜。
- 請求項1乃至14の内のいずれか一つに記載の層間絶縁膜において、前記絶縁性塗布膜はSiOの繰り返し単位が主骨格であり、かつ、その組成が一般式((CH3)nSiO2−n/2)x(SiO2)1−x (但し、n=1〜3、x≦1)で表される一種、又は二種以上の酸化物で構成される絶縁体膜であることを特徴とする層間絶縁膜。
- 請求項1乃至15の内のいずれか一つに記載の層間絶縁膜において、前記絶縁性塗布膜はその表面が窒化されてなる窒化表面層を有することを特徴とする層間絶縁膜。
- 請求項1乃至16の内のいずれか一つに記載の層間絶縁膜を備えた多層配線構造であって、前記層間絶縁膜にビア及び溝の内の少なくとも一方と、前記ビア及び溝の内の少なくとも一方に埋設された導体層と、前記導体層の周囲に設けられたバリアー層とを備えていることを特徴とする多層配線構造。
- 層間絶縁膜を有する多層配線構造において、前記層間絶縁膜は、一般式((CH3)nSiO2−n/2)x(SiO2)1−x (但し、n=1〜3、x≦1)であらわされる一種又は、二種以上の酸化物で構成される塗布膜から得られた絶縁性塗布膜を含み、前記絶縁性塗布膜はその表面の平坦度がRaで1nm以下、ピーク・トウ・バレイ値で20nm以下であることを特徴とする多層配線構造。
- 請求項18において、前記層間絶縁膜は、前記絶縁性塗布膜と、フロオロカーボン膜(CFx)とを有することを特徴とする多層配線構造。
- 請求項18において、前記層間絶縁膜は、前記絶縁性塗布膜によって形成されていることを特徴とする多層配線構造。
- 複数の層間絶縁膜を含む多層配線構造において、前記複数の層間絶縁膜のうちの少なくとも一層は一般式((CH3)nSiO2−n/2)x(SiO2)1−x (但し、n=1〜3、x≦1)であらわされる一種又は、二種以上の酸化物で構成される塗布膜から得られた絶縁性塗布膜を含み、前記絶縁性塗布膜はその表面の平坦度がRaで1nm以下、ピーク・トウ・バレイ値で20nm以下であることを特徴とする多層配線構造。
- 層間絶縁膜の製造方法において、一般式((CH3)nSiO2−n/2)x(SiO2)1−x (但し、n=1〜3、x≦1)であらわされる一種又は、二種以上の酸化物を含む液体状の材料を塗布し、当該塗布された膜を乾燥させることにより、比誘電率kが2.5以下で且つ、表面の平坦度がRaで1nm以下、ピーク・トウ・バレイ値で20nm以下である絶縁性塗布膜を含む層間絶縁膜を形成することを特徴とする層間絶縁膜の製造方法。
- 層間絶縁膜を含む多層配線構造を形成する製造方法において、前記層間絶縁膜を形成する工程は、一般式((CH3)nSiO2−n/2)x(SiO2)1−x (但し、n=1〜3、x≦1)であらわされる一種又は、二種以上の酸化物を含む液体状の材料を塗布し、当該塗布された膜を乾燥させることにより、比誘電率kが2.5以下で且つ、表面の平坦度がRaで1nm以下、ピーク・トウ・バレイ値で20nm以下である絶縁性塗布膜を含む前記層間絶縁膜を形成する工程を有することを特徴とする多層配線構造の製造方法。
- 層間絶縁膜を含む電子装置において、前記層間絶縁膜は一般式((CH3)nSiO2−n/2)x(SiO2)1−x (但し、n=1〜3、x≦1)であらわされる一種又は、二種以上の酸化物で構成され、比誘電率kが2.5以下で、且つ、表面の平坦度がRaで1nm以下、ピーク・トウ・バレイ値で20nm以下である絶縁性塗布膜から得られた絶縁体膜であることを特徴とする電子装置。
- 層間絶縁膜を含む電子装置の製造方法において、前記層間絶縁膜を形成する工程は、一般式((CH3)nSiO2−n/2)x(SiO2)1−x (但し、n=1〜3、x≦1)であらわされる一種又は、二種以上の酸化物を含む液体状の材料を塗布し、当該塗布された膜を乾燥させることにより、比誘電率kが2.5以下で、且つ、表面の平坦度がRaで1nm以下、ピーク・トウ・バレイ値で20nm以下である絶縁体塗布膜を含む前記層間絶縁膜を形成する工程を有することを特徴とする電子装置の製造方法。
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US10453751B2 (en) * | 2017-02-14 | 2019-10-22 | Globalfoundries Inc. | Tone inversion method and structure for selective contact via patterning |
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JP2001044191A (ja) * | 1999-07-27 | 2001-02-16 | Sony Corp | 積層絶縁膜とその製造方法および半導体装置とその製造方法 |
JP2002040651A (ja) * | 2000-07-25 | 2002-02-06 | Fujifilm Arch Co Ltd | ポジ型感光性樹脂組成物 |
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JP2005109452A (ja) * | 2003-09-12 | 2005-04-21 | Toshiba Corp | 半導体装置の製造方法 |
WO2006137384A1 (ja) * | 2005-06-20 | 2006-12-28 | Tohoku University | 層間絶縁膜および配線構造と、それらの製造方法 |
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US6768200B2 (en) * | 2000-10-25 | 2004-07-27 | International Business Machines Corporation | Ultralow dielectric constant material as an intralevel or interlevel dielectric in a semiconductor device |
JP2004095611A (ja) * | 2002-08-29 | 2004-03-25 | Fujitsu Ltd | 半導体装置およびその製造方法 |
US7704893B2 (en) * | 2003-08-15 | 2010-04-27 | Tokyo Eectron Limited | Semiconductor device, method for manufacturing semiconductor device and gas for plasma CVD |
JP4737552B2 (ja) * | 2004-07-22 | 2011-08-03 | 国立大学法人京都大学 | フルオロカーボン膜及びその形成方法 |
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JP2002353217A (ja) * | 1996-08-29 | 2002-12-06 | Matsushita Electric Ind Co Ltd | 半導体装置の製造方法 |
JP2001044191A (ja) * | 1999-07-27 | 2001-02-16 | Sony Corp | 積層絶縁膜とその製造方法および半導体装置とその製造方法 |
JP2002040651A (ja) * | 2000-07-25 | 2002-02-06 | Fujifilm Arch Co Ltd | ポジ型感光性樹脂組成物 |
JP2002222860A (ja) * | 2001-01-29 | 2002-08-09 | Sony Corp | 半導体装置の作成方法 |
JP2005109452A (ja) * | 2003-09-12 | 2005-04-21 | Toshiba Corp | 半導体装置の製造方法 |
WO2006137384A1 (ja) * | 2005-06-20 | 2006-12-28 | Tohoku University | 層間絶縁膜および配線構造と、それらの製造方法 |
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EP2184771A1 (en) | 2010-05-12 |
CN101779279A (zh) | 2010-07-14 |
TW200926297A (en) | 2009-06-16 |
JPWO2009022718A1 (ja) | 2010-11-18 |
WO2009022718A1 (ja) | 2009-02-19 |
US20110127075A1 (en) | 2011-06-02 |
KR20100044227A (ko) | 2010-04-29 |
EP2184771A4 (en) | 2010-10-20 |
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