CN100459052C - 形成具有特定尺寸的栅极侧壁间隔件之半导体装置的方法 - Google Patents

形成具有特定尺寸的栅极侧壁间隔件之半导体装置的方法 Download PDF

Info

Publication number
CN100459052C
CN100459052C CNB2005800392172A CN200580039217A CN100459052C CN 100459052 C CN100459052 C CN 100459052C CN B2005800392172 A CNB2005800392172 A CN B2005800392172A CN 200580039217 A CN200580039217 A CN 200580039217A CN 100459052 C CN100459052 C CN 100459052C
Authority
CN
China
Prior art keywords
gate electrode
sidewall
spacer
sidewall spacer
formation
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
CNB2005800392172A
Other languages
English (en)
Other versions
CN101073143A (zh
Inventor
M·C·克林
D·邦瑟
S·达克希那-穆尔蒂
A·野村
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
GlobalFoundries Inc
Original Assignee
Advanced Micro Devices Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Advanced Micro Devices Inc filed Critical Advanced Micro Devices Inc
Publication of CN101073143A publication Critical patent/CN101073143A/zh
Application granted granted Critical
Publication of CN100459052C publication Critical patent/CN100459052C/zh
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31144—Etching the insulating layers by chemical or physical means using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H01L21/28123—Lithography-related aspects, e.g. sub-lithography lengths; Isolation-related aspects, e.g. to solve problems arising at the crossing with the side of the device isolation; Planarisation aspects
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H01L21/28123—Lithography-related aspects, e.g. sub-lithography lengths; Isolation-related aspects, e.g. to solve problems arising at the crossing with the side of the device isolation; Planarisation aspects
    • H01L21/28132—Lithography-related aspects, e.g. sub-lithography lengths; Isolation-related aspects, e.g. to solve problems arising at the crossing with the side of the device isolation; Planarisation aspects conducting part of electrode is difined by a sidewall spacer or a similar technique, e.g. oxidation under mask, plating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28247—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon passivation or protection of the electrode, e.g. using re-oxidation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32139—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66613—Lateral single gate silicon transistors with a gate recessing step, e.g. using local oxidation
    • H01L29/66628—Lateral single gate silicon transistors with a gate recessing step, e.g. using local oxidation recessing the gate by forming single crystalline semiconductor material at the source or drain location
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66659—Lateral single gate silicon transistors with asymmetry in the channel direction, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Ceramic Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)
  • Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)

Abstract

在多晶硅栅电极形成具有特定尺寸的间隔件的方法系于选择性外延生长期间保护多晶硅栅电极侧壁。不论间隔件是对称或非对称，本方法均能在严格的对准规格下，用界定多晶硅栅电极图案及图案间隔件的相同特定曝光工具(例如193nm波长之步进扫描式曝光工具)及相同的图案标线片，精确地界定间隔件。

Description

形成具有特定尺寸的栅极侧壁间隔件之半导体装置的方法
技术领域
本发明系有关半导体装置之制造方法。更明确地说，本发明系有关形成特定尺寸的间隔件的方法。
背景技术
现今，深次微米的互补式金氧半导体(CMOS)是极大型积体(ULSI)装置的主流技术。过去廿年内，微电子业界的主要焦点均集中于如何缩小CMOS晶体管的尺寸并增加集成电路(IC)的晶体管密度。
ULSI电路可包含CMOS场效晶体管(FET)，其半导体栅极系配置于漏极与源极区之间。漏极和源极区通常系掺杂有高浓度之P-型杂质(硼)或N-型杂质(磷)。
漏极和源极区通常含有薄的延伸区(浅的源极及漏极延伸区，shallow source and drain extensions)，这些延伸区系部份地配置于栅极下方以提高晶体管的性能。浅的源极及漏极延伸区有助于避免短信道效应(short channel effect)，短信道效应会降低n-信道以及p-信道晶体管的晶体管性能。短信道效应会导致临限(threshold)电压下滑和由漏极引起的能障降低。因为可以控制短信道效应，当晶体管变得更小时，浅的源极及漏极延伸区就因此特别重要。
传统的技术利用双植入(double implant)制程形成浅的源极及漏极延伸区。依传统制程，源极及漏极延伸区的形成方式系于硅衬底(substrate)顶部表面提供没有侧壁间隔件之晶体管栅极结构。位于栅极结构两侧的硅衬底系以传统的掺杂制程(例如扩散制程或离子植入制程)掺杂。由于没有侧壁间隔件，掺杂制程会将杂质引入衬底顶部表面正下方的薄区，以形成源极及漏极延伸区且部份地形成漏极及源极区。
漏极及源极延伸区形成之后，再将邻接栅极结构横向侧面的侧壁间隔件置于源极及漏极延伸区上方。侧壁间隔件定位之后，第二度掺杂衬底以形成深的源极及漏极区。于深的源极及漏极区的形成期间，由于侧壁间隔件的阻挡能力因而得以阻止对源极及漏极延伸区的进一步掺杂。
随着IC上所置之晶体管尺寸缩小，具有浅及极浅的源/漏极延伸区之晶体管变得更难以制造。举例而言，晶体管可能需要具有接面深度小于30奈米(nm)的极浅源极及漏极延伸区。用传统的制作技术非常难以形成具有接面深度小于30nm的源极及漏极延伸区。例如，传统的离子植入技术因为半导体衬底主体(bulk)中于离子植入期间所产生的点状缺陷会使杂质更容易扩散(瞬时增强型扩散，transient enhanceddiffusion，TED)，而难以保持浅的源极及漏极延伸区。这种扩散常将源极及漏极延伸区向下垂直延伸进入半导体衬底主体中。而且，传统的离子植入及扩散掺杂技术使IC上的晶体管容易产生短信道效应，从而造成延伸深入衬底中之杂质曲线尾部分布(tail distribution)。
要克服这些问题，可以用选择性的硅外延生长(selective epitaxialgrowth，SEG)令源极及漏极区加高，使得和源极及漏极接点的连接比较不那么困难。加高的源极及漏极区为接点硅化制程(contact silicidationprocesses)提供额外的材料，并且减少深的源/漏极接面电阻(junctionresistance)与源/漏极串接电阻(series resistance)。
产生加高之源极及漏极时要考量的事包括加高之源极及漏极与多晶硅栅极间的间隔距离。另一个要关心的事项是进行选择性的硅外延生长期间对多晶硅栅极的侧壁保护。进行选择性的外延生长期间，若多晶硅栅极的侧壁曝露在外，多晶硅曝露的区域就会发生不想要的生长。在产生加高的源极及漏极期间，可以于选择性的硅外延生长期间用传统的自我对准(self-aligned)技术加以覆盖并保护多晶硅。但在实际应用上，因为难以避免蚀刻制程期间多晶硅的曝露，从而难以产生具有精确距离的间隔件及确使多晶硅栅极侧壁受到保护。
发明内容
因此需要有个方法来产生具有特定尺寸的间隔件，以便在选择性硅外延生长期间用来保护多晶硅栅极侧壁。
本发明实施例可以满足本项及其它需求。本发明提供形成半导体配置的方法，包括采用界定栅电极的曝光工具以形成具有侧壁之栅电极的步骤。侧壁间隔件系采用相同曝光工具界定侧壁间隔件而形成于栅电极的侧壁。
通过采用相同特定曝光工具(例如步进扫瞄式(step and scan)曝光工具)，及于若干实施例中用来界定多晶硅栅电极所用的相同图案标线片，可以用极严格的对准规格形成图案间隔件。所产生的图案间隔件可以覆盖图案多晶硅栅极结构，并在选择性外延生长期间保护多晶硅栅极侧壁以避免不必要的选择性外延生长。间隔件图案的宽度受控于光微影(photolithography)制程的参数以及蚀刻制程的参数。本发明的若干实施例中，间隔件图案可在故意设定偏移的情况下进行对准以产生非对称间隔件，经由非对称间隔件可以达到更佳的装置性能。
提供于半导体制作期间控制侧壁间隔件尺寸的方法之本发明之其它方面也可以满足先前描述的需求。此方法包括形成具有侧壁之栅电极以及在侧壁形成侧壁间隔件的步骤，该侧壁间隔件的形成系经由在栅电极上置放间隔件层、在间隔件层上形成图案化光刻胶掩模(patterned resist mask)、及依图案光刻胶掩模蚀刻间隔件层。
配合以下之图式及说明，熟习此技艺者将能进一步了解本发明之其它特色及优点。
附图说明
图1系依照本发明实施例于制作过程之一阶段中之半导体晶圆之部份示意图；
图2系显示图1依照本发明实施例形成栅电极后之结构；
图3系显示图2依照本发明实施例置放间隔件层后之结构；
图4系显示图3依照本发明实施例界定光刻胶图案后之结构；
图5系显示图4依照本发明实施例蚀刻间隔件层后之结构；
图6系显示图5依照本发明实施例光刻胶被移除后之结构；
图7系显示图6依照本发明实施例选择性外延生长后之结构；
图8系依照本发明实施例形成非对称间隔件配置的示意图；以及
图9系习知曝光工具之侧视图，该曝光工具可用来进行本发明之方法。
具体实施方式
本发明处理并解决之问题系有关于选择性外延生长制程期间之多晶硅栅电极保护、及加高之源/漏极的形成以及它们与栅电极侧壁间之间隔。尤其，本发明对加高之源极和漏极可达到精确的间隔，并通过采用和界定多晶硅栅极图案相同的特定曝光工具，以极严格的对准规格界定图案间隔件，以确使多晶硅栅电极的侧壁得到保护。所产生的图案间隔件覆盖图案化多晶硅栅电极的结构，并在选择性外延生长期间保护多晶硅栅极侧壁。这样可以避免栅电极产生不想要的选择性硅外延生长。而且，间隔件图案的宽度精确地受控于光微影制程的参数及蚀刻制程的参数。在若干实施例中，间隔件图案在故意设定偏移的情况下进行对准以产生非对称间隔件，经由植入制程可以达到更佳的装置性能。
图1所示者为依照本发明实施例所形成之半导体装置之部分剖面图。提供之衬底10可以是任意合适之衬底，但在例示之实施例中采用硅衬底。栅极层12系以传统之沉积制程在衬底10上形成。栅极层12可以是(例如)多晶硅制成。栅极层12之深度应等于想要的最后栅电极结构之较佳深度。
覆盖层(cap layer)14系成形于栅极层12上方，且可为任意合适之深度，以在制程中某些阶段期间保护多晶硅栅电极的顶部。于某些实施例中，覆盖层14系以(例如)氮化硅制成。
图2系显示图1依照本发明实施例以蚀刻制程形成栅电极20后之结构。于本发明中，蚀刻制程采用特定之曝光工具以界定多晶硅栅电极图案。也可以采用例如图9所示之传统的曝光工具，该图容后细述。举例而言，可以采用传统193nm波长的步进扫瞄式曝光工具，配合特定之图案标线片(specific pattern reticle)来形成掩模(mask)。然后将掩模用于蚀刻多晶硅栅电极。
沉积间隔件层16，如图3所示。可以利用传统的覆被(blanket)沉积制程(例如化学气相沉积(CVD)或其它合适的方法)来形成间隔件层16。以传统的间隔件材料(例如氧化硅或氮化硅或其它合适的材料)形成间隔件层16。
沉积间隔件层16之后，接着界定间隔件并使其图案化。于本发明之实施例中，系将半导体晶图置于和用来形成多晶硅栅电极为相同工具之特定曝光工具。进而，用来界定多晶硅栅电极图案之相同图案标线片现在也用来界定图案化间隔件。因此，相同特定曝光工具(例如图9中所用者)也用于多晶硅栅电极20上形成光刻胶掩模18，如图4所示。这种方法利用的是曝光工具镜头性能及重叠配准(对准)性能的进步，以及标线片制作容错度的进步。
利用相同于形成用于形成栅电极20之光刻胶掩模18所用之特定曝光工具，在栅电极20上形成光刻胶掩模18后，以传统的方式进行蚀刻制程以产生图5之结构。因此，蚀刻间隔件层16会在栅电极20侧壁24产生间隔件22。间隔件22的宽度W极严格地受控于光微影制程的参数(例如曝光量、标线片相对于光刻胶之临界尺寸偏差量(reticleto resist C.D.bias))以及蚀刻制程的参数(例如蚀刻化学作用、功率、压力、过蚀刻时间)。
图6系显示图5以传统光刻胶移除技术移除光刻胶18后之结构。这样在多晶硅栅电极20侧壁24及覆盖层14上留下间隔件22。于所要的制程步骤，如图7所示，进行选择性外延生长制程以产生选择性外延生长区26。这些区域通过具有精确宽度W之间隔件22而与多晶硅栅电极相隔特定的距离。整个多晶硅栅电极20在此制程中受到间隔件22保护而不会有不想要的选择性外延生长。于此阶段，间隔件层16可以整个被蚀刻或移除，以进行进一步的处理。
图6及图7中间隔件22之图标实施例显示间隔件具有对称之宽度。但在本发明之某些实施例中，所形成的是具有不同宽度之非对称间隔件，如图8所示。间隔件的非对称宽度可改进装置性能，这是因为它容许非对称掺杂以改进个别晶体管之性能。举例而言，非对称间隔件容许n-信道晶体管的最佳特性自p-信道晶体管去耦合(decoupling)，并视功能之不同(例如将驱动电流加至最大或使短信道效应达到最佳)避免相似掺杂的n-型晶体管或p-型晶体管之性能去耦合。
依照本发明的实施例，在故意设定偏移的情况下对间隔图案进行对准以获得非对称间隔件。举例而言，如图9所示之步进扫瞄式曝光工具中，可将偏移值设于曝光工具之对准参数。因此，光刻胶18于多晶硅栅电极20上方不会以对准中央的方式而是以所要之量偏离的方式进行对准。接下来蚀刻间隔件层16会产生图8之结构。进一步的处理可依前所述者进行。
为了说明，例示之步进扫瞄式曝光工具如图9所示，其中包括光照系统30，用以提供光照予装置。图案标线片32由标线片转盘34所支撑。如前所述，相同特定标线片32同时用于图案化多晶硅栅电极20及间隔件22。镜头装置36将来自光照系统30的光聚焦于由吸盘(chuck)40所承载之半导体晶圆38。控制器42控制步进扫瞄式曝光工具之运作。
因此，用本发明之方法，可产生尺寸精确受控之间隔件，不管是对称或非对称，俾于选择性外延生长期间保护多晶硅侧壁，从而避免于多晶硅栅电极曝露区域发生不想要之选择性外延生长。
虽然以上已对本发明进行深入之描述与说明，熟习此技艺者应了解，所作之描述及例示系说明之用而非用来限制，而本发明之范畴系界定于以下所附之申请专利范围。

Claims (8)

1.一种形成半导体装置的方法，包括下列步骤：
形成具有侧壁(24)的栅电极(20)，采用曝光工具(30-42)以界定该栅电极(20)；
在该栅电极(20)的侧壁(24)上形成侧壁间隔件(22)，采用相同的曝光工具(30-42)以界定该侧壁间隔件(22)，其中该侧壁间隔件(22)的形成包括在该栅电极(20)上方沉积间隔件层(16)，并在由该曝光工具(30-42)所界定的该间隔件层(16)上形成光刻胶掩模(18)，使得该光刻胶掩模(18)延伸超出该栅电极(20)的侧壁(24)；以及
依照该光刻胶掩模(18)各向异性蚀刻该间隔件层(16)以形成该侧壁间隔件(22)。
2.如权利要求1所述的方法，其中该栅电极(20)的形成包括采用图案标线片(32)；以及
该侧壁间隔件(22)的形成包括采用形成该栅电极(20)所用的相同图案标线片(32)。
3.如权利要求1或2所述的方法，还包括在其上形成有该栅电极(20)的衬底(10)上进行选择性外延生长，该侧壁间隔件(22)在进行该选择性外延生长的期间保护该栅电极(20)的侧壁(24)免于选择性外延生长。
4.如权利要求3所述的方法，其中该栅电极(20)的侧壁(24)上的该侧壁间隔件(22)具有对称宽度。
5.如权利要求3所述的方法，其中该栅电极(20)的侧壁(24)上的该侧壁间隔件(22)具有非对称宽度；以及
还包括当形成该侧壁间隔件(22)时偏移该曝光工具(30-42)的对准，该偏移的步骤包括将偏移值加入该曝光工具(30-42)的对准参数。
6.一种在半导体制造期间控制侧壁间隔件尺寸的方法，包括下列步骤：
形成具有侧壁(24)的栅电极(20)；
在该侧壁(24)上形成侧壁间隔件(22)，其中该侧壁间隔件的形成是通过：在该栅电极(20)上沉积间隔件层(16)；以及
在该间隔件层(16)上形成图案光刻胶掩模(18)，使得该图案光刻胶掩模(18)延伸超出该栅电极(20)的侧壁(24)，以及依照该图案光刻胶掩模(18)蚀刻该间隔件层(16)，其中形成该栅电极(20)的步骤包括用曝光工具(30-42)及图案标线片(32)界定该栅电极(20)，且形成该侧壁间隔件(22)的步骤包括用相同的曝光工具(30-42)及图案标线片(32)界定该图案光刻胶掩模(18)。
7.如权利要求6所述的方法，其中该侧壁间隔件(22)为对称的。
8.如权利要求6所述的方法，其中该侧壁间隔件(22)为非对称的。
CNB2005800392172A 2004-12-03 2005-11-29 形成具有特定尺寸的栅极侧壁间隔件之半导体装置的方法 Expired - Fee Related CN100459052C (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US11/002,586 2004-12-03
US11/002,586 US7279386B2 (en) 2004-12-03 2004-12-03 Method for forming a semiconductor arrangement with gate sidewall spacers of specific dimensions

Publications (2)

Publication Number Publication Date
CN101073143A CN101073143A (zh) 2007-11-14
CN100459052C true CN100459052C (zh) 2009-02-04

Family

ID=36218711

Family Applications (1)

Application Number Title Priority Date Filing Date
CNB2005800392172A Expired - Fee Related CN100459052C (zh) 2004-12-03 2005-11-29 形成具有特定尺寸的栅极侧壁间隔件之半导体装置的方法

Country Status (8)

Country Link
US (1) US7279386B2 (zh)
EP (1) EP1829092B1 (zh)
JP (1) JP2008522441A (zh)
KR (1) KR101142992B1 (zh)
CN (1) CN100459052C (zh)
DE (1) DE602005011483D1 (zh)
TW (1) TWI397107B (zh)
WO (1) WO2006060528A2 (zh)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7279386B2 (en) * 2004-12-03 2007-10-09 Advanced Micro Devices, Inc. Method for forming a semiconductor arrangement with gate sidewall spacers of specific dimensions
US7585735B2 (en) * 2005-02-01 2009-09-08 Freescale Semiconductor, Inc. Asymmetric spacers and asymmetric source/drain extension layers
US20110049582A1 (en) * 2009-09-03 2011-03-03 International Business Machines Corporation Asymmetric source and drain stressor regions
CN103943462A (zh) * 2014-04-28 2014-07-23 上海华力微电子有限公司 针对薄膜沉积产生负载效应的消除方法
CN103928315B (zh) * 2014-04-28 2017-06-23 上海华力微电子有限公司 一种栅极侧墙减薄工艺
US9941388B2 (en) 2014-06-19 2018-04-10 Globalfoundries Inc. Method and structure for protecting gates during epitaxial growth
US10566194B2 (en) * 2018-05-07 2020-02-18 Lam Research Corporation Selective deposition of etch-stop layer for enhanced patterning

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4033026A (en) * 1975-12-16 1977-07-05 Intel Corporation High density/high speed MOS process and device
US5930634A (en) * 1997-04-21 1999-07-27 Advanced Micro Devices, Inc. Method of making an IGFET with a multilevel gate
US6300208B1 (en) * 2000-02-16 2001-10-09 Ultratech Stepper, Inc. Methods for annealing an integrated device using a radiant energy absorber layer
CN1391258A (zh) * 2001-06-12 2003-01-15 三菱电机株式会社 半导体装置的制造方法
CN1470947A (zh) * 2002-06-27 2004-01-28 株式会社东芝 电子束曝光的邻近效应修正方法及其应用

Family Cites Families (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2685149B2 (ja) * 1988-04-11 1997-12-03 住友電気工業株式会社 電界効果トランジスタの製造方法
JPH08335554A (ja) * 1995-06-07 1996-12-17 Oki Electric Ind Co Ltd 半導体素子の製造方法
US5656518A (en) * 1996-09-13 1997-08-12 Advanced Micro Devices, Inc. Method for fabrication of a non-symmetrical transistor
JP3530692B2 (ja) * 1996-11-06 2004-05-24 キヤノン株式会社 走査型露光装置及びそれを用いたデバイスの製造方法
JP3598693B2 (ja) * 1996-12-03 2004-12-08 ソニー株式会社 半導体装置およびその製造方法
JPH10242460A (ja) * 1997-02-25 1998-09-11 Hitachi Ltd 半導体集積回路装置およびその製造方法
JP2000012844A (ja) * 1998-06-19 2000-01-14 Sony Corp 高耐圧半導体装置及びその製造方法
KR100284905B1 (ko) * 1998-10-16 2001-04-02 윤종용 반도체 장치의 콘택 형성 방법
JP2000260701A (ja) * 1999-03-10 2000-09-22 Toshiba Corp パターン形成方法及びそれを用いた半導体装置の製造方法
JP3381147B2 (ja) * 1999-04-16 2003-02-24 日本電気株式会社 半導体装置及びその製造方法
JP2001250756A (ja) * 2000-03-03 2001-09-14 Hitachi Ltd 半導体集積回路装置の製造方法
TW540102B (en) * 2001-12-31 2003-07-01 Silicon Integrated Sys Corp Formation method of oxide film
JP2004165218A (ja) * 2002-11-08 2004-06-10 Canon Inc 露光装置
TWI222227B (en) * 2003-05-15 2004-10-11 Au Optronics Corp Method for forming LDD of semiconductor devices
JP2005012038A (ja) * 2003-06-20 2005-01-13 Renesas Technology Corp 半導体装置の製造方法
US6893967B1 (en) * 2004-01-13 2005-05-17 Advanced Micro Devices, Inc. L-shaped spacer incorporating or patterned using amorphous carbon or CVD organic materials
US7279386B2 (en) 2004-12-03 2007-10-09 Advanced Micro Devices, Inc. Method for forming a semiconductor arrangement with gate sidewall spacers of specific dimensions

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4033026A (en) * 1975-12-16 1977-07-05 Intel Corporation High density/high speed MOS process and device
US5930634A (en) * 1997-04-21 1999-07-27 Advanced Micro Devices, Inc. Method of making an IGFET with a multilevel gate
US6300208B1 (en) * 2000-02-16 2001-10-09 Ultratech Stepper, Inc. Methods for annealing an integrated device using a radiant energy absorber layer
CN1391258A (zh) * 2001-06-12 2003-01-15 三菱电机株式会社 半导体装置的制造方法
CN1470947A (zh) * 2002-06-27 2004-01-28 株式会社东芝 电子束曝光的邻近效应修正方法及其应用

Also Published As

Publication number Publication date
EP1829092B1 (en) 2008-12-03
WO2006060528A2 (en) 2006-06-08
DE602005011483D1 (de) 2009-01-15
TW200623235A (en) 2006-07-01
US20060121711A1 (en) 2006-06-08
CN101073143A (zh) 2007-11-14
KR20070085551A (ko) 2007-08-27
KR101142992B1 (ko) 2012-05-15
EP1829092A2 (en) 2007-09-05
JP2008522441A (ja) 2008-06-26
TWI397107B (zh) 2013-05-21
US7279386B2 (en) 2007-10-09
WO2006060528A3 (en) 2006-10-26

Similar Documents

Publication Publication Date Title
US8173500B2 (en) Poly-emitter type bipolar junction transistor, bipolar CMOS DMOS device, and manufacturing methods of poly-emitter type bipolar junction transistor and bipolar CMOS DMOS device
CN100459052C (zh) 形成具有特定尺寸的栅极侧壁间隔件之半导体装置的方法
US20060273391A1 (en) CMOS devices for low power integrated circuits
JPH01101662A (ja) Ｃｍｏｓ集積回路デバイスの製造方法
WO2017016023A1 (zh) 一种低温多晶硅薄膜晶体管及其制造方法
JP2009055041A (ja) 半導体素子及びその製造方法
JPH04221835A (ja) バイポーラ・トランジスタとその製法
US6458666B2 (en) Spot-implant method for MOS transistor applications
KR100582374B1 (ko) 고전압 트랜지스터 및 그 제조 방법
KR100840659B1 (ko) 디이모스 소자의 제조 방법
US8084340B2 (en) Method of manufacturing semiconductor device and semiconductor device
KR20100007533A (ko) 반도체 집적 회로 장치의 제조 방법
KR100479820B1 (ko) 반도체소자의 제조방법
KR100369863B1 (ko) 이에스디 보호 회로의 트랜지스터 및 그의 제조 방법
KR100353466B1 (ko) 트랜지스터 및 그의 제조 방법
JP2005142528A (ja) モストランジスタ及びその製造方法
KR100935249B1 (ko) 고전압 소자 및 그의 제조 방법
US20080042198A1 (en) Demos structure
KR100595128B1 (ko) 정전기 방전 보호 소자 및 그 제조 방법
JP2004296914A (ja) 半導体装置およびその製造方法
KR100573274B1 (ko) 전계 효과 트렌지스터 및 그의 제조방법
KR100905183B1 (ko) 반도체 소자의 형성 방법
KR100222043B1 (ko) 모스 트랜지스터 및 그 제조방법
KR20090088677A (ko) 반도체 소자 및 그 제조방법
JP2005005457A (ja) 半導体装置および半導体装置の製造方法

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C14 Grant of patent or utility model
GR01 Patent grant
ASS Succession or assignment of patent right

Owner name: GLOBALFOUNDRIES INC.

Free format text: FORMER OWNER: ADVANCED MICRO DEVICES INC.

Effective date: 20100730

C41 Transfer of patent application or patent right or utility model
COR Change of bibliographic data

Free format text: CORRECT: ADDRESS; FROM: CALIFORNIA STATE, USA TO: CAYMAN ISLANDS GRAND CAYMAN ISLAND

TR01 Transfer of patent right

Effective date of registration: 20100730

Address after: Grand Cayman, Cayman Islands

Patentee after: Globalfoundries Semiconductor Inc.

Address before: American California

Patentee before: Advanced Micro Devices Inc.

CF01 Termination of patent right due to non-payment of annual fee
CF01 Termination of patent right due to non-payment of annual fee

Granted publication date: 20090204

Termination date: 20161129