TWI397107B - 形成具有特定尺寸之閘極側壁間隔件之半導體配置之方法 - Google Patents

形成具有特定尺寸之閘極側壁間隔件之半導體配置之方法 Download PDF

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TWI397107B
TWI397107B TW094141232A TW94141232A TWI397107B TW I397107 B TWI397107 B TW I397107B TW 094141232 A TW094141232 A TW 094141232A TW 94141232 A TW94141232 A TW 94141232A TW I397107 B TWI397107 B TW I397107B
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Mark C Kelling
Douglas Bonser
Srikanteswara Dakshina-Murthy
Asuka Nomura
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Globalfoundries Us Inc
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Description

形成具有特定尺寸之閘極側壁間隔件之半導體配置之方法
本發明係有關半導體裝置之製造方法。更明確地說，本發明係有關形成特定尺寸之間隔件的方法。
現今，深次微米的互補式金氧半導體(CMOS)是極大型積體(ULSI)裝置的主流技術。過去廿年內，微電子業界的主要焦點均集中於如何縮小CMOS電晶體的尺寸並增加積體電路(IC)的電晶體密度。
ULSI電路可包含CMOS場效電晶體(FET)，其半導體閘極係配置於汲極與源極區之間。汲極和源極區通常係摻雜有高濃度之P－型雜質(硼)或N－型雜質(磷)。
汲極和源極區通常含有薄的延伸區(淺的源極及汲極延伸區,shallow source and drain extensions)，這些延伸區係部份地配置於閘極下方以提高電晶體的性能。淺的源極及汲極延伸區有助於避免短通道效應(short channel effect)，短通道效應會降低n－通道以及p－通道電晶體的電晶體性能。短通道效應會導致臨限(threshold)電壓下滑和由汲極引起的能障降低。因為可以控制短通道效應，當電晶體變得更小時，淺的源極及汲極延伸區就因此特別重要。
傳統的技術利用雙植入(double implant)製程形成淺的源極及汲極延伸區。依傳統製程，源極及汲極延伸區之形成方式係於矽基材(substrate)頂部表面提供沒有側壁間隔件之電晶體閘極結構。位於閘極結構兩側的矽基材係以傳統的摻雜製程(例如擴散製程或離子植入製程)摻雜。由於沒有側壁間隔件，摻雜製程會將雜質引入基材頂部表面正下方的薄區，以形成源極及汲極延伸區且部份地形成汲極及源極區。
汲極及源極延伸區形成之後，再將鄰接閘極結構橫向側面的側壁間隔件置於源極及汲極延伸區上方。側壁間隔件定位之後，第二度摻雜基材以形成深的源極及汲極區。於深的源極及汲極區之形成期間，由於側壁間隔件的阻擋能力因而得以阻止對源極及汲極延伸區的進一步摻雜。
隨著IC上所置之電晶體尺寸縮小，具有淺及極淺的源/汲極延伸區之電晶體變得更難以製造。舉例而言，電晶體可能需要具有接面深度小於30奈米(nm)的極淺源極及汲極延伸區。用傳統的製作技術非常難以形成具有接面深度小於30nm的源極及汲極延伸區。例如，傳統的離子植入技術因為半導體基材主體(bulk)中於離子植入期間所產生的點狀缺陷會使雜質更容易擴散(暫態增強型擴散，transient enhanced diffusion,TED)，而難以保持淺的源極及汲極延伸區。這種擴散常將源極及汲極延伸區向下垂直延伸進入半導體基材主體中。而且，傳統的離子植入及擴散摻雜技術使IC上的電晶體容易產生短通道效應，從而造成延伸深入基材中之雜質曲線尾部分佈(tail distribution)。
要克服這些問題，可以用選擇性的矽磊晶成長(selective epitaxial growth,SEG)令源極及汲極區加高，使得和源極及汲極接點的連接比較不那麼困難。加高的源極及汲極區為接點矽化製程(contact silicidation processes)提供額外的材料，並且減少深的源/汲極接面電阻(junction resistance)與源/汲極串接電阻(series resistance)。
產生加高之源極及汲極時要考量的事包括加高之源極及汲極與多晶矽閘極間的間隔距離。另一個要關心的事項是進行選擇性的矽磊晶成長期間對多晶矽閘極的側壁保護。進行選擇性的磊晶成長期間，若多晶矽閘極的側壁曝露在外，多晶矽曝露的區域就會發生不想要的成長。在產生加高的源極及汲極期間，可以於選擇性的矽磊晶成長期間用傳統的自我對準(self－aligned)技術加以覆蓋並保護多晶矽。但在實際應用上，因為難以避免蝕刻製程期間多晶矽的曝露，從而難以產生具有精確距離的間隔件及確使多晶矽閘極側壁受到保護。
因此需要有個方法來產生具有特定尺寸之間隔件，以便在選擇性矽磊晶成長期間用來保護多晶矽閘極側壁。
本發明實施例可以滿足本項及其它需求。本發明提供形成半導體配置的方法，包括採用定義閘電極之曝光工具以形成具有側壁之閘電極的步驟。側壁間隔件係採用相同曝光工具定義側壁間隔件而形成於閘電極之側壁。
藉由採用相同特定曝光工具(例如步進掃瞄式曝光工具)，及於若干實施例中用來定義多晶矽閘電極所用的相同圖樣光罩，可以用極嚴格的對準規格形成圖樣間隔件。所產生的圖樣間隔件可以覆蓋圖樣多晶矽閘極結構，並在選擇性磊晶成長期間保護多晶矽閘極側壁以避免不必要的選擇性磊晶成長。間隔件圖樣的寬度受控於光微影(photolithography)製程的參數以及蝕刻製程的參數。本發明的若干實施例中，間隔件圖樣可在故意設定差距值的情況下進行對準以產生非對稱間隔件，經由非對稱間隔件可以達到更佳的裝置性能。
提供於半導體製作期間控制側壁間隔件尺寸的方法之本發明之其它方面也可以滿足先前描述的需求。此方法包括形成具有側壁之閘電極以及在側壁形成側壁間隔件的步驟，該側壁間隔件之形成係經由在閘電極上置放間隔件層、在間隔件層上形成圖樣化光阻遮罩(patterned resist mask)、及依圖樣光阻遮罩蝕刻間隔件層。
配合以下之圖式及說明，熟習此技藝者將能進一步了解本發明之其它特色及優點。
本發明處理並解決之問題係有關於選擇性磊晶成長製程期間之多晶矽閘電極保護、及加高之源/汲極的形成以及它們與閘電極側壁間之間隔。尤其，本發明對加高之源極和汲極可達到精確的間隔，並藉由採用和定義多晶矽閘極圖樣相同的特定曝光工具，以極嚴格的對準規格定義圖樣間隔件，以確使多晶矽閘電極之側壁得到保護。所產生的圖樣間隔件覆蓋圖樣化多晶矽閘電極之結構，並在選擇性磊晶成長期間保護多晶矽閘極側壁。這樣可以避免閘電極產生不想要的選擇性矽磊晶成長。而且，間隔件圖樣的寬度精確地受控於光微影製程的參數及蝕刻製程的參數。在若干實施例中，間隔件圖樣在故意設定差距值的情況下進行對準以產生非對稱間隔件，經由植入製程可以達到更佳的裝置性能。
第1圖所示者為依照本發明實施例所形成之半導體裝置之部分剖面圖。提供之基材10可以是任意合適之基材，但在例示之實施例中採用矽基材。閘極層12係以傳統之沈積製程在基材10上形成。閘極層12可以是(例如)多晶矽製成。閘極層12之深度應等於想要的最後閘電極結構之較佳深度。
覆蓋層(cap layer)14係成形於閘極層12上方，且可為任意合適之深度，以在製程中某些階段期間保護多晶矽閘電極之頂部。於某些實施例中，覆蓋層14係以(例如)氮化矽製成。
第2圖係顯示第1圖依照本發明實施例以蝕刻製程形成閘電極20後之結構。於本發明中，蝕刻製程採用特定之曝光工具以定義多晶矽閘電極圖樣。也可以採用例如第9圖所示之傳統的曝光工具，該圖容後細述。舉例而言，可以採用傳統193nm波長的步進掃瞄式曝光工具，配合特定之圖樣光罩(specific pattern reticle)來形成遮罩(mask)。然後將遮罩用於蝕刻多晶矽閘電極。
沈積間隔件層16，如第3圖所示。可以利用傳統的覆被(blanket)沈積製程(例如化學氣相沈積(CVD)或其它合適的方法)來形成間隔件層16。以傳統的間隔件材料(例如氧化矽或氮化矽或其它合適的材料)形成間隔件層16。
沈積間隔件層16之後，接著定義間隔件並使其圖樣化。於本發明之實施例中，係將半導體晶圖置於和用來形成多晶矽閘電極為相同工具之特定曝光工具。進而，用來定義多晶矽閘電極圖樣之相同圖樣光罩現在也用來定義圖樣化間隔件。因此，相同特定曝光工具(例如第9圖中所用者)也用於多晶矽閘電極20上形成光阻遮罩18，如第4圖所示。這種方法利用的是曝光工具鏡頭性能及重疊配準(對準)性能的進步，以及光罩製作容錯度的進步。
利用相同於形成用於形成閘電極20之光阻遮罩18所用之特定曝光工具，在閘電極20上形成光阻遮罩18後，以傳統的方式進行蝕刻製程以產生第5圖之結構。因此，蝕刻間隔件層16會在閘電極20側壁24產生間隔件22。間隔件22的寬度W極嚴格地受控於光微影製程的參數(例如曝光量、光罩相對於光阻之臨界尺寸偏差量(reticle to resist C.D.bias))以及蝕刻製程的參數(例如蝕刻化學作用、功率、壓力、過蝕刻時間)。
第6圖係顯示第5圖以傳統光阻移除技術移除光阻18後之結構。這樣在多晶矽閘電極20側壁24及覆蓋層14上留下間隔件22。於所要的製程步驟，如第7圖所示，進行選擇性磊晶成長製程以產生選擇性磊晶成長區26。這些區域藉由具有精確寬度W之間隔件22而與多晶矽閘電極相隔特定的距離。整個多晶矽閘電極20在此製程中受到間隔件22保護而不會有不想要的選擇性磊晶成長。於此階段，間隔件層16可以整個被蝕刻或移除，以進行進一步的處理。
第6圖及第7圖中間隔件22之圖示實施例顯示間隔件具有對稱之寬度。但在本發明之某些實施例中，所形成的是具有不同寬度之非對稱間隔件，如第8圖所示。間隔件的非對稱寬度可改進裝置性能，這是因為它容許非對稱摻雜以改進個別電晶體之性能。舉例而言，非對稱間隔件容許n－通道電晶體的最佳特性自p－通道電晶體去耦合(decoupling)，並視功能之不同(例如將驅動電流加至最大或使短通道效應達到最佳)避免相似摻雜的n－型電晶體或p－型電晶體之性能去耦合。
依照本發明的實施例，在故意設定差距值的情況下對間隔圖樣進行對準以獲得非對稱間隔件。舉例而言，如第9圖所示之步進掃瞄式曝光工具中，可將差距值設於曝光工具之對準參數。因此，光阻18於多晶矽閘電極20上方不會以對準中央的方式而是以所要之量偏離的方式進行對準。接下來蝕刻間隔件層16會產生第8圖之結構。進一步的處理可依前所述者進行。
為了說明，例示之步進掃瞄式曝光工具如第9圖所示，其中包括光照系統30，用以提供光照予裝置。圖樣光罩32由光罩轉盤34所支撐。如前所述，相同特定光罩32同時用於圖樣化多晶矽閘電極20及間隔件22。鏡頭裝置36將來自光照系統30的光聚焦於由吸盤(chuck)40所承載之半導體晶圓38。控制器42控制步進掃瞄式曝光工具之運作。
因此，用本發明之方法，可產生尺寸精確受控之間隔件，不管是對稱或非對稱，俾於選擇性磊晶成長期間保護多晶矽側壁，從而避免於多晶矽閘電極曝露區域發生不想要之選擇性磊晶成長。
雖然以上已對本發明進行深入之描述與說明，熟習此技藝者應了解，所作之描述及例示係說明之用而非用來限制，而本發明之範疇係定義於以下所附之申請專利範圍。
10．．．基材
12．．．閘極層
14．．．覆蓋層
16．．．間隔件層
18．．．光阻遮罩
20．．．閘電極
22．．．間隔件
24．．．側壁
26．．．磊晶成長區
30．．．光照系統
32．．．光罩
34．．．光罩轉盤
36．．．鏡頭裝置
38．．．半導體晶圓
40．．．吸盤
42．．．控制器
第1圖係依照本發明實施例於製作過程之一階段中之半導體晶圓之部份示意圖；第2圖係顯示第1圖依照本發明實施例形成閘電極後之結構；第3圖係顯示第2圖依照本發明實施例置放間隔件層後之結構；第4圖係顯示第3圖依照本發明實施例定義光阻圖樣後之結構；第5圖係顯示第4圖依照本發明實施例蝕刻間隔件層後之結構；第6圖係顯示第5圖依照本發明實施例光阻被移除後之結構；第7圖係顯示第6圖依照本發明實施例選擇性磊晶成長後之結構；第8圖係依照本發明實施例形成非對稱間隔件配置之示意圖；以及第9圖係習知曝光工具之側視圖，該曝光工具可用來進行本發明之方法。
10．．．基材
12．．．閘極層
14．．．覆蓋層
20．．．閘電極
22．．．間隔件
24．．．側壁
26．．．磊晶成長區

Claims (15)

  1. 一種形成半導體配置之方法，包括下列步驟：採用曝光工具及圖樣光罩定義閘電極以形成具有側壁之該閘電極；用相同曝光工具及圖樣光罩定義側壁間隔件以在該閘電極側壁形成該側壁間隔件。
  2. 如申請專利範圍第1項之方法，其中該曝光工具為步進掃瞄式曝光工具。
  3. 如申請專利範圍第2項之方法，其中該閘電極之形成包括採用圖樣光罩。
  4. 如申請專利範圍第3項之方法，其中該側壁間隔件之形成包括採用形成該閘電極所用的相同圖樣光罩。
  5. 如申請專利範圍第4項之方法，其中該側壁間隔件之形成包括於該閘電極上方沈積間隔件層，並在該圖樣光罩所定義的該間隔件上形成光阻遮罩。
  6. 如申請專利範圍第5項之方法，復包括依照該光阻遮罩以各向異性方式蝕刻該間隔件層以形成該側壁間隔件。
  7. 如申請專利範圍第6項之方法，復包括在形成有該閘電極之基材上進行選擇性磊晶成長，該側壁間隔件在進行該選擇性磊晶成長的期間保護該閘電極側壁免於選擇性磊晶成長。
  8. 如申請專利範圍第7項之方法，其中該閘電極側壁之該側壁間隔件具有對稱寬度。
  9. 如申請專利範圍第7項之方法，其中該閘電極側壁之該 側壁間隔件具有非對稱寬度。
  10. 如申請專利範圍第9項之方法，復包括於形成該側壁間隔件時，偏移該曝光工具的對準。
  11. 如申請專利範圍第10項之方法，其中偏移對準之步驟包括於該曝光工具之對準參數加入差距值(offset value)。
  12. 一種於製作半導體期間控制側壁間隔件尺寸之方法，包括下列步驟：用曝光工具及圖樣光罩定義閘電極，以形成具有側壁之該閘電極；及在該側壁形成側壁間隔件，其中該側壁間隔件的形成係藉由在該閘電極上沈積間隔件層；在該間隔件層上用相同曝光工具及圖樣光罩定義並形成圖樣光阻遮罩；及依照該圖樣光阻遮罩蝕刻該間隔件層。
  13. 如申請專利範圍第12項之方法，其中該側壁間隔件為對稱。
  14. 如申請專利範圍第12項之方法，其中該側壁間隔件為非對稱。
  15. 如申請專利範圍第14項之方法，其中形成該非對稱側壁間隔件之步驟包括偏移該曝光工具的對準。
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Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7279386B2 (en) * 2004-12-03 2007-10-09 Advanced Micro Devices, Inc. Method for forming a semiconductor arrangement with gate sidewall spacers of specific dimensions
US7585735B2 (en) * 2005-02-01 2009-09-08 Freescale Semiconductor, Inc. Asymmetric spacers and asymmetric source/drain extension layers
US20110049582A1 (en) * 2009-09-03 2011-03-03 International Business Machines Corporation Asymmetric source and drain stressor regions
CN103928315B (zh) * 2014-04-28 2017-06-23 上海华力微电子有限公司 一种栅极侧墙减薄工艺
CN103943462A (zh) * 2014-04-28 2014-07-23 上海华力微电子有限公司 针对薄膜沉积产生负载效应的消除方法
US9941388B2 (en) 2014-06-19 2018-04-10 Globalfoundries Inc. Method and structure for protecting gates during epitaxial growth
US10566194B2 (en) * 2018-05-07 2020-02-18 Lam Research Corporation Selective deposition of etch-stop layer for enhanced patterning

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW540102B (en) * 2001-12-31 2003-07-01 Silicon Integrated Sys Corp Formation method of oxide film
TW200425522A (en) * 2003-05-15 2004-11-16 Au Optronics Corp Method for forming LDD of semiconductor devices

Family Cites Families (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4033026A (en) * 1975-12-16 1977-07-05 Intel Corporation High density/high speed MOS process and device
JP2685149B2 (ja) * 1988-04-11 1997-12-03 住友電気工業株式会社 電界効果トランジスタの製造方法
JPH08335554A (ja) * 1995-06-07 1996-12-17 Oki Electric Ind Co Ltd 半導体素子の製造方法
US5656518A (en) * 1996-09-13 1997-08-12 Advanced Micro Devices, Inc. Method for fabrication of a non-symmetrical transistor
JP3530692B2 (ja) * 1996-11-06 2004-05-24 キヤノン株式会社 走査型露光装置及びそれを用いたデバイスの製造方法
JP3598693B2 (ja) * 1996-12-03 2004-12-08 ソニー株式会社 半導体装置およびその製造方法
JPH10242460A (ja) * 1997-02-25 1998-09-11 Hitachi Ltd 半導体集積回路装置およびその製造方法
US5930634A (en) * 1997-04-21 1999-07-27 Advanced Micro Devices, Inc. Method of making an IGFET with a multilevel gate
JP2000012844A (ja) * 1998-06-19 2000-01-14 Sony Corp 高耐圧半導体装置及びその製造方法
KR100284905B1 (ko) * 1998-10-16 2001-04-02 윤종용 반도체 장치의 콘택 형성 방법
JP2000260701A (ja) * 1999-03-10 2000-09-22 Toshiba Corp パターン形成方法及びそれを用いた半導体装置の製造方法
JP3381147B2 (ja) * 1999-04-16 2003-02-24 日本電気株式会社 半導体装置及びその製造方法
US6300208B1 (en) * 2000-02-16 2001-10-09 Ultratech Stepper, Inc. Methods for annealing an integrated device using a radiant energy absorber layer
JP2001250756A (ja) * 2000-03-03 2001-09-14 Hitachi Ltd 半導体集積回路装置の製造方法
JP4776813B2 (ja) * 2001-06-12 2011-09-21 ルネサスエレクトロニクス株式会社 半導体装置の製造方法
JP3725841B2 (ja) * 2002-06-27 2005-12-14 株式会社東芝 電子ビーム露光の近接効果補正方法、露光方法、半導体装置の製造方法及び近接効果補正モジュール
JP2004165218A (ja) * 2002-11-08 2004-06-10 Canon Inc 露光装置
JP2005012038A (ja) * 2003-06-20 2005-01-13 Renesas Technology Corp 半導体装置の製造方法
US6893967B1 (en) * 2004-01-13 2005-05-17 Advanced Micro Devices, Inc. L-shaped spacer incorporating or patterned using amorphous carbon or CVD organic materials
US7279386B2 (en) 2004-12-03 2007-10-09 Advanced Micro Devices, Inc. Method for forming a semiconductor arrangement with gate sidewall spacers of specific dimensions

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW540102B (en) * 2001-12-31 2003-07-01 Silicon Integrated Sys Corp Formation method of oxide film
TW200425522A (en) * 2003-05-15 2004-11-16 Au Optronics Corp Method for forming LDD of semiconductor devices

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