WO2017016023A1 - 一种低温多晶硅薄膜晶体管及其制造方法 - Google Patents

一种低温多晶硅薄膜晶体管及其制造方法 Download PDF

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WO2017016023A1
WO2017016023A1 PCT/CN2015/088415 CN2015088415W WO2017016023A1 WO 2017016023 A1 WO2017016023 A1 WO 2017016023A1 CN 2015088415 W CN2015088415 W CN 2015088415W WO 2017016023 A1 WO2017016023 A1 WO 2017016023A1
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layer
dopant ions
semiconductor layer
specific region
high concentration
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PCT/CN2015/088415
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English (en)
French (fr)
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卢昶鸣
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深圳市华星光电技术有限公司
武汉华星光电技术有限公司
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Priority to US14/909,092 priority Critical patent/US9842935B2/en
Publication of WO2017016023A1 publication Critical patent/WO2017016023A1/zh

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Definitions

  • the present invention relates to the field of transistor fabrication, and more particularly to a low temperature polysilicon thin film transistor and a method of fabricating the same.
  • TFTs thin film transistors
  • TFTs made by LTPS have higher electron mobility.
  • TFTs fabricated by LTPS can be applied to make liquid crystal displays have higher resolution and lower power consumption. Therefore, low temperature polysilicon technology has been widely used and studied.
  • TFT Thin Film Transistor
  • the invention provides a low-temperature polysilicon thin film transistor and a manufacturing method thereof, which can solve the problem that two masks are needed when the source-drain heavy doping and the LDD light doping are used in the LDD process using the LTPS technology.
  • a first aspect of the embodiments of the present invention provides a method for manufacturing a low temperature polysilicon thin film transistor, including:
  • a first cobalt layer corresponding to the first photoresist layer is disposed on each of the first photoresist layers, and a vertical projection of the first cobalt layer coincides with a vertical projection of the first photoresist layer corresponding to the first cobalt layer;
  • Removing the first cobalt layer performing partial ashing treatment on the plurality of first photoresist layers to obtain a plurality of second photoresist layers of a second predetermined thickness, wherein the second predetermined thickness is less than the First predetermined thickness;
  • a second cobalt layer corresponding to the second photoresist layer is disposed on each of the second photoresist layers, and a vertical projection of the second cobalt layer coincides with a vertical projection of the second photoresist layer corresponding to the second cobalt layer;
  • the second cobalt layer is removed, and the second photoresist layer is completely ashed to remove the second photoresist layer.
  • the plurality of first photoresist layers are partially ashed to obtain a plurality of second photoresist layers of a second predetermined thickness.
  • the substrate layer includes a substrate, a silicon nitride layer, and a silicon oxide layer.
  • Layer where:
  • the silicon nitride layer is over the substrate; the silicon oxide layer is on a side of the silicon nitride layer that faces away from the substrate.
  • the second photoresist layer is completely grayed After removing the second photoresist layer, the method further includes:
  • a gate is formed on a side of the oxide layer that faces away from the semiconductor layer.
  • the first predetermined thickness is 1-3 micrometers.
  • the incorporation of the high concentration dopant ions in the first specific region of the semiconductor layer includes:
  • a first concentration region in the semiconductor layer is doped with a high concentration of dopant ions by ion implantation.
  • Incorporating low concentration dopant ions in the second specific region of the semiconductor layer includes:
  • a second specific region in the semiconductor layer is doped with a low concentration of dopant ions by ion implantation.
  • High concentration dopant ions include high concentration P-type dopant ions or high concentration N-type dopant ions.
  • Low concentration dopant ions include low concentration P-type dopant ions or low concentration N-type dopant ions.
  • a second aspect of the embodiments of the present invention provides a low temperature polysilicon thin film transistor, the low temperature polysilicon thin film transistor comprising:
  • the base layer forming a semiconductor layer and a low temperature polysilicon layer on the same surface
  • the first specific region in the semiconductor layer is doped with a high concentration of dopant ions
  • a second specific region in the semiconductor layer incorporates a low concentration of dopant ions.
  • a semiconductor layer and a low-temperature polysilicon layer are formed on the same surface of the base layer; an oxide layer is formed on a side of the semiconductor layer facing away from the base layer, and an oxide layer is formed on a side of the low-temperature polysilicon layer facing away from the base layer; Forming a plurality of first photoresist layers of a first predetermined thickness; providing a first cobalt layer corresponding thereto on each of the first photoresist layers, a vertical projection of the first cobalt layer corresponding to the first cobalt layer a vertical projection of a photoresist layer is superposed; a first specific region in the semiconductor layer is doped with a high concentration of dopant ions; a first cobalt layer is removed, and a plurality of first photoresist layers are partially ashed, to obtain a plurality of a second photoresist layer of a second predetermined thickness, wherein the second predetermined thickness is smaller than the first predetermined thickness; and a
  • the first photoresist layer and the first cobalt layer are used to dope the high concentration dopant ions in the first specific region, and the second photoresist layer and the second cobalt layer are mixed in the second specific region.
  • the concentration is doped with ions, and the second photoresist layer is partially ashed to the first photoresist layer.
  • only one mask is used to realize source-drain heavy doping and LDD light doping. Compared with the prior art, the mask is used twice, the number of masks is reduced, and the production time is reduced.
  • FIG. 1 is a schematic flow chart of a method for manufacturing a low temperature polysilicon thin film transistor according to an embodiment of the present invention
  • FIG. 2 is a schematic flow chart of another method for manufacturing a low temperature polysilicon thin film transistor according to an embodiment of the present invention
  • step S101 in a method for fabricating a low temperature polysilicon thin film transistor according to an embodiment of the present invention
  • step S102 is a cross-sectional view corresponding to step S102 in a method for fabricating a low temperature polysilicon thin film transistor according to an embodiment of the present invention
  • step S103 is a cross-sectional view corresponding to step S103 in a method for fabricating a low temperature polysilicon thin film transistor according to an embodiment of the present invention
  • step S104 is a cross-sectional view corresponding to step S104 in a method for fabricating a low temperature polysilicon thin film transistor according to an embodiment of the present invention
  • step S105 is a cross-sectional view corresponding to step S105 in a method for fabricating a low temperature polysilicon thin film transistor according to an embodiment of the present invention
  • step S106 is a cross-sectional view corresponding to step S106 in a method for fabricating a low temperature polysilicon thin film transistor according to an embodiment of the present invention
  • step S107 is a cross-sectional view corresponding to step S107 in a method for fabricating a low temperature polysilicon thin film transistor according to an embodiment of the present invention.
  • step S108 is a cross-sectional view corresponding to step S108 in a method for fabricating a low temperature polysilicon thin film transistor according to an embodiment of the present invention
  • step S109 is a cross-sectional view corresponding to step S109 in a method for fabricating a low temperature polysilicon thin film transistor according to an embodiment of the present invention
  • FIG. 12 is a cross-sectional view showing a base layer in a method for manufacturing a low-temperature polysilicon thin film transistor according to an embodiment of the present invention
  • FIG. 13 is a cross-sectional view corresponding to step S210 in a method for fabricating a low temperature polysilicon thin film transistor according to an embodiment of the present invention
  • FIG. 14 is a parameter test diagram of a low temperature polysilicon thin film transistor disclosed in the present invention.
  • FIG. 1 is a schematic flow chart of a method for fabricating a low temperature polysilicon thin film transistor according to an embodiment of the present invention, and a method for fabricating a low temperature polysilicon thin film transistor as described in FIG.
  • the semiconductor layer 102 and the low temperature polysilicon layer 103 are located on the same side of the base layer 101, and the semiconductor layer 102 is used for doping dopant ions to form source and drain doped regions, low temperature polysilicon layer.
  • 103 may be formed by irradiating amorphous silicon with an excimer laser, and the base layer 101 may be a glass substrate and a silicide, and the silicide may function as an insulator.
  • the base layer comprises a substrate, a silicon nitride layer and a silicon oxide layer, wherein:
  • a silicon nitride layer is over the substrate; a silicon oxide layer is on a side of the silicon nitride layer that faces away from the substrate.
  • FIG. 12 is a schematic cross-sectional view of a base layer in a method for manufacturing a low-temperature polysilicon thin film transistor according to an embodiment of the present invention.
  • the base layer 101 includes a substrate 1011.
  • the oxide layer 104 is disposed on the semiconductor layer 102 and the low temperature polysilicon layer 103 for isolating the gate and the source and drain.
  • the thickness of the oxide layer is generally several nanometers to several tens. Between nanometers.
  • the first photoresist layer 105 is disposed on the oxide layer 104.
  • the formation of the first photoresist layer 105 may include: photoresist coating, pre-baking, alignment, and exposure. After the steps of post-baking, developing, hardening, etc., the first photoresist layer can be precisely formed on the oxide layer by a lithography machine.
  • the thickness of the first photoresist layer 105 can be preset, and the first photoresist layer 105 can be There are a plurality of areas in which the area covered by the first photoresist layer 105 is protected, and the area not covered by the first photoresist layer 105 is processed. After the first photoresist layer 105 is formed, automatic photo inspection (ADI) is performed after development.
  • ADI automatic photo inspection
  • the first predetermined thickness is 1-3 micrometers.
  • the thickness of the first photoresist layer may be set to 1 to 3 micrometers by a lithography machine.
  • a first cobalt layer corresponding to the first photoresist layer is disposed on each of the first photoresist layers, and a vertical projection of the first cobalt layer coincides with a vertical projection of the first photoresist layer corresponding to the first cobalt layer.
  • a first cobalt layer 106 corresponding to the first photoresist layer 105 is disposed on the first photoresist layer 105, and the first cobalt layer 106 is used for blocking dopant ion lithography in the subsequent step. Glue to avoid doping the undoped areas.
  • the vertical projection of the first cobalt layer 106 coincides with the vertical projection of the first photoresist layer 105 corresponding to the first cobalt layer 106 for the specific region where the dopant ions can be doped into the semiconductor layer 102 for subsequent doping.
  • the first specific region 1021 in the semiconductor layer 102 is doped with a high concentration of dopant ions, and can be doped in the first specific region 1021 in the semiconductor layer 102 by ion implantation.
  • the first specific region 1021 is a source/drain region
  • the doping in the first specific region 1021 is source-drain region (SD) doping
  • the first specific region 1021 is not covered by the first photoresist layer 105.
  • the size of the first specific area 1021 can be controlled by the position and size of the first photoresist layer 105.
  • the high concentration is generally greater than 1 x 10 17 /cm 3 .
  • step S105 incorporating the high concentration dopant ions in the first specific region in the semiconductor layer comprises:
  • the first specific region in the semiconductor layer is doped with a high concentration of dopant ions by ion implantation.
  • the first specific region 1021 in the semiconductor layer 102 may be doped with a high concentration of dopant ions by an ion implanter.
  • the high concentration dopant ions include a low concentration P-type dopant ion or a low concentration.
  • the N-type dopant ions, the P-type dopant ions may include ions in the fifth main group such as nitrogen, phosphorus, and arsenic, and the N-type dopant ions may include ions in the third main group such as boron, aluminum, or gallium.
  • the first cobalt layer is removed, and the plurality of first photoresist layers are partially ashed to obtain a plurality of second photoresist layers of a second predetermined thickness.
  • the second predetermined thickness is less than the first predetermined thickness.
  • the plurality of first photoresist layers 105 are partially ashed, so that part of the first photoresist layer 105 is peeled off to form a plurality of layers.
  • the second photoresist layer 107 of the second predetermined thickness is obtained by partially peeling off the first photoresist layer 105 to obtain the second photoresist layer 107.
  • the second predetermined thickness of the second photoresist layer 107 is smaller than the first light.
  • the first thickness of the resist layer 105 can be partially etched by an etching machine, and the etching method can be plasma etching (PE), reactive ion etching (Reactive Ion Etch, RIE).
  • IBE Ion Beam Etch
  • ICP Inductive Coupled Plasma
  • ADI automatic photo inspection
  • the gas used in the ashing process may be oxygen (O 2 ), or ozone (O 3 ), or fluorinated carbon (CF 4 ) or nitrogen oxide (N 2 O or NO), for a plurality of first photoresist layers.
  • the process parameters used in the partial ashing process can be preset.
  • step S106 performing a partial ashing process on the plurality of first photoresist layers to obtain a plurality of second photoresist layers of the second predetermined thickness may include:
  • the plurality of first photoresist layers are partially etched by a plasma etching machine to obtain a plurality of second photoresist layers of a second predetermined thickness; wherein the etching power of the plasma etching machine is set to 1000 to 1600 W, The etching time is 250 to 350 s.
  • the processing parameters of the plasma etching machine can be set.
  • the etching power of the plasma etching machine is set to 1000-1600 W, and the etching time is 250-350 s.
  • the processing parameters of the plasma etching machine are some of the parameters in the partial ashing process parameters.
  • a second cobalt layer corresponding to the second photoresist layer is disposed on each of the second photoresist layers, and the vertical projection of the second cobalt layer coincides with the vertical projection of the second photoresist layer corresponding to the second cobalt layer.
  • a second cobalt layer 108 corresponding to the second photoresist layer 107 is disposed on the second photoresist layer 107, and the second cobalt layer 108 is used for blocking dopant ion lithography in the subsequent step. Glue to avoid doping the undoped areas.
  • the vertical projection of the second cobalt layer 108 coincides with the vertical projection of the second photoresist layer 107 corresponding to the second cobalt layer 108 for the purpose of incorporating dopant ions into a specific region of the semiconductor layer 102 for subsequent doping.
  • the second specific region 1022 in the semiconductor layer 102 is doped with a low concentration of dopant ions, which may be doped by the second specific region 1022 in the semiconductor layer 102 by ion implantation.
  • the low concentration doping ions, the second specific region 1022 is connected to the first specific region 1021, the low doping type drain (LDD) in the second specific region 1022 is doped, and the second specific region 1022 is the second photoresist layer 107.
  • the area of the second specific area 1022 can be controlled by the position and size of the second photoresist layer 107.
  • the low concentration is generally less than 1 x 10 14 /cm 3 .
  • step S108 incorporating the low concentration dopant ions in the second specific region in the semiconductor layer comprises:
  • a second specific region in the semiconductor layer is doped with a low concentration of dopant ions by ion implantation.
  • the second specific region 1022 in the semiconductor layer 102 may be doped with low concentration dopant ions by an ion implanter.
  • the low concentration dopant ions include low concentration P-type dopant ions or low concentration.
  • the N-type dopant ions, the P-type dopant ions may include ions in the fifth main group such as nitrogen, phosphorus, and arsenic, and the N-type dopant ions may include ions in the third main group such as boron, aluminum, or gallium.
  • the second cobalt layer 108 is removed, and the second photoresist layer 107 is completely ashed, so that the second photoresist layer 107 is completely stripped.
  • the gas used in the ashing process may be oxygen (O 2 ), or ozone (O 3 ), or carbon fluoride (CF 4 ) or nitrogen oxide (N 2 O or NO), and completely ash the second photoresist layer.
  • the process parameters used in the processing can be preset.
  • the first photoresist layer 105 is formed first, and the first specific region 1021 in the semiconductor layer 102 is doped with a high concentration of doping ions to complete the SD doping.
  • a photoresist layer 105 is completely stripped, and the first photoresist layer 105 is partially ashed by step S106 to change the first photoresist layer 105 into the second photoresist layer 107, and then the second photoresist layer 107 is utilized.
  • the second specific region 1022 in the semiconductor layer 102 is doped with a low concentration of doped ions to complete the LDD doping.
  • FIG. 2 is a schematic flow chart of another method for fabricating a low temperature polysilicon thin film transistor according to an embodiment of the present invention, and the method for manufacturing the low temperature polysilicon thin film transistor as described in FIG.
  • a first cobalt layer corresponding to the first photoresist layer is disposed on each of the first photoresist layers, and a vertical projection of the first cobalt layer coincides with a vertical projection of the first photoresist layer corresponding to the first cobalt layer.
  • a second cobalt layer corresponding to the second photoresist layer is disposed on each of the second photoresist layers, and the vertical projection of the second cobalt layer coincides with the vertical projection of the second photoresist layer corresponding to the second cobalt layer.
  • a gate electrode 109 is formed on a side of the surface of the oxide layer 104 facing away from the semiconductor layer 102, and a gate electrode may be formed on the side of the oxide layer 104 away from the semiconductor layer 102 by sputtering. 109.
  • the first photoresist layer 105 is first formed, and the first specificity in the semiconductor layer 102 is formed.
  • the region 1021 is doped with a high concentration of doping ions to complete the SD doping.
  • the first photoresist layer 105 is not completely stripped, and the first photoresist layer 105 is partially ashed by the step S106.
  • the first photoresist layer 105 is changed to the second photoresist layer 107, and then the second specific region 1022 in the semiconductor layer 102 is doped with the low concentration dopant ions by the second photoresist layer 107 to complete the LDD doping.
  • FIG. 14 is a parameter test diagram of a low temperature polysilicon thin film transistor disclosed in the present invention, and FIG. 14 is a parameter test diagram obtained by measuring some parameters of a low temperature polysilicon thin film transistor fabricated by the method of FIG. 1 or FIG.
  • FIG. 14 measures some parameters of nine sets of low-temperature polysilicon thin film transistors having different ashing process parameters, wherein PR thickness is the thickness of the second photoresist layer 107 in micrometers ( ⁇ m), and Ashing Power is ashing etching. Power in watts (W), Ashing Time is the ashing etch time in seconds (s), P-doping Dosage is the P-type light doping concentration in units of 1/cm 3 (cm -3 ), CD Data is Critical Dimension (CD).
  • Array Yield is the yield of low-temperature polysilicon thin film transistors. The higher the yield, the better the ashing process parameters.

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Abstract

一种低温多晶硅薄膜晶体管及其制造方法。该方法包括：在基底层（101）同一表面形成半导体层（102）和低温多晶硅层（103）；在半导体层（102）背离基底层（101）的一侧形成氧化层（104），在低温多晶硅层（103）背离基底层（101）的一侧形成氧化层（104）；在氧化层（104）上形成多个第一预设厚度的第一光阻层（105）；在每个第一光阻层（105）上设置一个与之对应的第一钴层（106）；在半导体层（102）中的第一特定区域（1021）掺入高浓度掺杂离子；移除第一钴层（106），对多个第一光阻层（105）进行部分灰化处理，得到多个第二预设厚度的第二光阻层（107）；在每个第二光阻层（107）上设置一个与之对应的第二钴层（108）；在半导体层（102）中的第二特定区域（1022）掺入低浓度掺杂离子；移除第二钴层（108），对第二光阻层（107）进行完全灰化处理，去除第二光阻层（107），可以减少光罩次数，降低生产时间。

Description

一种低温多晶硅薄膜晶体管及其制造方法
本发明要求2015年07月29日递交的申请号为201510456334.4、发明名称为“一种低温多晶硅薄膜晶体管及其制造方法”的在先申请优先权，上述在先申请的内容以引入的方式并入本文本中。
技术领域
本发明涉及晶体管制造领域，尤其涉及一种低温多晶硅薄膜晶体管及其制造方法。
背景技术
低温多晶硅技术(Low Temperature Ploy-silicon，LTPS)采用多晶硅制造薄膜晶体管(Thin Film Transistor，TFT)，与采用非晶硅制作的TFT相比，LTPS制作的TFT有更高的电子迁移率。LTPS制作的TFT可应用于使液晶显示器具有更高的分辨率和低能耗。因此，低温多晶硅技术得到了广泛地应用和研究。
低掺杂型漏极(Lightly Doped Drain，LDD)，用于在薄膜晶体管(Thin Film Transistor，TFT)沟道中靠近漏极的地方设置一个低掺杂区，可以减少漏极附近的峰值电场，从而抑制热电子效应。目前使用LTPS技术在LDD制程时，在源漏极重掺杂和LDD轻掺杂时需要用到两次光罩，成本较高，生产时间较长。
发明内容
本发明提供一种低温多晶硅薄膜晶体管及其制造方法，可以解决使用LTPS技术在LDD制程时，在源漏极重掺杂和LDD轻掺杂时需要用到两次光罩的问题。
本发明实施例第一方面提供一种低温多晶硅薄膜晶体管制造方法，包括：
在基底层同一表面形成半导体层和低温多晶硅层；
在所述半导体层背离所述基底层的一侧形成氧化层，在所述低温多晶硅层背离所述基底层的一侧形成所述氧化层；
在所述氧化层上形成多个第一预设厚度的第一光阻层；
在每个第一光阻层上设置一个与之对应的第一钴层，所述第一钴层的垂直投影与所述第一钴层对应的第一光阻层的垂直投影重合；
在所述半导体层中的第一特定区域掺入高浓度掺杂离子；
移除所述第一钴层，对所述多个第一光阻层进行部分灰化处理，得到多个第二预设厚度的第二光阻层，所述第二预设厚度小于所述第一预设厚度；
在每个第二光阻层上设置一个与之对应的第二钴层，所述第二钴层的垂直投影与所述第二钴层对应的第二光阻层的垂直投影重合；
在所述半导体层中的第二特定区域掺入低浓度掺杂离子；
移除所述第二钴层，对所述第二光阻层进行完全灰化处理，去除所述第二光阻层。
在本发明实施例第一方面的第一种可能的实现方式中，所述对所述多个第一光阻层进行部分灰化处理，得到多个第二预设厚度的第二光阻层，包括：
利用等离子刻蚀机对所述多个第一光阻层进行部分刻蚀，得到多个第二预设厚度的第二光阻层；其中，设定所述等离子刻蚀机的刻蚀功率为1000～1600W，刻蚀时间为250～350s。
结合本发明实施例第一方面的第一种可能的实现方式，在本发明实施例第一方面的第二种可能的实现方式中，所述基底层包括衬底、氮化硅层和氧化硅层，其中：
所述氮化硅层位于所述衬底之上；所述氧化硅层位于所述氮化硅层背离所述衬底的一侧。
结合本发明实施例第一方面的第二种可能的实现方式，在本发明实施例第一方面的第三种可能的实现方式中，所述对所述第二光阻层进行完全灰化处理，去除所述第二光阻层之后，所述方法还包括：
在所述氧化层上背离所述半导体层的一侧形成栅极。
结合本发明实施例第一方面的第三种可能的实现方式，在本发明实施例第一方面的第四种可能的实现方式中，所述第一预设厚度为1～3微米。
结合本发明实施例第一方面或第一方面的第一种至第四种中的任一种可能的实现方式，在本发明实施例第一方面的第五种可能的实现方式中，所述在 所述半导体层中的第一特定区域掺入高浓度掺杂离子包括：
采用离子注入方式在所述半导体层中的第一特定区域掺入高浓度掺杂离子。
结合本发明实施例第一方面或第一方面的第一种至第四种中的任一种可能的实现方式，在本发明实施例第一方面的第六种可能的实现方式中，所述在所述半导体层中的第二特定区域掺入低浓度掺杂离子包括：
采用离子注入方式在所述半导体层中的第二特定区域掺入低浓度掺杂离子。
结合本发明实施例第一方面或第一方面的第一种至第四种中的任一种可能的实现方式，在本发明实施例第一方面的第七种可能的实现方式中，所述高浓度掺杂离子包括高浓度P型掺杂离子或高浓度N型掺杂离子。
结合本发明实施例第一方面或第一方面的第一种至第四种中的任一种可能的实现方式，在本发明实施例第一方面的第八种可能的实现方式中，所述低浓度掺杂离子包括低浓度P型掺杂离子或低浓度N型掺杂离子。
本发明实施例第二方面提供一种低温多晶硅薄膜晶体管，所述低温多晶硅薄膜晶体管包括：
基底层，所述基底层同一表面形成半导体层和低温多晶硅层；
所述半导体层背离所述基底层的一侧形成氧化层，所述低温多晶硅层背离所述基底层的一侧形成所述氧化层；
所述半导体层中的第一特定区域掺入高浓度掺杂离子；
所述半导体层中的第二特定区域掺入低浓度掺杂离子。
本发明实施例中，在基底层同一表面形成半导体层和低温多晶硅层；在半导体层背离基底层的一侧形成氧化层，在低温多晶硅层背离基底层的一侧形成氧化层；在氧化层上形成多个第一预设厚度的第一光阻层；在每个第一光阻层上设置一个与之对应的第一钴层，第一钴层的垂直投影与第一钴层对应的第一光阻层的垂直投影重合；在半导体层中的第一特定区域掺入高浓度掺杂离子；移除第一钴层，对多个第一光阻层进行部分灰化处理，得到多个第二预设厚度的第二光阻层，第二预设厚度小于第一预设厚度；在每个第二光阻层上设置一个与之对应的第二钴层，第二钴层的垂直投影与第二钴层对应的第二光阻层的 垂直投影重合；在半导体层中的第二特定区域掺入低浓度掺杂离子；移除第二钴层，对第二光阻层进行完全灰化处理，去除第二光阻层。在本发明实施例中，利用第一光阻层和第一钴层在第一特定区域掺入高浓度掺杂离子，利用第二光阻层和第二钴层在第二特定区域掺入低浓度掺杂离子，并且第二光阻层是对第一光阻层进行部分灰化处理得到的，本发明实施例中只用到了一次光罩实现了源漏极重掺杂和LDD轻掺杂，相比现有技术中要用到两次光罩，减少光罩次数，降低生产时间。
附图说明
为了更清楚地说明本发明实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本发明实施例公开的一种低温多晶硅薄膜晶体管制造方法的流程示意图；
图2为本发明实施例公开的另一种低温多晶硅薄膜晶体管制造方法的流程示意图；
图3为本发明实施例公开的一种低温多晶硅薄膜晶体管制造方法中步骤S101对应的剖面示意图；
图4为本发明实施例公开的一种低温多晶硅薄膜晶体管制造方法中步骤S102对应的剖面示意图；
图5为本发明实施例公开的一种低温多晶硅薄膜晶体管制造方法中步骤S103对应的剖面示意图；
图6为本发明实施例公开的一种低温多晶硅薄膜晶体管制造方法中步骤S104对应的剖面示意图；
图7为本发明实施例公开的一种低温多晶硅薄膜晶体管制造方法中步骤S105对应的剖面示意图；
图8为本发明实施例公开的一种低温多晶硅薄膜晶体管制造方法中步骤S106对应的剖面示意图；
图9为本发明实施例公开的一种低温多晶硅薄膜晶体管制造方法中步骤S107对应的剖面示意图；
图10为本发明实施例公开的一种低温多晶硅薄膜晶体管制造方法中步骤S108对应的剖面示意图；
图11为本发明实施例公开的一种低温多晶硅薄膜晶体管制造方法中步骤S109对应的剖面示意图；
图12为本发明实施例公开的一种低温多晶硅薄膜晶体管制造方法中基底层的剖面示意图；
图13为本发明实施例公开的一种低温多晶硅薄膜晶体管制造方法中步骤S210对应的剖面示意图；
图14为本发明实施公开的一种低温多晶硅薄膜晶体管的参数测试图。
具体实施方式
下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本发明一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。
请参阅图1，图1为本发明实施例公开的一种低温多晶硅薄膜晶体管制造方法的流程示意图，如图1所描述的低温多晶硅薄膜晶体管制造方法，包括步骤：
S101，在基底层同一表面形成半导体层和低温多晶硅层。
本发明实施例中，如图3所示，半导体层102和低温多晶硅层103位于基底层101的同一侧，半导体层102用于掺入掺杂离子以形成源漏极掺杂区，低温多晶硅层103可以通过准分子激光照射非晶硅形成，基底层101可以为玻璃基板和硅化物，硅化物可以起绝缘作用。
可选的，步骤S101中，基底层包括衬底、氮化硅层和氧化硅层，其中：
氮化硅层位于衬底之上；氧化硅层位于氮化硅层背离衬底的一侧。
本发明实施例中，如图12所示，图12为本发明实施例公开的一种低温多晶硅薄膜晶体管制造方法中基底层的剖面示意图，基底层101包括衬底1011、 氮化硅层1012和氧化硅层1013，其中，衬底1011可以为玻璃基板，氮化硅层1012可以为SiNx，氧化硅层1013可以为SiOx。
S102，在半导体层背离基底层的一侧形成氧化层，在低温多晶硅层背离基底层的一侧形成氧化层。
本发明实施例中，如图4所示，氧化层104设置在半导体层102和低温多晶硅层103之上，用于隔绝栅极和源漏极，氧化层的厚度一般为几个纳米到几十个纳米之间。
S103，在氧化层上形成多个第一预设厚度的第一光阻层。
本发明实施例中，如图5所示，第一光阻层105设置在氧化层104之上，第一光阻层105的形成可以包括：光刻胶涂覆、前烘、对准、曝光、后烘、显影、坚膜等步骤，第一光阻层可以通过光刻机精确控制形成在氧化层之上，第一光阻层105的厚度可以预先设定，第一光阻层105可以有多个，以使第一光阻层105覆盖的区域受到保护，对第一光阻层105不覆盖的区域进行处理。第一光阻层105形成后，进行显影后自动光检查(ADI)。
可选的，步骤S103中，第一预设厚度为1～3微米。
本发明实施例中，可以通过光刻机设置第一光阻层的厚度为1～3微米。
S104，在每个第一光阻层上设置一个与之对应的第一钴层，第一钴层的垂直投影与第一钴层对应的第一光阻层的垂直投影重合。
本发明实施例中，如图6所示，在第一光阻层105上设置一个与之对应的第一钴层106，第一钴层106用于后续步骤中阻挡掺杂离子透过光刻胶，避免对非掺杂区域进行掺杂。第一钴层106的垂直投影与第一钴层106对应的第一光阻层105的垂直投影重合是为了后续掺杂时能够将掺杂离子掺入半导体层102的特定区域。
S105，在半导体层中的第一特定区域掺入高浓度掺杂离子。
本发明实施例中，如图7所示，在半导体层102中的第一特定区域1021掺入高浓度掺杂离子，可以通过离子注入的方式在半导体层102中的第一特定区域1021掺入高浓度掺杂离子，第一特定区域1021为源漏区，第一特定区域1021内的掺杂为源漏区(SD)掺杂，第一特定区域1021为第一光阻层105不覆盖的区域，可以通过第一光阻层105的位置和大小控制第一特定区域1021 的大小。高浓度一般为大于1×1017/cm3。
可选的，步骤S105中，在半导体层中的第一特定区域掺入高浓度掺杂离子包括：
采用离子注入方式在半导体层中的第一特定区域掺入高浓度掺杂离子。
本发明实施例中，可以通过离子注入机在半导体层102中的第一特定区域1021掺入高浓度掺杂离子，可选的，高浓度掺杂离子包括低浓度P型掺杂离子或低浓度N型掺杂离子，P型掺杂离子可以包括氮、磷、砷等第五主族内的离子，N型掺杂离子可以包括硼、铝、镓等第三主族内的离子。
S106，移除第一钴层，对多个第一光阻层进行部分灰化处理，得到多个第二预设厚度的第二光阻层，第二预设厚度小于第一预设厚度。
本发明实施例中，如图8所示，移除第一钴层106之后，对多个第一光阻层105进行部分灰化处理，以使部分第一光阻层105剥离，形成多个第二预设厚度的第二光阻层107，由于对第一光阻层105进行了部分剥离得到第二光阻层107，第二光阻层107的第二预设厚度要小于第一光阻层105的第一厚度，可以通过刻蚀机对第一光阻层进行部分刻蚀，刻蚀方式可以为等离子刻蚀(Plasma Etching，PE)、反应离子刻蚀(Reactive Ion Etch，RIE)、离子束刻蚀(Ion Beam Etch，IBE)、电感耦合等离子刻蚀(Inductive Coupled Plasma，ICP)等。第二光阻层107形成后，进行显影后自动光检查(ADI)。灰化制程中使用的气体可以是氧气(O2)，或者臭氧(O3)，或者氟化碳(CF4)或者氧化氮(N2O或者NO)，对多个第一光阻层进行部分灰化处理时用到的制程参数可以进行预先设定。
可选的，步骤S106中，对多个第一光阻层进行部分灰化处理，得到多个第二预设厚度的第二光阻层，可以包括：
利用等离子刻蚀机对多个第一光阻层进行部分刻蚀，得到多个第二预设厚度的第二光阻层；其中，设定等离子刻蚀机的刻蚀功率为1000～1600W，刻蚀时间为250～350s。
本发明实施例中，可以设定等离子刻蚀机的加工参数，例如，设定等离子刻蚀机的刻蚀功率为1000～1600W，刻蚀时间为250～350s。等离子刻蚀机的加工参数为部分灰化制程参数中的部分参数。
S107，在每个第二光阻层上设置一个与之对应的第二钴层，第二钴层的垂直投影与第二钴层对应的第二光阻层的垂直投影重合。
本发明实施例中，如图9所示，在第二光阻层107上设置一个与之对应的第二钴层108，第二钴层108用于后续步骤中阻挡掺杂离子透过光刻胶，避免对非掺杂区域进行掺杂。第二钴层108的垂直投影与第二钴层108对应的第二光阻层107的垂直投影重合是为了后续掺杂时能够将掺杂离子掺入半导体层102的特定区域。
S108，在半导体层中的第二特定区域掺入低浓度掺杂离子。
本发明实施例中，如图10所示，在半导体层102中的第二特定区域1022掺入低浓度掺杂离子，可以通过离子注入的方式在半导体层102中的第二特定区域1022掺入低浓度掺杂离子，第二特定区域1022与第一特定区域1021连接，第二特定区域1022内的低掺杂型漏极(LDD)掺杂，第二特定区域1022为第二光阻层107不覆盖的区域，可以通过第二光阻层107的位置和大小控制第二特定区域1022的大小。低浓度一般为小于1×1014/cm3。
可选的，步骤S108中，在半导体层中的第二特定区域掺入低浓度掺杂离子包括：
采用离子注入方式在半导体层中的第二特定区域掺入低浓度掺杂离子。
本发明实施例中，可以通过离子注入机在半导体层102中的第二特定区域1022掺入低浓度掺杂离子，可选的，低浓度掺杂离子包括低浓度P型掺杂离子或低浓度N型掺杂离子，P型掺杂离子可以包括氮、磷、砷等第五主族内的离子，N型掺杂离子可以包括硼、铝、镓等第三主族内的离子。
S109，移除第二钴层，对第二光阻层进行完全灰化处理，去除第二光阻层。
本发明实施例中，如图11所示，当LDD掺杂完成后，移除第二钴层108，对第二光阻层107进行完全灰化处理，以使第二光阻层107完全剥离。灰化制程中使用的气体可以是氧气(O2)，或者臭氧(O3)，或者氟化碳(CF4)或者氧化氮(N2O或者NO)，对第二光阻层进行完全灰化处理时用到的制程参数可以进行预先设定。
本发明实施例中，先形成第一光阻层105，在半导体层102中的第一特定区域1021掺入高浓度掺杂离子，完成SD掺杂，当SD掺杂完成后，无需对第 一光阻层105进行完全剥离，通过步骤S106对第一光阻层105进行部分灰化处理，以使第一光阻层105变为第二光阻层107，然后利用第二光阻层107在半导体层102中的第二特定区域1022掺入低浓度掺杂离子，完成LDD掺杂，整个制作过程中，涂覆了一次光刻胶之后，完成了两道掺杂制程(SD掺杂和LDD掺杂)，整个掺杂过程，仅使用了一次光罩，与现有技术相比，可以减少光罩次数，降低生产时间。
请参阅图2，图2为本发明实施例公开的另一种低温多晶硅薄膜晶体管制造方法的流程示意图，如图2所描述的低温多晶硅薄膜晶体管制造方法，包括步骤：
S201，在基底层同一表面形成半导体层和低温多晶硅层。
S202，在半导体层背离基底层的一侧形成氧化层，在低温多晶硅层背离基底层的一侧形成氧化层。
S203，在氧化层上形成多个第一预设厚度的第一光阻层。
S204，在每个第一光阻层上设置一个与之对应的第一钴层，第一钴层的垂直投影与第一钴层对应的第一光阻层的垂直投影重合。
S205，在半导体层中的第一特定区域掺入高浓度掺杂离子。
S206，移除第一钴层，对多个第一光阻层进行部分灰化处理，得到多个第二预设厚度的第二光阻层，第二预设厚度小于第一预设厚度。
S207，在每个第二光阻层上设置一个与之对应的第二钴层，第二钴层的垂直投影与第二钴层对应的第二光阻层的垂直投影重合。
S208，在半导体层中的第二特定区域掺入低浓度掺杂离子。
S209，移除第二钴层，对第二光阻层进行完全灰化处理，去除第二光阻层。
S210，在氧化层上背离半导体层的一侧形成栅极。
本发明实施例中，如图13所示，在氧化层104表面背离半导体层102的一侧形成栅极109，可以通过溅射的方式在氧化,104上背离半导体层102的一侧形成栅极109。
本发明实施例中的步骤S201～步骤S209可以参见图1所示的步骤S101～步骤S109，本发明实施例不再赘述。
本发明实施例中，先形成第一光阻层105，在半导体层102中的第一特定 区域1021掺入高浓度掺杂离子，完成SD掺杂，当SD掺杂完成后，无需对第一光阻层105进行完全剥离，通过步骤S106对第一光阻层105进行部分灰化处理，以使第一光阻层105变为第二光阻层107，然后利用第二光阻层107在半导体层102中的第二特定区域1022掺入低浓度掺杂离子，完成LDD掺杂，整个制作过程中，涂覆了一次光刻胶之后，完成了两道掺杂制程(SD掺杂和LDD掺杂)，整个掺杂过程，仅使用了一次光罩，与现有技术相比，可以减少光罩次数，降低生产时间。
图14为本发明实施公开的一种低温多晶硅薄膜晶体管的参数测试图，图14为对采用图1或图2的方法制作的低温多晶硅薄膜晶体管的一些参数进行测量得到的参数测试图。
图14中对九组不同灰化制程参数的低温多晶硅薄膜晶体管的一些参数进行测量，其中，PR thickness为第二光阻层107的厚度，单位为微米(μm)，Ashing Power为灰化刻蚀功率，单位为瓦特(W)，Ashing Time为灰化刻蚀时间，单位为秒(s)，P-doping Dosage为P型轻掺杂浓度，单位为1/立方厘米(cm-3)，CD data为关键尺寸(Critical Dimension，CD)，Array Yield为低温多晶硅薄膜晶体管的良率，良率越高表明灰化制程参数较优。
从图14可以看出，当P型轻掺杂浓度为2.5×1013cm-3、灰化刻蚀功率1000W，灰化刻蚀时间300s时，良率为93.8％(第四组，L4)；当P型轻掺杂浓度为2.5×1013cm-3、灰化刻蚀功率1600W，灰化刻蚀时间250s时，良率为92.0％(第六组，L6)；当P型轻掺杂浓度为1.5×1013cm-3、灰化刻蚀功率1600W，灰化刻蚀时间300s时，良率为94.6％(第9组，L9)，从图14可知，第四组、第六组和第九组的制程参数较优，采用图1或图2的方法制作的低温多晶硅薄膜晶体管的良率较高。
以上所揭露的仅为本发明一种较佳实施例而已，当然不能以此来限定本发明之权利范围，本领域普通技术人员可以理解实现上述实施例的全部或部分流程，并依本发明权利要求所作的等同变化，仍属于发明所涵盖的范围。

Claims (16)

  1. 一种低温多晶硅薄膜晶体管制造方法，其中，包括：
    在基底层同一表面形成半导体层和低温多晶硅层；
    在所述半导体层背离所述基底层的一侧形成氧化层，在所述低温多晶硅层背离所述基底层的一侧形成所述氧化层；
    在所述氧化层上形成多个第一预设厚度的第一光阻层；
    在每个第一光阻层上设置一个与之对应的第一钴层，所述第一钴层的垂直投影与所述第一钴层对应的第一光阻层的垂直投影重合；
    在所述半导体层中的第一特定区域掺入高浓度掺杂离子；
    移除所述第一钴层，对所述多个第一光阻层进行部分灰化处理，得到多个第二预设厚度的第二光阻层，所述第二预设厚度小于所述第一预设厚度；
    在每个第二光阻层上设置一个与之对应的第二钴层，所述第二钴层的垂直投影与所述第二钴层对应的第二光阻层的垂直投影重合；
    在所述半导体层中的第二特定区域掺入低浓度掺杂离子；
    移除所述第二钴层，对所述第二光阻层进行完全灰化处理，去除所述第二光阻层。
  2. 根据权利要求1所述的方法，其中，所述对所述多个第一光阻层进行部分灰化处理，得到多个第二预设厚度的第二光阻层，包括：
    利用等离子刻蚀机对所述多个第一光阻层进行部分刻蚀，得到多个第二预设厚度的第二光阻层；其中，设定所述等离子刻蚀机的刻蚀功率为1000～1600W，刻蚀时间为250～350s。
  3. 根据权利要求2所述的方法，其中，所述基底层包括衬底、氮化硅层和氧化硅层，其中：
    所述氮化硅层位于所述衬底之上；所述氧化硅层位于所述氮化硅层背离所述衬底的一侧。
  4. 根据权利要求3所述的方法，其中，所述对所述第二光阻层进行完全灰化处理，去除所述第二光阻层之后，所述方法还包括：
    在所述氧化层上背离所述半导体层的一侧形成栅极。
  5. 根据权利要求4所述的方法，其中，所述第一预设厚度为1～3微米。
  6. 根据权利要求1所述的方法，其中，所述在所述半导体层中的第一特定区域掺入高浓度掺杂离子包括：
    采用离子注入方式在所述半导体层中的第一特定区域掺入高浓度掺杂离子；其中，所述高浓度掺杂离子包括高浓度P型掺杂离子或高浓度N型掺杂离子。
  7. 根据权利要求2所述的方法，其中，所述在所述半导体层中的第一特定区域掺入高浓度掺杂离子包括：
    采用离子注入方式在所述半导体层中的第一特定区域掺入高浓度掺杂离子；其中，所述高浓度掺杂离子包括高浓度P型掺杂离子或高浓度N型掺杂离子。
  8. 根据权利要求3所述的方法，其中，所述在所述半导体层中的第一特定区域掺入高浓度掺杂离子包括：
    采用离子注入方式在所述半导体层中的第一特定区域掺入高浓度掺杂离子；其中，所述高浓度掺杂离子包括高浓度P型掺杂离子或高浓度N型掺杂离子。
  9. 根据权利要求4所述的方法，其中，所述在所述半导体层中的第一特定区域掺入高浓度掺杂离子包括：
    采用离子注入方式在所述半导体层中的第一特定区域掺入高浓度掺杂离子；其中，所述高浓度掺杂离子包括高浓度P型掺杂离子或高浓度N型掺杂离子。
  10. 根据权利要求5所述的方法，其中，所述在所述半导体层中的第一特定区域掺入高浓度掺杂离子包括：
    采用离子注入方式在所述半导体层中的第一特定区域掺入高浓度掺杂离子；其中，所述高浓度掺杂离子包括高浓度P型掺杂离子或高浓度N型掺杂离子。
  11. 根据权利要求1所述的方法，其中，所述在所述半导体层中的第二特定区域掺入低浓度掺杂离子包括：
    采用离子注入方式在所述半导体层中的第二特定区域掺入低浓度掺杂离子；其中，所述低浓度掺杂离子包括低浓度P型掺杂离子或低浓度N型掺杂离子。
  12. 根据权利要求2所述的方法，其中，所述在所述半导体层中的第二特定区域掺入低浓度掺杂离子包括：
    采用离子注入方式在所述半导体层中的第二特定区域掺入低浓度掺杂离子；其中，所述低浓度掺杂离子包括低浓度P型掺杂离子或低浓度N型掺杂离子。
  13. 根据权利要求3所述的方法，其中，所述在所述半导体层中的第二特定区域掺入低浓度掺杂离子包括：
    采用离子注入方式在所述半导体层中的第二特定区域掺入低浓度掺杂离子；其中，所述低浓度掺杂离子包括低浓度P型掺杂离子或低浓度N型掺杂离子。
  14. 根据权利要求4所述的方法，其中，所述在所述半导体层中的第二特定区域掺入低浓度掺杂离子包括：
    采用离子注入方式在所述半导体层中的第二特定区域掺入低浓度掺杂离子；其中，所述低浓度掺杂离子包括低浓度P型掺杂离子或低浓度N型掺杂 离子。
  15. 根据权利要求5所述的方法，其中，所述在所述半导体层中的第二特定区域掺入低浓度掺杂离子包括：
    采用离子注入方式在所述半导体层中的第二特定区域掺入低浓度掺杂离子；其中，所述低浓度掺杂离子包括低浓度P型掺杂离子或低浓度N型掺杂离子。
  16. 一种低温多晶硅薄膜晶体管，其中，所述低温多晶硅薄膜晶体管包括：
    基底层，所述基底层同一表面形成半导体层和低温多晶硅层；
    所述半导体层背离所述基底层的一侧形成氧化层，所述低温多晶硅层背离所述基底层的一侧形成所述氧化层；
    所述半导体层中的第一特定区域掺入高浓度掺杂离子；
    所述半导体层中的第二特定区域掺入低浓度掺杂离子。
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CN106898613A (zh) * 2017-02-07 2017-06-27 武汉华星光电技术有限公司 Tft基板及其制作方法
CN106876334B (zh) * 2017-03-10 2019-11-29 京东方科技集团股份有限公司 阵列基板的制造方法及阵列基板
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