CN106876334B - 阵列基板的制造方法及阵列基板 - Google Patents
阵列基板的制造方法及阵列基板 Download PDFInfo
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- 239000000758 substrate Substances 0.000 title claims abstract description 67
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 23
- 239000004065 semiconductor Substances 0.000 claims abstract description 70
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 62
- 229920005591 polysilicon Polymers 0.000 claims abstract description 59
- 238000000034 method Methods 0.000 claims abstract description 48
- 238000000059 patterning Methods 0.000 claims abstract description 11
- 239000010410 layer Substances 0.000 claims description 303
- 239000011241 protective layer Substances 0.000 claims description 46
- 238000002161 passivation Methods 0.000 claims description 39
- 239000011229 interlayer Substances 0.000 claims description 27
- 238000005530 etching Methods 0.000 claims description 22
- 238000009413 insulation Methods 0.000 claims description 16
- 238000001312 dry etching Methods 0.000 claims description 15
- 238000001039 wet etching Methods 0.000 claims description 12
- XLOMVQKBTHCTTD-UHFFFAOYSA-N Zinc monoxide Chemical compound [Zn]=O XLOMVQKBTHCTTD-UHFFFAOYSA-N 0.000 claims description 10
- 229910052738 indium Inorganic materials 0.000 claims description 10
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 claims description 10
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 claims description 5
- AJNVQOSZGJRYEI-UHFFFAOYSA-N digallium;oxygen(2-) Chemical compound [O-2].[O-2].[O-2].[Ga+3].[Ga+3] AJNVQOSZGJRYEI-UHFFFAOYSA-N 0.000 claims description 5
- 229910052733 gallium Inorganic materials 0.000 claims description 5
- 229910001195 gallium oxide Inorganic materials 0.000 claims description 5
- 239000011787 zinc oxide Substances 0.000 claims description 5
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 4
- 239000000463 material Substances 0.000 claims description 4
- 230000003647 oxidation Effects 0.000 claims description 4
- 238000007254 oxidation reaction Methods 0.000 claims description 4
- 229910052710 silicon Inorganic materials 0.000 claims description 4
- 239000010703 silicon Substances 0.000 claims description 4
- TYHJXGDMRRJCRY-UHFFFAOYSA-N zinc indium(3+) oxygen(2-) tin(4+) Chemical compound [O-2].[Zn+2].[Sn+4].[In+3] TYHJXGDMRRJCRY-UHFFFAOYSA-N 0.000 claims description 4
- 230000015572 biosynthetic process Effects 0.000 claims description 3
- 150000001875 compounds Chemical class 0.000 claims description 3
- -1 aluminium zinc oxygen Chemical compound 0.000 claims 2
- 239000010408 film Substances 0.000 description 18
- 229920002120 photoresistant polymer Polymers 0.000 description 17
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 7
- 238000010586 diagram Methods 0.000 description 5
- 239000011521 glass Substances 0.000 description 5
- 239000000377 silicon dioxide Substances 0.000 description 4
- JYMITAMFTJDTAE-UHFFFAOYSA-N aluminum zinc oxygen(2-) Chemical compound [O-2].[Al+3].[Zn+2] JYMITAMFTJDTAE-UHFFFAOYSA-N 0.000 description 3
- 229910052681 coesite Inorganic materials 0.000 description 3
- 239000004020 conductor Substances 0.000 description 3
- 229910052906 cristobalite Inorganic materials 0.000 description 3
- 229910052682 stishovite Inorganic materials 0.000 description 3
- 229910052905 tridymite Inorganic materials 0.000 description 3
- 229910021417 amorphous silicon Inorganic materials 0.000 description 2
- 238000004380 ashing Methods 0.000 description 2
- 239000013078 crystal Substances 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- 239000007789 gas Substances 0.000 description 2
- 230000002093 peripheral effect Effects 0.000 description 2
- 238000001259 photo etching Methods 0.000 description 2
- 239000010409 thin film Substances 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- WGCXSIWGFOQDEG-UHFFFAOYSA-N [Zn].[Sn].[In] Chemical compound [Zn].[Sn].[In] WGCXSIWGFOQDEG-UHFFFAOYSA-N 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 230000003139 buffering effect Effects 0.000 description 1
- 238000007715 excimer laser crystallization Methods 0.000 description 1
- 238000005224 laser annealing Methods 0.000 description 1
- 239000004973 liquid crystal related substance Substances 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 238000002834 transmittance Methods 0.000 description 1
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Abstract
本发明提供一种阵列基板的制造方法及阵列基板,该阵列基板的制造方法包括:在衬底上形成多晶硅层,其中,所述衬底包括第一区域和第二区域;在所述多晶硅层上形成氧化物半导体层;以及利用一次构图工艺,在所述第一区域形成第一有源层,在所述第二区域形成第二有源层,其中,所述第一有源层由所述多晶硅层构成,所述第二有源层由所述氧化物半导体层及所述多晶硅层构成。
Description
技术领域
本发明涉及阵列基板的制造方法及阵列基板。
背景技术
在显示面板的TFT(Thin Film Transistor:薄膜晶体管)阵列基板的制造中,LTPO(Low Temperature Polycrystalline Oxide:低温多晶氧化物)工艺是一种同时利用低温多晶硅(LTPS)工艺和氧化物(Oxide)工艺制造TFT阵列基板的新技术。
发明内容
本发明鉴于上述情况而完成,其目的在于提供一种能够简化工序且提高生产量的阵列基板的制造方法及阵列基板。
本发明提供一种阵列基板的制造方法,包括以下步骤:在衬底上形成多晶硅层,其中,所述衬底包括第一区域和第二区域;在所述多晶硅层上形成氧化物半导体层;以及利用一次构图工艺,在所述第一区域形成第一有源层,在所述第二区域形成第二有源层,其中,所述第一有源层由所述多晶硅层构成,所述第二有源层由所述氧化物半导体层及所述多晶硅层构成。
例如,执行所述构图工艺的步骤包括以下步骤:第一步骤,利用一个掩模,在所述第一区域形成第一保护层,在所述第二区域形成第二保护层,其中,所述第一保护层的厚度小于所述第二保护层的厚度;第二步骤,对所述第一区域和所述第二区域中未被所述第一保护层和所述第二保护层覆盖的所述氧化物半导体层和所述多晶硅层执行蚀刻;第三步骤,去除所述第一保护层的全部和所述第二保护层的一部分,暴露所述第一保护层下方的所述氧化物半导体层;第四步骤,对所暴露出的所述氧化物半导体层执行蚀刻,形成由所述多晶硅层构成的所述第一有源层;以及第五步骤,去除所述第二保护层的剩余部分,形成由所述氧化物半导体层及所述多晶硅层构成所述第二有源层。
例如,还包括:在执行所述构图工艺之前,在所述氧化物半导体层上形成钝化层的步骤,所述构图工艺包括:第一步骤,利用一个掩模,在所述第一区域形成第一保护层,在所述第二区域形成第二保护层,其中,所述第一保护层的厚度小于所述第二保护层的厚度;第二步骤,对所述第一区域和所述第二区域中未被所述第一保护层和所述第二保护层覆盖的所述钝化层、所述氧化物半导体层和所述多晶硅层执行蚀刻;第三步骤,去除所述第一保护层的全部和所述第二保护层的一部分,暴露所述第一保护层下方的所述钝化层;第四步骤,对所暴露出的所述钝化层及其下方的所述氧化物半导体层执行蚀刻,形成由所述多晶硅层构成的所述第一有源层;以及第五步骤,去除所述第二保护层的剩余部分,形成由所述氧化物半导体层及所述多晶硅层构成所述第二有源层,并保留所述第二有源层上的所述钝化层。
例如,所述第二步骤和所述第四步骤中的蚀刻为干法蚀刻。
例如,在所述第二步骤中,按照湿法蚀刻、干法蚀刻的顺序,依次去除所述第一区域和所述第二区域中未被所述第一保护层和所述第二保护层覆盖的所述氧化物半导体层和所述多晶硅层,在所述第四步骤中,通过湿法蚀刻来去除所暴露出的所述氧化物半导体层。
例如,在所述第二步骤中,按照干法蚀刻、湿法蚀刻、干法蚀刻的顺序,依次去除所述第一区域和所述第二区域中未被所述第一保护层和所述第二保护层覆盖的所述钝化层、所述氧化物半导体层和所述多晶硅层。
例如,在所述第四步骤中,通过干法蚀刻、湿法蚀刻,依次去除所暴露出的所述钝化层及其下方的所述氧化物半导体层。
例如,所述氧化物半导体层的材料包括铟镓锌氧化物、铟镓氧化物、铟锡锌氧化物和铝锌氧化物中的至少一种。
例如,还包括以下步骤:形成栅绝缘层;形成所述第一区域的第一栅极和所述第二区域的第二栅极;形成层间绝缘层;以及形成所述第一区域的第一源极和第一漏极、所述第二区域的第二源极和第二漏极,所述第一源极和第一漏极分别通过贯穿所述层间绝缘层和所述栅绝缘层的过孔与所述第一有源层连接,所述第二源极和第二漏极分别通过贯穿所述层间绝缘层、所述栅绝缘层和所述钝化层的过孔与所述第二有源层连接。
本发明还提供一种阵列基板,包括:衬底、栅极绝缘层、栅极、源极和漏极,其中,所述衬底具有第一区域和第二区域,在所述第一区域设置有第一有源层,该第一有源层由多晶硅层构成,在所述第二区域设置有第二有源层,该第二有源层由多晶硅层和形成在该多晶硅层上的氧化物半导体层构成,在同一层设置所述第一有源层中的多晶硅层和所述第二有源层中的多晶硅层。
例如,在所述第二有源层上方还设置有钝化层。
例如,所述氧化物半导体层的材料包括铟镓锌氧化物、铟镓氧化物、铟锡锌氧化物和铝锌氧化物中的至少一种。
例如,该阵列基板还包括层间绝缘层,所述栅极包括第一栅极和第二栅极,所述源极包括第一源极和第二源极,所述漏极包括第一漏极和第二漏极,所述栅绝缘层设置在所述第一有源层和所述钝化层上方,所述栅极设置在所述栅绝缘层上方,所述层间绝缘层设置在所述栅极上方,所述第一源极、第一漏极、第二源极、第二漏极形成在所述层间绝缘层上方,其中,所述第一源极和第一漏极分别通过贯穿所述层间绝缘层和所述栅绝缘层的过孔与所述第一有源层连接,所述第二源极和第二漏极分别通过贯穿所述层间绝缘层、所述栅绝缘层和所述钝化层的过孔与所述第二有源层连接。
在本发明中,由于通过一次构图工艺就能够同时形成LTPS TFT的有源层和OxideTFT的有源层,因此能够简化工序,提高生产量。另外,由于Oxide TFT阵列基板的有源层包括氧化物半导体层及其下方的多晶硅层,因此对于紫外线非常敏感的氧化物半导体层来说,在氧化物半导体层下方形成多晶硅层有利于阻断紫外线。
附图说明
为了更清楚地说明本发明实施例的技术方案,下面将对实施例的附图进行简单说明,显而易见地,下面描述中的附图仅仅涉及本发明的一些实施例,而非对本发明的限制。
图1是示出了现有技术中的LTPO TFT阵列基板的结构示意图。
图2是本发明的实施例所提供的LTPO TFT阵列基板的结构示意图。
图3~图10是根据本发明实施例示出了图2中的TFT阵列基板的有源层的制造工序的工序图。
图11是根据本发明实施例示出了图2中的TFT阵列基板的有源层的制造工序的流程图。
图12是根据本发明实施例示出了图11中的步骤S205的具体内容的流程图。
符号说明:
1、11-LTPS TFT;2、22-Oxide TFT;10、110-基板;20-缓冲层;30、130-多晶硅层(低温多晶硅层);40、140-氧化物半导体层;50-钝化层;201、1201-栅极绝缘层;102、202、1102、1202-栅极;203、1203-层间绝缘层;104、204、1104、1204-源极;105、205、1105、1205-漏极。
具体实施方式
为使本发明实施例的目的、技术方案和优点更加清楚,下面将结合本发明实施例的附图,对本发明实施例的技术方案进行清楚、完整地描述。显然,所描述的实施例是本发明的一部分实施例,而不是全部的实施例。基于所描述的本发明的实施例,本领域普通技术人员在无需创造性劳动的前提下所获得的所有其他实施例,都属于本发明保护的范围。
除非另外定义,本公开使用的技术术语或者科学术语应当为本发明所属领域内具有一般技能的人士所理解的通常意义。本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性,而只是用来区分不同的结构部分。本公开中使用的“包括”、“包含”、“具备”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同,而不排除其他元件或者物件。“上”、“下”等用语仅用于表示相对位置关系,当被描述对象的绝对位置改变后,则该相对位置关系也可能相应地改变。
图1是示出了现有技术中的LTPO TFT阵列基板的结构示意图。如图1所示,所谓LTPO工艺是,通过LTPS工艺形成作为周边电路区域的LTPS TFT 11,通过Oxide工艺形成作为像素区域的Oxide TFT 22。
如图1所示,LTPS TFT 11具备玻璃基板110、形成在玻璃基板110上的多晶硅层130、覆盖多晶硅层130的栅极绝缘层1201、形成在栅极绝缘层1201上的栅极1102、覆盖栅极1102的层间绝缘层1203、贯穿层间绝缘层1203和栅极绝缘层1201的过孔而与多晶硅层130连接的源极1104及漏极1105。利用LTPS工艺形成的TFT具有电子迁移率高的优点,因此能够提高周边电路的集成度,并且通过利用复用(MUX)方式,减少了数据驱动集成电路(IC),因此能够减少成本。如图1所示,Oxide TFT 22具备玻璃基板110、形成在玻璃基板110上的栅极绝缘层1201、形成在栅极绝缘层1201上的栅极1202、覆盖栅极1202的层间绝缘层1203、形成在层间绝缘层1203上的氧化物半导体层140、与氧化物半导体层140连接的源极1204和漏极1205。Oxide工艺形成的TFT由于漏电流非常低,因此可实现低频驱动。通过LTPO工艺形成的TFT恰好能够结合这两者的优点,但是现有的LTPO工艺需要执行现有的LTPS工艺和现有的Oxide工艺,因此即便最小限度地减少光刻工序中的掩模,也至少需要两个掩模,分别用于形成LTPS TFT的有源层和Oxide TFT的有源层。因此,所使用的掩模数量较多,工序变得复杂。
本发明为了解决上述技术问题而完成,以下结合具体实施例进行详细说明。
图2是本发明的实施例所提供的LTPO TFT阵列基板的结构示意图。如图2所示,本发明的LTPO TFT阵列基板包括LTPS TFT 1和与该LTPS TFT 1相邻的Oxide TFT 2。在本实施例中,LTPS TFT 1和Oxide TFT 2都采用顶栅型结构,但是本发明并不限于此。
如图2所示,LTPS TFT 1具备基板10、形成在基板10上的缓冲层20(基板10和缓冲层20相当于衬底)、形成在缓冲层20上的多晶硅层30(第一有源层)、覆盖多晶硅层30的栅极绝缘层201、形成在栅极绝缘层201上的栅极102(第一栅极)、覆盖栅极102的层间绝缘层203、贯穿层间绝缘层203和栅极绝缘层201的过孔而与多晶硅层30连接的源极104(第一源极)及漏极105(第一漏极)。
另外,如图2所示,Oxide TFT 2具备基板10、形成在基板10上的缓冲层20、形成在缓冲层20上的多晶硅层30、形成在多晶硅层30上的氧化物半导体层40(多晶硅层30和氧化物半导体层40相当于第二有源层)、形成在氧化物半导体层40上的钝化层50、覆盖钝化层50的栅极绝缘层201、形成在栅极绝缘层201上的栅极202(第二栅极)、覆盖栅极202的层间绝缘层203、、贯穿层间绝缘层203和栅极绝缘层201的过孔而与氧化物半导体层40连接的源极204(第二源极)及漏极205(第二漏极)。
在此,基板10例如是玻璃基板。此外,栅极绝缘层201例如可以由二氧化硅或氮化硅构成。层间绝缘层203例如也可以由二氧化硅或氮化硅构成。缓冲层20可采用现有技术形成,在此不进行详细说明。
图3~图10是根据本发明实施例示出了图2中的LTPO TFT阵列基板的有源层的制造工序的各阶段的示意图。图11是根据本发明实施例示出了图2中的LTPO TFT阵列基板的有源层的制造工序的流程图。图12是根据本发明实施例示出了图11中的步骤S205的具体内容的流程图。以下,结合图3~图10,具体说明LTPO TFT阵列基板的有源层的制造方法。
如图3所示,在图11所示的步骤S201中,优选在基板10上沉积缓冲层20,在缓冲层20上沉积非晶硅(a-Si)层,然后通过ELA(Excimer Laser Annealing:准分子激光晶化)工序形成多晶硅(P-Si)层30。
如图4所示,在图11所示的步骤S102中,在多晶硅层30上沉积氧化物半导体层40。该氧化物半导体层40可以包括IGZO(铟镓锌氧化物)、IGO(铟镓氧化物)、ITZO(铟锡锌氧化物)或AlZnO(铝锌氧化物)中的至少一种。
如图5所示,在图11所示的步骤S203中,在氧化物半导体层40上沉积钝化层50。该钝化层50可由SiO2构成。该钝化层50对氧化物半导体层40特性的影响比较大,因此工序条件很重要。通常,在氧化物半导体层上形成的钝化层由多层形成,氧化物半导体层紧上面的钝化层大多情况下通过低温工序形成(例如,170~250℃)。在本发明中,为了确保氧化物半导体层40的特性,优选形成钝化层,在低温下,例如在170~250℃下,沉积厚度约为0.1μm的SiO2层。这是为了确保氧化物半导体层40的特性,并在后续的工序中保护氧化物半导体层40。
如图6所示,在图11所示的步骤S104中,在一次光刻工序内,利用一个掩模,在LTPSTFT 1区域形成第一光刻胶层108(基于halftone),在Oxide TFT 2区域形成第二光刻胶层208(基于full tone)。如图6所示,第一光刻胶层(第一保护层)108和第二光刻胶层(第二保护层)208局部覆盖钝化层50,且厚度不同。例如,第一光刻胶层108的厚度可以是0.5μm,第二光刻胶层208的厚度可以是2μm。这里,通过在掩模的不同位置处设置不同的透光率来实现上述光刻工序。
由于在同一光刻工序内利用一个掩模就能够同时形成第一光刻胶层108和第二光刻胶层208,因此对于现有工厂来说,能够简化光刻工序,提高生产量,从而提高收益,对于新设工厂来说,能够有效降低投资成本。
如图10所示,在图11所示的步骤S105中,通过执行蚀刻,形成:LTPS TFT 1的有源层、即多晶硅层30(第一有缘层);和Oxide TFT 2的有源层、即多晶硅层30和氧化物半导体层40(第二有缘层)。在此,保留Oxide TFT 2中的氧化物半导体层40上方的钝化层50,以便在后续的工序中保护氧化物半导体层40,且确保氧化物半导体层40的特性。
此外,步骤S105中的蚀刻具体可按照图12中的流程来进行。
首先,如图7所示,在图12所示的步骤S1051中,对未被第一光刻胶层108和第二光刻胶层208覆盖的钝化层50、氧化物半导体层40和多晶硅层30执行蚀刻。如果对氧化物半导体层40的蚀刻选择湿法蚀刻,则可按照干法蚀刻、湿法蚀刻、干法蚀刻的顺序,依次对未被第一光刻胶层108和第二光刻胶层208覆盖的钝化层50、氧化物半导体层40和多晶硅层30执行蚀刻。这样执行蚀刻的缺点是工序比较复杂。优选地,可将对氧化物半导体层40的蚀刻选择为干法蚀刻,在一个工序内,通过变更蚀刻气体,依次对未被第一光刻胶层108和第二光刻胶层208覆盖的钝化层50、氧化物半导体层40和多晶硅层30执行蚀刻。蚀刻完成后的结构如图7所示。
然后,如图8所示,在图12所示的步骤S1052中,通过灰化(Ashing),去除第一光刻胶层108的全部和第二光刻胶层208的一部分。此时,第二光刻胶层208的剩余部分的厚度例如可以是1μm。
然后,如图9所示,在图12所示的步骤S1053中,对去除第一光刻胶层108的全部后暴露出的钝化层50及其下方的氧化物半导体层40执行蚀刻,形成LTPS TFT 1的有源层、即多晶硅层30。在该步骤中,也可以如步骤S1051那样,如果对氧化物半导体层40的蚀刻选择湿法蚀刻,则可按照干法蚀刻、湿法蚀刻的顺序,依次去除暴露出的钝化层50及其下方的氧化物半导体层40。但是,也可在一个工序内,利用干法蚀刻,通过变更蚀刻气体,依次去除暴露出的钝化层50及其下方的氧化物半导体层40,这样可以简化工序。
最后,如图10所示,在图12所示的步骤S1054中,通过剥离(strip),去除第二光刻胶层208的剩余部分,由此形成Oxide TFT 2的有源层,保留该Oxide TFT 2的有源层上方的钝化层50。也就是说,Oxide TFT 2的有源层由多晶硅层30和氧化物半导体层40构成。
通过以上各步骤,完成LTPO TFT的有源层形成工序。如上所述,在本实施方式中,利用一次构图工艺(利用一个掩模,执行一次光刻工序),形成了LTPS TFT 1的有缘层和Oxide TFT 2的有源层。
形成有源层之后,形成LTPS TFT 1及Oxide TFT 2的栅极绝缘层、栅极、层间绝缘层、源极和漏极的工序与现有技术相同,因此在此不进行详细说明。关于Oxide TFT 2中的接触区域,由于在对层间绝缘层203执行蚀刻时,该接触区域会被导体化,因此接触上不存在问题。
形成LTPS TFT 1的源极及漏极、Oxide TFT 2的源极和漏极以后,可根据LCD(Liquid Crystal Display)或OLED(Organic Light Emitting Diode)的需要形成所需的各层,在此不进行详细说明。
根据本发明的LTPO TFT阵列基板的制造方法,由于在同一光刻工序内仅使用一个掩模即可形成LTPS TFT的有缘层和Oxide TFT的有源层,因此能够简化工序,提高生产量,从而提高收益率。
另外,在本发明的LTPO TFT阵列基板中,Oxide TFT 2的有源层由氧化物半导体层40及其下方的多晶硅层30构成。由于氧化物半导体层对紫外线非常敏感,因此在氧化物半导体层40下方形成多晶硅层30有利于阻断紫外线。
有以下几点需要说明:(1)本发明的实施例的附图仅涉及与本发明的实施例相关的结构,其他结构可参考通常设计;(2)附图中各层厚度和形状不反映真实比例,其目的仅仅是示意性说明本发明的实施例。
以上所述仅是本发明的示范性实施方式,并非用于限制本发明的保护范围,本发明的保护范围由所附的权利要求书确定。
Claims (13)
1.一种阵列基板的制造方法,包括以下步骤:
在衬底上形成多晶硅层,其中,所述衬底包括第一区域和第二区域;
在所述多晶硅层上形成氧化物半导体层;以及
利用一次构图工艺,在所述第一区域形成第一有源层,在所述第二区域形成第二有源层,其中,所述第一有源层由所述多晶硅层构成,所述第二有源层由所述氧化物半导体层及所述多晶硅层构成。
2.根据权利要求1所述的阵列基板的制造方法,其中,
所述构图工艺包括:
第一步骤,利用一个掩模,在所述第一区域形成第一保护层,在所述第二区域形成第二保护层,其中,所述第一保护层的厚度小于所述第二保护层的厚度;
第二步骤,对所述第一区域和所述第二区域中未被所述第一保护层和所述第二保护层覆盖的所述氧化物半导体层和所述多晶硅层执行蚀刻;
第三步骤,去除所述第一保护层的全部和所述第二保护层的一部分,暴露所述第一保护层下方的所述氧化物半导体层;
第四步骤,对所暴露出的所述氧化物半导体层执行蚀刻,形成由所述多晶硅层构成的所述第一有源层;以及
第五步骤,去除所述第二保护层的剩余部分,形成由所述氧化物半导体层及所述多晶硅层构成所述第二有源层。
3.根据权利要求1所述的阵列基板的制造方法,还包括:
在执行所述构图工艺之前,在所述氧化物半导体层上形成钝化层的步骤,
所述构图工艺包括:
第一步骤,利用一个掩模,在所述第一区域形成第一保护层,在所述第二区域形成第二保护层,其中,所述第一保护层的厚度小于所述第二保护层的厚度;
第二步骤,对所述第一区域和所述第二区域中未被所述第一保护层和所述第二保护层覆盖的所述钝化层、所述氧化物半导体层和所述多晶硅层执行蚀刻;
第三步骤,去除所述第一保护层的全部和所述第二保护层的一部分,暴露所述第一保护层下方的所述钝化层;
第四步骤,对所暴露出的所述钝化层及其下方的所述氧化物半导体层执行蚀刻,形成由所述多晶硅层构成的所述第一有源层;以及
第五步骤,去除所述第二保护层的剩余部分,形成由所述氧化物半导体层及所述多晶硅层构成所述第二有源层,并保留所述第二有源层上方的所述钝化层。
4.根据权利要求2或3所述的阵列基板的制造方法,其中,
所述第二步骤和所述第四步骤中的蚀刻为干法蚀刻。
5.根据权利要求2所述的阵列基板的制造方法,其中,
在所述第二步骤中,按照湿法蚀刻、干法蚀刻的顺序,依次去除所述第一区域和所述第二区域中未被所述第一保护层和所述第二保护层覆盖的所述氧化物半导体层和所述多晶硅层,
在所述第四步骤中,通过湿法蚀刻来去除所暴露出的所述氧化物半导体层。
6.根据权利要求3所述的阵列基板的制造方法,其中,
在所述第二步骤中,按照干法蚀刻、湿法蚀刻、干法蚀刻的顺序,依次去除所述第一区域和所述第二区域中未被所述第一保护层和所述第二保护层覆盖的所述钝化层、所述氧化物半导体层和所述多晶硅层。
7.根据权利要求3所述的阵列基板的制造方法,其中,
在所述第四步骤中,通过干法蚀刻、湿法蚀刻,依次去除所暴露出的所述钝化层及其下方的所述氧化物半导体层。
8.根据权利要求1~3中任一项所述的阵列基板的制造方法,其中,
所述氧化物半导体层的材料包括铟镓锌氧化物、铟镓氧化物、铟锡锌氧化物和铝锌氧化物中的至少一种。
9.根据权利要求3所述的阵列基板的制造方法,还包括以下步骤:
形成栅绝缘层;
形成所述第一区域的第一栅极和所述第二区域的第二栅极;
形成层间绝缘层;以及
形成所述第一区域的第一源极和第一漏极、所述第二区域的第二源极和第二漏极,
所述第一源极和第一漏极分别通过贯穿所述层间绝缘层和所述栅绝缘层的过孔与所述第一有源层连接,
所述第二源极和第二漏极分别通过贯穿所述层间绝缘层、所述栅绝缘层和所述钝化层的过孔与所述第二有源层连接。
10.一种阵列基板,包括:
衬底、栅绝缘层、栅极、源极和漏极,
其中,所述衬底具有第一区域和第二区域,
在所述第一区域设置有第一有源层,该第一有源层由多晶硅层构成,
在所述第二区域设置有第二有源层,该第二有源层由多晶硅层和形成在该多晶硅层上的氧化物半导体层构成,其中与所述第二有源层连接的源极和漏极与所述氧化物半导体层连接,
在同一层设置有所述第一有源层中的多晶硅层和所述第二有源层中的多晶硅层。
11.根据权利要求10所述的阵列基板,其中,
在所述第二有源层上方还设置有钝化层。
12.根据权利要求10或11所述的阵列基板,其中,
所述氧化物半导体层的材料包括铟镓锌氧化物、铟镓氧化物、铟锡锌氧化物和铝锌氧化物中的至少一种。
13.根据权利要求11所述的阵列基板,其中,
该阵列基板还包括层间绝缘层,
所述栅极包括第一栅极和第二栅极,所述源极包括第一源极和第二源极,所述漏极包括第一漏极和第二漏极,
所述栅绝缘层设置在所述第一有源层和所述钝化层上方,
所述栅极设置在所述栅绝缘层上方,
所述层间绝缘层设置在所述栅极上方,
所述第一源极、第一漏极、第二源极、第二漏极形成在所述层间绝缘层上方,
其中,所述第一源极和第一漏极分别通过贯穿所述层间绝缘层和所述栅绝缘层的过孔与所述第一有源层连接,
所述第二源极和第二漏极分别通过贯穿所述层间绝缘层、所述栅绝缘层和所述钝化层的过孔与所述第二有源层连接。
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