CN105118807B - 一种低温多晶硅薄膜晶体管及其制造方法 - Google Patents

一种低温多晶硅薄膜晶体管及其制造方法 Download PDF

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CN105118807B
CN105118807B CN201510456334.4A CN201510456334A CN105118807B CN 105118807 B CN105118807 B CN 105118807B CN 201510456334 A CN201510456334 A CN 201510456334A CN 105118807 B CN105118807 B CN 105118807B
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CN105118807A (zh
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卢昶鸣
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Wuhan China Star Optoelectronics Technology Co Ltd
TCL Huaxing Photoelectric Technology Co Ltd
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Shenzhen China Star Optoelectronics Technology Co Ltd
Wuhan China Star Optoelectronics Technology Co Ltd
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Priority to PCT/CN2015/088415 priority patent/WO2017016023A1/zh
Priority to US14/909,092 priority patent/US9842935B2/en
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Abstract

本发明提供一种低温多晶硅薄膜晶体管及其制造方法。该方法包括：在基底层同一表面形成半导体层和低温多晶硅层；在半导体层背离基底层的一侧形成氧化层，在低温多晶硅层背离基底层的一侧形成氧化层；在氧化层上形成多个第一预设厚度的第一光阻层；在每个第一光阻层上设置一个与之对应的第一钴层；在半导体层中的第一特定区域掺入高浓度掺杂离子；移除第一钴层，对多个第一光阻层进行部分灰化处理，得到多个第二预设厚度的第二光阻层；在每个第二光阻层上设置一个与之对应的第二钴层；在半导体层中的第二特定区域掺入低浓度掺杂离子；移除第二钴层，对第二光阻层进行完全灰化处理，去除第二光阻层。实施本发明，可以减少光罩次数，降低生产时间。

Description

一种低温多晶硅薄膜晶体管及其制造方法
技术领域
本发明涉及晶体管制造领域，尤其涉及一种低温多晶硅薄膜晶体管及其制造方法。
背景技术
低温多晶硅技术(Low Temperature Ploy-silicon，LTPS)采用多晶硅制造薄膜晶体管(Thin Film Transistor，TFT)，与采用非晶硅制作的TFT相比，LTPS制作的TFT有更高的电子迁移率。LTPS制作的TFT可应用于使液晶显示器具有更高的分辨率和低能耗。因此，低温多晶硅技术得到了广泛地应用和研究。
低掺杂型漏极(Lightly Doped Drain，LDD)，用于在薄膜晶体管(Thin FilmTransistor，TFT)沟道中靠近漏极的地方设置一个低掺杂区，可以减少漏极附近的峰值电场，从而抑制热电子效应。目前使用LTPS技术在LDD制程时，在源漏极重掺杂和LDD轻掺杂时需要用到两次光罩，成本较高，生产时间较长。
发明内容
本发明提供一种低温多晶硅薄膜晶体管及其制造方法，可以解决使用LTPS技术在LDD制程时，在源漏极重掺杂和LDD轻掺杂时需要用到两次光罩的问题。
本发明实施例第一方面提供一种低温多晶硅薄膜晶体管制造方法，包括：
在基底层同一表面形成半导体层和低温多晶硅层；
在所述半导体层背离所述基底层的一侧形成氧化层，在所述低温多晶硅层背离所述基底层的一侧形成所述氧化层；
在所述氧化层上形成多个第一预设厚度的第一光阻层；
在每个第一光阻层上设置一个与之对应的第一钴层，所述第一钴层的垂直投影与所述第一钴层对应的第一光阻层的垂直投影重合；
在所述半导体层中的第一特定区域掺入高浓度掺杂离子；
移除所述第一钴层，对所述多个第一光阻层进行部分灰化处理，得到多个第二预设厚度的第二光阻层，所述第二预设厚度小于所述第一预设厚度；
在每个第二光阻层上设置一个与之对应的第二钴层，所述第二钴层的垂直投影与所述第二钴层对应的第二光阻层的垂直投影重合；
在所述半导体层中的第二特定区域掺入低浓度掺杂离子；
移除所述第二钴层，对所述第二光阻层进行完全灰化处理，去除所述第二光阻层。
在本发明实施例第一方面的第一种可能的实现方式中，所述对所述多个第一光阻层进行部分灰化处理，得到多个第二预设厚度的第二光阻层，包括：
利用等离子刻蚀机对所述多个第一光阻层进行部分刻蚀，得到多个第二预设厚度的第二光阻层；其中，设定所述等离子刻蚀机的刻蚀功率为1000～1600W，刻蚀时间为250～350s。
结合本发明实施例第一方面的第一种可能的实现方式，在本发明实施例第一方面的第二种可能的实现方式中，所述基底层包括衬底、氮化硅层和氧化硅层，其中：
所述氮化硅层位于所述衬底之上；所述氧化硅层位于所述氮化硅层背离所述衬底的一侧。
结合本发明实施例第一方面的第二种可能的实现方式，在本发明实施例第一方面的第三种可能的实现方式中，所述对所述第二光阻层进行完全灰化处理，去除所述第二光阻层之后，所述方法还包括：
在所述氧化层上背离所述半导体层的一侧形成栅极。
结合本发明实施例第一方面的第三种可能的实现方式，在本发明实施例第一方面的第四种可能的实现方式中，所述第一预设厚度为1～3微米。
结合本发明实施例第一方面或第一方面的第一种至第四种中的任一种可能的实现方式，在本发明实施例第一方面的第五种可能的实现方式中，所述在所述半导体层中的第一特定区域掺入高浓度掺杂离子包括：
采用离子注入方式在所述半导体层中的第一特定区域掺入高浓度掺杂离子。
结合本发明实施例第一方面或第一方面的第一种至第四种中的任一种可能的实现方式，在本发明实施例第一方面的第六种可能的实现方式中，所述在所述半导体层中的第二特定区域掺入低浓度掺杂离子包括：
采用离子注入方式在所述半导体层中的第二特定区域掺入低浓度掺杂离子。
结合本发明实施例第一方面或第一方面的第一种至第四种中的任一种可能的实现方式，在本发明实施例第一方面的第七种可能的实现方式中，所述高浓度掺杂离子包括高浓度P型掺杂离子或高浓度N型掺杂离子。
结合本发明实施例第一方面或第一方面的第一种至第四种中的任一种可能的实现方式，在本发明实施例第一方面的第八种可能的实现方式中，所述低浓度掺杂离子包括低浓度P型掺杂离子或低浓度N型掺杂离子。
本发明实施例第二方面提供一种低温多晶硅薄膜晶体管，所述低温多晶硅薄膜晶体管采用本发明实施例第一方面或第一方面的第一种至第八种中的任一种方法制得。
本发明实施例中，在基底层同一表面形成半导体层和低温多晶硅层；在半导体层背离基底层的一侧形成氧化层，在低温多晶硅层背离基底层的一侧形成氧化层；在氧化层上形成多个第一预设厚度的第一光阻层；在每个第一光阻层上设置一个与之对应的第一钴层，第一钴层的垂直投影与第一钴层对应的第一光阻层的垂直投影重合；在半导体层中的第一特定区域掺入高浓度掺杂离子；移除第一钴层，对多个第一光阻层进行部分灰化处理，得到多个第二预设厚度的第二光阻层，第二预设厚度小于第一预设厚度；在每个第二光阻层上设置一个与之对应的第二钴层，第二钴层的垂直投影与第二钴层对应的第二光阻层的垂直投影重合；在半导体层中的第二特定区域掺入低浓度掺杂离子；移除第二钴层，对第二光阻层进行完全灰化处理，去除第二光阻层。在本发明实施例中，利用第一光阻层和第一钴层在第一特定区域掺入高浓度掺杂离子，利用第二光阻层和第二钴层在第二特定区域掺入低浓度掺杂离子，并且第二光阻层是对第一光阻层进行部分灰化处理得到的，本发明实施例中只用到了一次光罩实现了源漏极重掺杂和LDD轻掺杂，相比现有技术中要用到两次光罩，减少光罩次数，降低生产时间。
附图说明
为了更清楚地说明本发明实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本发明实施例公开的一种低温多晶硅薄膜晶体管制造方法的流程示意图；
图2为本发明实施例公开的另一种低温多晶硅薄膜晶体管制造方法的流程示意图；
图3为本发明实施例公开的一种低温多晶硅薄膜晶体管制造方法中步骤S101对应的剖面示意图；
图4为本发明实施例公开的一种低温多晶硅薄膜晶体管制造方法中步骤S102对应的剖面示意图；
图5为本发明实施例公开的一种低温多晶硅薄膜晶体管制造方法中步骤S103对应的剖面示意图；
图6为本发明实施例公开的一种低温多晶硅薄膜晶体管制造方法中步骤S104对应的剖面示意图；
图7为本发明实施例公开的一种低温多晶硅薄膜晶体管制造方法中步骤S105对应的剖面示意图；
图8为本发明实施例公开的一种低温多晶硅薄膜晶体管制造方法中步骤S106对应的剖面示意图；
图9为本发明实施例公开的一种低温多晶硅薄膜晶体管制造方法中步骤S107对应的剖面示意图；
图10为本发明实施例公开的一种低温多晶硅薄膜晶体管制造方法中步骤S108对应的剖面示意图；
图11为本发明实施例公开的一种低温多晶硅薄膜晶体管制造方法中步骤S109对应的剖面示意图；
图12为本发明实施例公开的一种低温多晶硅薄膜晶体管制造方法中基底层的剖面示意图；
图13为本发明实施例公开的一种低温多晶硅薄膜晶体管制造方法中步骤S210对应的剖面示意图；
图14为本发明实施公开的一种低温多晶硅薄膜晶体管的参数测试图。
具体实施方式
下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本发明一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。
请参阅图1，图1为本发明实施例公开的一种低温多晶硅薄膜晶体管制造方法的流程示意图，如图1所描述的低温多晶硅薄膜晶体管制造方法，包括步骤：
S101，在基底层同一表面形成半导体层和低温多晶硅层。
本发明实施例中，如图3所示，半导体层102和低温多晶硅层103位于基底层101的同一侧，半导体层102用于掺入掺杂离子以形成源漏极掺杂区，低温多晶硅层103可以通过准分子激光照射非晶硅形成，基底层101可以为玻璃基板和硅化物，硅化物可以起绝缘作用。
可选的，步骤S101中，基底层包括衬底、氮化硅层和氧化硅层，其中：
氮化硅层位于衬底之上；氧化硅层位于氮化硅层背离衬底的一侧。
本发明实施例中，如图12所示，图12为本发明实施例公开的一种低温多晶硅薄膜晶体管制造方法中基底层的剖面示意图，基底层101包括衬底1011、氮化硅层1012和氧化硅层1013，其中，衬底1011可以为玻璃基板，氮化硅层1012可以为SiNx，氧化硅层1013可以为SiOx。
S102，在半导体层背离基底层的一侧形成氧化层，在低温多晶硅层背离基底层的一侧形成氧化层。
本发明实施例中，如图4所示，氧化层104设置在半导体层102和低温多晶硅层103之上，用于隔绝栅极和源漏极，氧化层的厚度一般为几个纳米到几十个纳米之间。
S103，在氧化层上形成多个第一预设厚度的第一光阻层。
本发明实施例中，如图5所示，第一光阻层105设置在氧化层104之上，第一光阻层105的形成可以包括：光刻胶涂覆、前烘、对准、曝光、后烘、显影、坚膜等步骤，第一光阻层可以通过光刻机精确控制形成在氧化层之上，第一光阻层105的厚度可以预先设定，第一光阻层105可以有多个，以使第一光阻层105覆盖的区域受到保护，对第一光阻层105不覆盖的区域进行处理。第一光阻层105形成后，进行显影后自动光检查(ADI)。
可选的，步骤S103中，第一预设厚度为1～3微米。
本发明实施例中，可以通过光刻机设置第一光阻层的厚度为1～3微米。
S104，在每个第一光阻层上设置一个与之对应的第一钴层，第一钴层的垂直投影与第一钴层对应的第一光阻层的垂直投影重合。
本发明实施例中，如图6所示，在第一光阻层105上设置一个与之对应的第一钴层106，第一钴层106用于后续步骤中阻挡掺杂离子透过光刻胶，避免对非掺杂区域进行掺杂。第一钴层106的垂直投影与第一钴层106对应的第一光阻层105的垂直投影重合是为了后续掺杂时能够将掺杂离子掺入半导体层102的特定区域。
S105，在半导体层中的第一特定区域掺入高浓度掺杂离子。
本发明实施例中，如图7所示，在半导体层102中的第一特定区域1021掺入高浓度掺杂离子，可以通过离子注入的方式在半导体层102中的第一特定区域1021掺入高浓度掺杂离子，第一特定区域1021为源漏区，第一特定区域1021内的掺杂为源漏区(SD)掺杂，第一特定区域1021为第一光阻层105不覆盖的区域，可以通过第一光阻层105的位置和大小控制第一特定区域1021的大小。高浓度一般为大于1×1017/cm3。
可选的，步骤S105中，在半导体层中的第一特定区域掺入高浓度掺杂离子包括：
采用离子注入方式在半导体层中的第一特定区域掺入高浓度掺杂离子。
本发明实施例中，可以通过离子注入机在半导体层102中的第一特定区域1021掺入高浓度掺杂离子，可选的，高浓度掺杂离子包括低浓度P型掺杂离子或低浓度N型掺杂离子，P型掺杂离子可以包括氮、磷、砷等第五主族内的离子，N型掺杂离子可以包括硼、铝、镓等第三主族内的离子。
S106，移除第一钴层，对多个第一光阻层进行部分灰化处理，得到多个第二预设厚度的第二光阻层，第二预设厚度小于第一预设厚度。
本发明实施例中，如图8所示，移除第一钴层106之后，对多个第一光阻层105进行部分灰化处理，以使部分第一光阻层105剥离，形成多个第二预设厚度的第二光阻层107，由于对第一光阻层105进行了部分剥离得到第二光阻层107，第二光阻层107的第二预设厚度要小于第一光阻层105的第一厚度，可以通过刻蚀机对第一光阻层进行部分刻蚀，刻蚀方式可以为等离子刻蚀(Plasma Etching，PE)、反应离子刻蚀(Reactive Ion Etch，RIE)、离子束刻蚀(Ion Beam Etch，IBE)、电感耦合等离子刻蚀(Inductive Coupled Plasma，ICP)等。第二光阻层107形成后，进行显影后自动光检查(ADI)。灰化制程中使用的气体可以是氧气(O2)，或者臭氧(O3)，或者氟化碳(CF4)或者氧化氮(N2O或者NO)，对多个第一光阻层进行部分灰化处理时用到的制程参数可以进行预先设定。
可选的，步骤S106中，对多个第一光阻层进行部分灰化处理，得到多个第二预设厚度的第二光阻层，可以包括：
利用等离子刻蚀机对多个第一光阻层进行部分刻蚀，得到多个第二预设厚度的第二光阻层；其中，设定等离子刻蚀机的刻蚀功率为1000～1600W，刻蚀时间为250～350s。
本发明实施例中，可以设定等离子刻蚀机的加工参数，例如，设定等离子刻蚀机的刻蚀功率为1000～1600W，刻蚀时间为250～350s。等离子刻蚀机的加工参数为部分灰化制程参数中的部分参数。
S107，在每个第二光阻层上设置一个与之对应的第二钴层，第二钴层的垂直投影与第二钴层对应的第二光阻层的垂直投影重合。
本发明实施例中，如图9所示，在第二光阻层107上设置一个与之对应的第二钴层108，第二钴层108用于后续步骤中阻挡掺杂离子透过光刻胶，避免对非掺杂区域进行掺杂。第二钴层108的垂直投影与第二钴层108对应的第二光阻层107的垂直投影重合是为了后续掺杂时能够将掺杂离子掺入半导体层102的特定区域。
S108，在半导体层中的第二特定区域掺入低浓度掺杂离子。
本发明实施例中，如图10所示，在半导体层102中的第二特定区域1022掺入低浓度掺杂离子，可以通过离子注入的方式在半导体层102中的第二特定区域1022掺入低浓度掺杂离子，第二特定区域1022与第一特定区域1021连接，第二特定区域1022内的低掺杂型漏极(LDD)掺杂，第二特定区域1022为第二光阻层107不覆盖的区域，可以通过第二光阻层107的位置和大小控制第二特定区域1022的大小。低浓度一般为小于1×1014/cm3。
可选的，步骤S108中，在半导体层中的第二特定区域掺入低浓度掺杂离子包括：
采用离子注入方式在半导体层中的第二特定区域掺入低浓度掺杂离子。
本发明实施例中，可以通过离子注入机在半导体层102中的第二特定区域1022掺入低浓度掺杂离子，可选的，低浓度掺杂离子包括低浓度P型掺杂离子或低浓度N型掺杂离子，P型掺杂离子可以包括氮、磷、砷等第五主族内的离子，N型掺杂离子可以包括硼、铝、镓等第三主族内的离子。
S109，移除第二钴层，对第二光阻层进行完全灰化处理，去除第二光阻层。
本发明实施例中，如图11所示，当LDD掺杂完成后，移除第二钴层108，对第二光阻层107进行完全灰化处理，以使第二光阻层107完全剥离。灰化制程中使用的气体可以是氧气(O2)，或者臭氧(O3)，或者氟化碳(CF4)或者氧化氮(N2O或者NO)，对第二光阻层进行完全灰化处理时用到的制程参数可以进行预先设定。
本发明实施例中，先形成第一光阻层105，在半导体层102中的第一特定区域1021掺入高浓度掺杂离子，完成SD掺杂，当SD掺杂完成后，无需对第一光阻层105进行完全剥离，通过步骤S106对第一光阻层105进行部分灰化处理，以使第一光阻层105变为第二光阻层107，然后利用第二光阻层107在半导体层102中的第二特定区域1022掺入低浓度掺杂离子，完成LDD掺杂，整个制作过程中，涂覆了一次光刻胶之后，完成了两道掺杂制程(SD掺杂和LDD掺杂)，整个掺杂过程，仅使用了一次光罩，与现有技术相比，可以减少光罩次数，降低生产时间。
请参阅图2，图2为本发明实施例公开的另一种低温多晶硅薄膜晶体管制造方法的流程示意图，如图2所描述的低温多晶硅薄膜晶体管制造方法，包括步骤：
S201，在基底层同一表面形成半导体层和低温多晶硅层。
S202，在半导体层背离基底层的一侧形成氧化层，在低温多晶硅层背离基底层的一侧形成氧化层。
S203，在氧化层上形成多个第一预设厚度的第一光阻层。
S204，在每个第一光阻层上设置一个与之对应的第一钴层，第一钴层的垂直投影与第一钴层对应的第一光阻层的垂直投影重合。
S205，在半导体层中的第一特定区域掺入高浓度掺杂离子。
S206，移除第一钴层，对多个第一光阻层进行部分灰化处理，得到多个第二预设厚度的第二光阻层，第二预设厚度小于第一预设厚度。
S207，在每个第二光阻层上设置一个与之对应的第二钴层，第二钴层的垂直投影与第二钴层对应的第二光阻层的垂直投影重合。
S208，在半导体层中的第二特定区域掺入低浓度掺杂离子。
S209，移除第二钴层，对第二光阻层进行完全灰化处理，去除第二光阻层。
S210，在氧化层上背离半导体层的一侧形成栅极。
本发明实施例中，如图13所示，在氧化层104表面背离半导体层102的一侧形成栅极109，可以通过溅射的方式在氧化,104上背离半导体层102的一侧形成栅极109。
本发明实施例中的步骤S201～步骤S209可以参见图1所示的步骤S101～步骤S109，本发明实施例不再赘述。
本发明实施例中，先形成第一光阻层105，在半导体层102中的第一特定区域1021掺入高浓度掺杂离子，完成SD掺杂，当SD掺杂完成后，无需对第一光阻层105进行完全剥离，通过步骤S106对第一光阻层105进行部分灰化处理，以使第一光阻层105变为第二光阻层107，然后利用第二光阻层107在半导体层102中的第二特定区域1022掺入低浓度掺杂离子，完成LDD掺杂，整个制作过程中，涂覆了一次光刻胶之后，完成了两道掺杂制程(SD掺杂和LDD掺杂)，整个掺杂过程，仅使用了一次光罩，与现有技术相比，可以减少光罩次数，降低生产时间。
图14为本发明实施公开的一种低温多晶硅薄膜晶体管的参数测试图，图14为对采用图1或图2的方法制作的低温多晶硅薄膜晶体管的一些参数进行测量得到的参数测试图。
图14中对九组不同灰化制程参数的低温多晶硅薄膜晶体管的一些参数进行测量，其中，PR thickness为第二光阻层107的厚度，单位为微米(μm)，Ashing Power为灰化刻蚀功率，单位为瓦特(W)，Ashing Time为灰化刻蚀时间，单位为秒(s)，P-doping Dosage为P型轻掺杂浓度，单位为1/立方厘米(cm-3)，CD data为关键尺寸(Critical Dimension，CD)，ArrayYield为低温多晶硅薄膜晶体管的良率，良率越高表明灰化制程参数较优。
从图14可以看出，当P型轻掺杂浓度为2.5×1013cm-3、灰化刻蚀功率1000W，灰化刻蚀时间300s时，良率为93.8％(第四组，L4)；当P型轻掺杂浓度为2.5×1013cm-3、灰化刻蚀功率1600W，灰化刻蚀时间250s时，良率为92.0％(第六组，L6)；当P型轻掺杂浓度为1.5×1013cm-3、灰化刻蚀功率1600W，灰化刻蚀时间300s时，良率为94.6％(第9组，L9)，从图14可知，第四组、第六组和第九组的制程参数较优，采用图1或图2的方法制作的低温多晶硅薄膜晶体管的良率较高。
以上所揭露的仅为本发明一种较佳实施例而已，当然不能以此来限定本发明之权利范围，本领域普通技术人员可以理解实现上述实施例的全部或部分流程，并依本发明权利要求所作的等同变化，仍属于发明所涵盖的范围。

Claims (9)

1.一种低温多晶硅薄膜晶体管制造方法，其特征在于，包括：
在基底层同一表面形成半导体层和低温多晶硅层；
在所述半导体层背离所述基底层的一侧形成氧化层，在所述低温多晶硅层背离所述基底层的一侧形成所述氧化层；
在所述氧化层上形成多个第一预设厚度的第一光阻层；
在每个第一光阻层上设置一个与之对应的第一钴层，所述第一钴层的垂直投影与所述第一钴层对应的第一光阻层的垂直投影重合；
在所述半导体层中的第一特定区域掺入高浓度掺杂离子；所述高浓度掺杂离子的掺杂浓度大于1×1017/cm3；
移除所述第一钴层，对所述多个第一光阻层进行部分灰化处理，得到多个第二预设厚度的第二光阻层，所述第二预设厚度小于所述第一预设厚度；
在每个第二光阻层上设置一个与之对应的第二钴层，所述第二钴层的垂直投影与所述第二钴层对应的第二光阻层的垂直投影重合；
在所述半导体层中的第二特定区域掺入低浓度掺杂离子；所述第二特定区域与所述第一特定区域连接，第二特定区域为所述第二光阻层不覆盖的区域；低浓度掺杂离子的掺杂浓度小于1×1014/cm3；
移除所述第二钴层，对所述第二光阻层进行完全灰化处理，去除所述第二光阻层；
所述对所述多个第一光阻层进行部分灰化处理，得到多个第二预设厚度的第二光阻层，包括：
利用等离子刻蚀机对所述多个第一光阻层进行部分刻蚀，得到多个第二预设厚度的第二光阻层；其中，设定所述等离子刻蚀机的刻蚀功率为1000～1600W，刻蚀时间为250～350s。
2.根据权利要求1所述的方法，其特征在于，所述基底层包括衬底、氮化硅层和氧化硅层，其中：
所述氮化硅层位于所述衬底之上；所述氧化硅层位于所述氮化硅层背离所述衬底的一侧。
3.根据权利要求2所述的方法，其特征在于，所述对所述第二光阻层进行完全灰化处理，去除所述第二光阻层之后，所述方法还包括：
在所述氧化层上背离所述半导体层的一侧形成栅极。
4.根据权利要求3所述的方法，其特征在于，所述第一预设厚度为1～3微米。
5.根据权利要求1～4任一项所述的方法，其特征在于，所述在所述半导体层中的第一特定区域掺入高浓度掺杂离子包括：
采用离子注入方式在所述半导体层中的第一特定区域掺入高浓度掺杂离子。
6.根据权利要求1～4任一项所述的方法，其特征在于，所述在所述半导体层中的第二特定区域掺入低浓度掺杂离子包括：
采用离子注入方式在所述半导体层中的第二特定区域掺入低浓度掺杂离子。
7.根据权利要求1～4任一项所述的方法，其特征在于，所述高浓度掺杂离子包括高浓度P型掺杂离子或高浓度N型掺杂离子。
8.根据权利要求1～4任一项所述的方法，其特征在于，所述低浓度掺杂离子包括低浓度P型掺杂离子或低浓度N型掺杂离子。
9.一种低温多晶硅薄膜晶体管，其特征在于，所述低温多晶硅薄膜晶体管采用权利要求1～8任一项所述的方法制得。
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