CN104576387B - 低温多晶硅薄膜晶体管制造方法 - Google Patents
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- 238000000034 method Methods 0.000 title claims abstract description 39
- 229910021420 polycrystalline silicon Inorganic materials 0.000 title claims abstract description 23
- 229920005591 polysilicon Polymers 0.000 title claims abstract description 23
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 22
- 238000001020 plasma etching Methods 0.000 claims abstract description 42
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 18
- 229910052581 Si3N4 Inorganic materials 0.000 claims abstract description 15
- 238000005530 etching Methods 0.000 claims abstract description 15
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims abstract description 15
- 239000000758 substrate Substances 0.000 claims abstract description 13
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims abstract description 12
- 238000009413 insulation Methods 0.000 claims abstract description 11
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- 239000007789 gas Substances 0.000 claims description 9
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- 239000010409 thin film Substances 0.000 claims description 6
- SFZCNBIFKDRMGX-UHFFFAOYSA-N sulfur hexafluoride Chemical compound FS(F)(F)(F)(F)F SFZCNBIFKDRMGX-UHFFFAOYSA-N 0.000 claims description 4
- 229910052760 oxygen Inorganic materials 0.000 claims description 3
- 239000001301 oxygen Substances 0.000 claims description 3
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims 2
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- 229910052814 silicon oxide Inorganic materials 0.000 description 13
- 229910004205 SiNX Inorganic materials 0.000 description 10
- 230000015572 biosynthetic process Effects 0.000 description 5
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- 230000007547 defect Effects 0.000 description 2
- 150000002500 ions Chemical class 0.000 description 2
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- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 238000003486 chemical etching Methods 0.000 description 1
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- 238000000151 deposition Methods 0.000 description 1
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- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
- H01L29/78618—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure
- H01L29/78621—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure with LDD structure or an extension or an offset region or characterised by the doping profile
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- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66492—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a pocket or a lightly doped drain selectively formed at the side of the gate
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- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
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- H01L29/41725—Source or drain electrodes for field effect devices
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- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42384—Gate electrodes for field effect devices for field-effect transistors with insulated gate for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
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- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66742—Thin film unipolar transistors
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Abstract
公开了一种低温多晶硅薄膜晶体管制造方法,包括:在基板上形成多晶硅层;在多晶硅层上依序形成具有氧化硅和氮化硅层叠结构的栅绝缘层以及栅极层;在栅极层上形成图案化光致抗蚀剂;对基板进行等离子体蚀刻和反应离子蚀刻,以去除未被光致抗蚀剂覆盖的氮化硅和栅极层;移除栅极层,以形成栅底脚和栅极;移除光致抗蚀剂,利用栅极和栅底脚为掩模进行重掺杂工艺,形成源/漏极和轻掺杂漏极。采用本申请提供的方法,可以减小蚀刻栅极层和氮化硅层时氧化硅的损失。
Description
技术领域
本申请涉及薄膜晶体管技术,尤其涉及一种低温多晶硅薄膜晶体管(LowTemperature Poly Silicon Thin Film Transistor,LTPS TFT)制造方法。
背景技术
在LTPS工艺中,轻掺杂漏极(Lightly Doped Drain,LDD)的存在对漏电流(Ioff)的抑制是很重要的。LDD的一种制作方法是形成具有氧化硅和氮化硅层叠结构(SiOx/SiNx)的栅绝缘层,栅极层形成在该栅绝缘层上,然后通过干蚀刻形成栅底脚,即SiNx底脚。
图1到图4示出了现有技术LTPS工艺中的TFT的结构示意图。
如图1所示,在干蚀刻之前,由SiNx和SiOx层叠结构形成的栅绝缘层14形成在多晶硅层13上方。然后,利用物理蚀刻和化学蚀刻,先蚀刻掉未被光致抗蚀剂PR覆盖的栅极层15和栅绝缘层14中的SiNx,如图2所示。之后,对栅极层15进行进一步蚀刻,形成SiNx底脚14a,如图3所示。之后,去除光致抗蚀剂,通过掺杂形成LDD结构。
图1到图3所示的现有技术LTPS工艺中存在的问题是,在蚀刻栅极层15和栅绝缘层14中的SiNx的过程中,由于太偏重物理蚀刻,因而会造成栅绝缘层14中SiOx的损失(如图4所示),而SiOx的损失会造成阈值电压偏移,从而减小漏电流路径,造成漏电流变大。而且,SiOx的损失不均,会造成mura发生。
发明内容
为了解决上述问题,本申请提供一种LTPS TFT制造方法,能够避免SiOx损失。
在本申请的一个方案中,提供了一种LTPS TFT制造方法,包括:
在基板上形成多晶硅层;
在所述多晶硅层上依序形成具有氧化硅和氮化硅层叠结构的栅绝缘层以及栅极层;
在所述栅极层上形成图案化光致抗蚀剂;
对于所述基板进行等离子体蚀刻和反应离子蚀刻,以去除未被所述光致抗蚀剂覆盖的氮化硅和栅极层;
移除所述栅极层,以形成栅底脚和栅极;
移除所述光致抗蚀剂,利用所述栅极和所述栅底脚为掩模进行重掺杂工艺,形成源/漏极和轻掺杂漏极。
在本申请提供的LTPS TFT制造方法中,在蚀刻栅极层和SiNx的步骤中,进行等离子体蚀刻(Plasma Etching,PE)和反应离子蚀刻(Reactive Ion Etching,RIE)两种蚀刻,并且可以减小用于RIE的功率,也就是说,减小在该蚀刻步骤中RIE所占的比重,从而减小了物理蚀刻的作用,避免了在蚀刻SiNx和栅极层的过程中造成的SiOx损失。这样,避免了由于SiOx损失造成的阈值偏移、漏电流路径减小以及漏电流变大等缺陷。
附图说明
图1到图4示出了现有技术LTPS工艺中的TFT的结构示意图;
图5示意性示出本申请LTPS TFT制造方法实施例的流程图;
图6到图10示意性示出本申请LTPS-TFT制造方法实施例形成的TFT的剖视图;
图12示出了一种O2的百分比与相对蚀刻率之间的关系的曲线图。
具体实施方式
图5示意性示出本申请LTPS TFT制造方法实施例的流程图。图6到图10示意性示出本申请LTPS-TFT制造方法实施例形成的TFT的剖视图。
在步骤S101中,如图6所示,在基板21上形成多晶硅层23。该基板可以为玻璃或者其他适用于显示器件的基板。多晶硅层可以包括沟道部23a、轻掺杂漏极形成部23b和源/漏极形成部23c。本申请对于形成多晶硅层23的方式没有特别的限定。例如,该多晶硅层23的形成方式可以是,例如,在基板21上形成一非晶硅层,接着对该非晶硅层进行一准分子激光退火工艺或者一热处理,以使非晶硅层形成为多晶硅层。
在基板21和多晶硅层23之间还可以包括缓冲层22,该缓冲层可以是SiNx和SiOx形成的层叠结构。
在步骤S102中,如图7所示,在多晶硅层23上依序形成具有SiOx和SiNx层叠结构的栅绝缘层24以及栅极层25。该栅极层25的材料可以是金属,例如钼(Mo)等。在该步骤中,关于栅绝缘层24和栅极层25的形成方法没有限制,例如,可以采用化学气相沉积方法、溅射或者蒸镀等方法。
在步骤S103中,如图8所示,在栅极层25上形成图案化光致抗蚀剂PR。具体地,可以在栅极层25上形成光致抗蚀剂层,利用图案化掩模,通过光刻技术对该光致抗蚀剂层进行曝光、显影等,从而形成图案化的光致抗蚀剂PR。该光致抗蚀剂PR的图案可以由待形成的栅极的尺寸和栅底脚的尺寸来确定。
在步骤S104中,对于图8所示的基板进行等离子体蚀刻和反应离子蚀刻,蚀刻掉未被光致抗蚀剂PR覆盖的SiNx和栅极层25,如图9所示。例如,该步骤可以在在能够同时进行等离子体蚀刻和反应离子蚀刻的机台(例如,可以是感应耦合等离子体机台)中进行。在该过程中,可以将进行反应离子蚀刻的功率减小,从而减小离子轰击。由于离子轰击减小,因而可以减小在蚀刻过程中对于SiOx造成的蚀刻,从而减小了SiOx损失。
在步骤S104中,通入的反应气体可以是氟化硫(SF6)和氧气(O2)的混合气体,其中,O2的比例可以根据膜的蚀刻率和薄膜晶体管的良率(Yield)来确定。图12示出了一种O2的百分比与相对蚀刻率之间的关系的曲线图,从该曲线图中可以看出,对于SiOx而言,当O2的比例是在大约23%时,蚀刻率最大。通过该曲线图,接合TFT的良率,可以适当地确定出O2在SF6和O2的混合气体中的比例。一个原则是,需要兼顾蚀刻率和TFT的良率,不能为了获得高的蚀刻率而忽略TFT的良率。
当然,也可以采用其他的反应气体,例如,可以采用氟化碳(CF4)。
在步骤S104中,进行蚀刻时所采用的温度可以基于均匀性(LTPS的质量关键)考虑而设定,例如,可以在大约60摄氏度以下进行蚀刻,优选的是在室温下(大约25摄氏度)进行。另外,进行蚀刻时所采用的压强可以基于反应气体的量以及温度来设定。
在步骤S105中,如图10所示,移除栅极层25,形成栅底脚,同时形成栅极25a。在该步骤中,所使用的反应气体可以是氯气(Cl2)和O2的混合气体。
在步骤S106中,如图11所示,移除光致抗蚀剂PR之后,利用栅极25a和栅底脚24a为掩模进行重掺杂工艺,形成源/漏极和轻掺杂漏极。具体而言,可以进行重掺杂工艺,使得未被栅底脚24a覆盖的源/漏极形成部23c被重掺杂,从而形成源/漏极;而LLD形成部23b由于栅底脚24a的遮蔽作用而形成轻掺杂区。
在经过步骤S106之后还可以形成与源/漏极接触的接触线以及绝缘层等,这些部件的形成可以采用本申请中公知的技术,此处不再赘述。
在本申请提供的LTPS TFT制造方法中,还可以包括:对所形成的薄膜晶体管的栅底脚的倾斜角度进行分析(例如,可以通过扫描电子显微镜(Scanning ElectronMicroscope,SEM)分析方法进行分析);确定栅底脚倾斜角度对应的反应离子蚀刻功率和等离子体蚀刻功率(具体地,可以确定优选的栅底脚倾斜角度对应的反应离子蚀刻功率和等离子体蚀刻功率);由栅底脚倾斜角度对应的反应离子蚀刻功率和等离子体蚀刻功率来进行反应离子蚀刻和等离子体蚀刻。
在具有LDD结构的TFT中,栅底脚倾斜角度越小,即栅底脚越平缓,则形成的LDD的电气性能越好。反之,栅底脚倾斜角度越大,即栅底脚越陡,则形成的LDD的电气性能越差。
在LTPS TFT形成过程中,实时监测栅底脚的倾斜角度有些困难,因而可以在形成TFT之后,利用SEM方法对所形成的栅底脚的倾斜角度进行分析,进而确定出优选的栅底脚倾斜角度对应的反应离子蚀刻功率和等离子体蚀刻功率。
具体而言,如果用于RIE的功率较大,即在RIE和PE同时蚀刻的步骤中偏重RIE,则栅底脚的倾斜角度大,即栅底脚比较陡;如果用于PE的功率较大,即在RIE和PE同时蚀刻的步骤中偏重PE,则栅底脚的倾斜角度小,即栅底脚平缓。
因而,例如,如果通过SEM方法分析确定所形成的栅底脚倾斜角度与优选的栅底脚倾斜角度相比较大,则可以在后续的制造过程中,调高用于PE的功率,而调低用于RIE的功率,使得后续形成的栅底脚变缓。
在本申请提供的LTPS TFT制造方法中,在蚀刻栅极层和SiNx的步骤中,进行RE和RIE两种蚀刻(例如,可以在能够进行RE和RIE这两种蚀刻的机台中进行蚀刻),并且可以减小用于RIE的功率,也就是说,减小在该蚀刻步骤中RIE所占的比重,从而减小了物理蚀刻的作用,避免了在蚀刻SiNx和栅极层的过程中造成的SiOx损失。这样,避免了由于SiOx损失造成的阈值偏移、漏电流路径减小以及漏电流变大等缺陷,提高了LTPS元件的可靠性。
而且,在本申请提供的LTPS-TFT制造方法中,通过SEM分析方法分析栅底脚的倾斜角度来确定PE和RIE的功率,通过增大用于PE的功率来减小栅底脚的倾斜角度,即使得栅底脚平缓,从而获得电气性能优良的LDD。
可见,采用本申请提供的LTPS-TFT制造方法,既能够获得满足要求的SiNx底脚,使得LDD发挥其最大性能,又能够避免SiOx损失进而避免由于SiOx损失带来的一系列问题。
在本申请图6到图10中主要是以P沟道TFT为例进行说明,然而,该TFT也可以是N沟道TFT,具体的制造工艺与P沟道TFT的类似,此处不再赘述。
虽然已参照几个典型实施例描述了本申请,但应当理解,所用的术语是说明和示例性、而非限制性的术语。由于本申请能够以多种形式具体实施而不脱离发明的精神或实质,所以应当理解,上述实施例不限于任何前述的细节,而应在随附权利要求所限定的精神和范围内广泛地解释,因此落入权利要求或其等效范围内的全部变化和改型都应为随附权利要求所涵盖。
Claims (5)
1.一种低温多晶硅薄膜晶体管制造方法,包括:
在基板上形成多晶硅层;
在所述多晶硅层上依序形成具有氧化硅和氮化硅层叠结构的栅绝缘层以及栅极层;
在所述栅极层上形成图案化光致抗蚀剂;
对于所述基板进行等离子体蚀刻和反应离子蚀刻,以去除未被所述光致抗蚀剂覆盖的氮化硅和栅极层;
移除部分所述栅极层,以形成氮化硅底脚和栅极,所述氮化硅底脚是移除部分所述栅极层后所述栅极层暴露出的氮化硅;
移除所述光致抗蚀剂,利用所述栅极和所述氮化硅底脚为掩模进行重掺杂工艺,形成源/漏极和轻掺杂漏极;
还包括:
对所形成的薄膜晶体管的氮化硅底脚的倾斜角度进行分析;
确定氮化硅底脚倾斜角度对应的反应离子蚀刻功率和等离子体蚀刻功率;
由氮化硅底脚倾斜角度对应的反应离子蚀刻功率和等离子体蚀刻功率来进行反应离子蚀刻和等离子体蚀刻。
2.根据权利要求1所述的低温多晶硅薄膜晶体管制造方法,其中,在对于所述基板进行等离子体蚀刻和反应离子蚀刻的过程中,使用氟化硫和氧气的混合气体作为反应气体。
3.根据权利要求2所述的低温多晶硅薄膜晶体管制造方法,其中,所述氟化硫和氧气的比例由蚀刻率和薄膜晶体管的良率来确定。
4.根据权利要求1所述的低温多晶硅薄膜晶体管制造方法,其中,在对于所述基板进行蚀刻的过程中,所使用的温度小于60摄氏度。
5.根据权利要求4所述的低温多晶硅薄膜晶体管制造方法,其中,在对于所述基板进行蚀刻的过程中,所使用的温度是25摄氏度。
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