TWI528464B - 低溫多晶矽薄膜電晶體製造方法 - Google Patents
低溫多晶矽薄膜電晶體製造方法 Download PDFInfo
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- 238000004519 manufacturing process Methods 0.000 title claims description 18
- 229910021420 polycrystalline silicon Inorganic materials 0.000 title claims description 13
- 229920005591 polysilicon Polymers 0.000 title claims description 13
- 239000010409 thin film Substances 0.000 title claims description 8
- 238000001020 plasma etching Methods 0.000 claims description 52
- 238000005530 etching Methods 0.000 claims description 31
- 238000000034 method Methods 0.000 claims description 27
- 229920002120 photoresistant polymer Polymers 0.000 claims description 14
- 239000000758 substrate Substances 0.000 claims description 14
- 229910052732 germanium Inorganic materials 0.000 claims description 10
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 claims description 10
- 239000010408 film Substances 0.000 claims description 5
- 239000007789 gas Substances 0.000 claims description 5
- MZLGASXMSKOWSE-UHFFFAOYSA-N tantalum nitride Chemical compound [Ta]#N MZLGASXMSKOWSE-UHFFFAOYSA-N 0.000 claims description 5
- 239000012495 reaction gas Substances 0.000 claims description 4
- BPUBBGLMJRNUCC-UHFFFAOYSA-N oxygen(2-);tantalum(5+) Chemical compound [O-2].[O-2].[O-2].[O-2].[O-2].[Ta+5].[Ta+5] BPUBBGLMJRNUCC-UHFFFAOYSA-N 0.000 claims description 3
- SFZCNBIFKDRMGX-UHFFFAOYSA-N sulfur hexafluoride Chemical compound FS(F)(F)(F)(F)F SFZCNBIFKDRMGX-UHFFFAOYSA-N 0.000 claims description 3
- 229910001936 tantalum oxide Inorganic materials 0.000 claims description 3
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 2
- 229910052760 oxygen Inorganic materials 0.000 claims description 2
- 239000001301 oxygen Substances 0.000 claims description 2
- 229960000909 sulfur hexafluoride Drugs 0.000 claims 2
- MYMOFIZGZYHOMD-UHFFFAOYSA-N Dioxygen Chemical compound O=O MYMOFIZGZYHOMD-UHFFFAOYSA-N 0.000 claims 1
- 229910001882 dioxygen Inorganic materials 0.000 claims 1
- 230000015572 biosynthetic process Effects 0.000 description 6
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- 238000010849 ion bombardment Methods 0.000 description 2
- ZAMOUSCENKQFHK-UHFFFAOYSA-N Chlorine atom Chemical compound [Cl] ZAMOUSCENKQFHK-UHFFFAOYSA-N 0.000 description 1
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 1
- 238000003486 chemical etching Methods 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
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- 229910052750 molybdenum Inorganic materials 0.000 description 1
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- 238000004626 scanning electron microscopy Methods 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 230000001629 suppression Effects 0.000 description 1
- TXEYQDLBPFQVAA-UHFFFAOYSA-N tetrafluoromethane Chemical compound FC(F)(F)F TXEYQDLBPFQVAA-UHFFFAOYSA-N 0.000 description 1
- 238000013022 venting Methods 0.000 description 1
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- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
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- H01L29/78621—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure with LDD structure or an extension or an offset region or characterised by the doping profile
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- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
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Description
本申請涉及薄膜電晶體技術，尤其涉及一種低溫多晶矽薄膜電晶體(Low Temperature Poly Silicon Thin Film Transistor，LTPS TFT)製造方法。
在LTPS工藝中，輕摻雜洩極(Lightly Doped Drain，LDD)的存在對漏電流(Ioff)的抑制是很重要的。LDD的一種製作方法是形成具有氧化矽和氮化矽層疊結構(SiOx/SiNx)的閘絕緣層，閘極層形成在該閘絕緣層上，然後通過乾蝕刻形成閘底脚，即SiNx底脚。
圖1到圖4示出了現有技術LTPS工藝中的TFT的結構示意圖。
如圖1所示，在乾蝕刻之前，由SiNx和SiOx層疊結構形成的閘絕緣層14形成在多晶矽層13上方。然後，利用物理蝕刻和化學蝕刻，先蝕刻掉未被光致抗蝕劑PR覆蓋的閘極層15和閘絕緣層14中的SiNx，如圖2所示。之後，對閘極層15進行進一步蝕刻，形成SiNx底脚14a，如圖3所示。之後，去除光致抗蝕劑，通過摻雜形成LDD結構。
圖1到圖3所示的現有技術LTPS工藝中存在的問題是，在蝕刻閘極層15和閘絕緣層14中的SiNx的過程中，由於太偏重物理蝕刻，因而會造成閘絕緣層14中SiOx的損失(如圖4所示)，而SiOx的損失會造成閾值電壓偏移，從而减小漏電流路徑，造成漏電流變大。而且，SiOx的損失不均，會造成mura發生。
為了解决上述問題，本申請提供一種LTPS TFT製造方法，
能够避免SiOx損失。
在本申請的一個方案中，提供了一種LTPS TFT製造方法，包括：在基板上形成多晶矽層；在所述多晶矽層上依序形成具有氧化矽和氮化矽層疊結構的閘絕緣層以及閘極層；在所述閘極層上形成圖案化光致抗蝕劑；對於所述基板進行等離子體蝕刻和反應離子蝕刻，以去除未被所述光致抗蝕劑覆蓋的氮化矽和閘極層；移除所述閘極層，以形成閘底脚和閘極；移除所述光致抗蝕劑，利用所述閘極和所述閘底脚為掩模進行重摻雜工藝，形成源/洩極和輕摻雜洩極。
在本申請提供的LTPS TFT製造方法中，在蝕刻閘極層和SiNx的步驟中，進行等離子體蝕刻(Plasma Etching,PE)和反應離子蝕刻(Reactive Ion Etching，RIE)兩種蝕刻，並且可以减小用於RIE的功率，也就是說，减小在該蝕刻步驟中RIE所占的比重，從而减小了物理蝕刻的作用，避免了在蝕刻SiNx和閘極層的過程中造成的SiOx損失。這樣，避免了由於SiOx損失造成的閾值偏移、漏電流路徑减小以及漏電流變大等缺陷。
21‧‧‧基板
22‧‧‧緩衝層
23‧‧‧多晶矽層
23a‧‧‧溝道部
23b‧‧‧輕摻雜洩極形成部
23c‧‧‧源/洩極形成部
24‧‧‧閘絕緣層
24a‧‧‧閘底脚
25‧‧‧閘極層
25a‧‧‧閘極
S101~S106‧‧‧步驟
圖1到圖4示出了現有技術LTPS工藝中的TFT的結構示意圖；圖5示意性示出本申請LTPS TFT製造方法實施例的流程圖；圖6到圖11示意性示出本申請LTPS-TFT製造方法實施例形成的TFT的剖視圖；圖12示出了一種O2的百分比與相對蝕刻率之間的關係的曲線圖。
圖5示意性示出本申請LTPS TFT製造方法實施例的流程圖。圖6到圖11示意性示出本申請LTPS-TFT製造方法實施例形成的TFT的剖視圖。
在步驟S101中，如圖6所示，在基板21上形成多晶矽層23。該基板可以為玻璃或者其他適用於顯示器件的基板。多晶矽層可以包括溝道部23a、輕摻雜洩極形成部23b和源/洩極形成部23c。本申請對於形成多晶矽層23的方式沒有特別的限定。例如，該多晶矽層23的形成方式可以是，例如，在基板21上形成一非晶矽層，接著對該非晶矽層進行一準分
子激光退火工藝或者一熱處理，以使非晶矽層形成為多晶矽層。
在基板21和多晶矽層23之間還可以包括緩衝層22，該緩衝層可以是SiNx和SiOx形成的層疊結構。
在步驟S102中，如圖7所示，在多晶矽層23上依序形成具有SiOx和SiNx層疊結構的閘絕緣層24以及閘極層25。該閘極層25的材料可以是金屬，例如鉬(Mo)等。在該步驟中，關於閘絕緣層24和閘極層25的形成方法沒有限制，例如，可以採用化學氣相沉積方法、濺射或者蒸鍍等方法。
在步驟S103中，如圖8所示，在閘極層25上形成圖案化光致抗蝕劑PR。具體地，可以在閘極層25上形成光致抗蝕劑層，利用圖案化掩模，通過光刻技術對該光致抗蝕劑層進行曝光、顯影等，從而形成圖案化的光致抗蝕劑PR。該光致抗蝕劑PR的圖案可以由待形成的閘極的尺寸和閘底脚的尺寸來確定。
在步驟S104中，對於圖8所示的基板進行等離子體蝕刻和反應離子蝕刻，蝕刻掉未被光致抗蝕劑PR覆蓋的SiNx和閘極層25，如圖9所示。例如，該步驟可以在在能够同時進行等離子體蝕刻和反應離子蝕刻的機台(例如，可以是感應耦合等離子體機台)中進行。在該過程中，可以將進行反應離子蝕刻的功率减小，從而减小離子轟擊。由於離子轟擊减小，因而可以减小在蝕刻過程中對於SiOx造成的蝕刻，從而减小了SiOx損失。
在步驟S104中，通入的反應氣體可以是氟化硫(SF6)和氧氣(O2)的混合氣體，其中，O2的比例可以根據膜的蝕刻率和薄膜電晶體的良率(Yield)來確定。圖12示出了一種O2的百分比與相對蝕刻率之間的關係的曲線圖，從該曲線圖中可以看出，對於SiOx而言，當O2的比例是在大約23%時，蝕刻率最大。通過該曲線圖，接合TFT的良率，可以適當地確定出O2在SF6和O2的混合氣體中的比例。一個原則是，需要兼顧蝕刻率和TFT的良率，不能為了獲得高的蝕刻率而忽略TFT的良率。
當然，也可以採用其他的反應氣體，例如，可以採用氟化碳
(CF4)。
在步驟S104中，進行蝕刻時所採用的溫度可以基於均勻性(LTPS的質量關鍵)考慮而設定，例如，可以在大約60攝氏度以下進行蝕刻，優選的是在室溫下(大約25攝氏度)進行。另外，進行蝕刻時所採用的壓强可以基於反應氣體的量以及溫度來設定。
在步驟S105中，如圖10所示，移除閘極層25，形成閘底脚，同時形成閘極25a。在該步驟中，所使用的反應氣體可以是氯氣(Cl2)和O2的混合氣體。
在步驟S106中，如圖11所示，移除光致抗蝕劑PR之後，利用閘極25a和閘底脚24a為掩模進行重摻雜工藝，形成源/洩極和輕摻雜洩極。具體而言，可以進行重摻雜工藝，使得未被閘底脚24a覆蓋的源/洩極形成部23c被重摻雜，從而形成源/洩極；而LDD形成部23b由於閘底脚24a的遮蔽作用而形成輕摻雜區。
在經過步驟S106之後還可以形成與源/洩極接觸的接觸線以及絕緣層等，這些部件的形成可以採用本申請中公知的技術，此處不再贅述。
在本申請提供的LTPS TFT製造方法中，還可以包括：對所形成的薄膜電晶體的閘底脚的傾斜角度進行分析(例如，可以通過掃描電子顯微鏡(Scanning Electron Microscope，SEM)分析方法進行分析)；確定閘底脚傾斜角度對應的反應離子蝕刻功率和等離子體蝕刻功率(具體地，可以確定優選的閘底脚傾斜角度對應的反應離子蝕刻功率和等離子體蝕刻功率)；由閘底脚傾斜角度對應的反應離子蝕刻功率和等離子體蝕刻功率來進行反應離子蝕刻和等離子體蝕刻。
在具有LDD結構的TFT中，閘底脚傾斜角度越小，即閘底脚越平緩，則形成的LDD的電氣性能越好。反之，閘底脚傾斜角度越大，即閘底脚越陡，則形成的LDD的電氣性能越差。
在LTPS TFT形成過程中，實時監測閘底脚的傾斜角度有些困難，因而可以在形成TFT之後，利用SEM方法對所形成的閘底脚的傾斜
角度進行分析，進而確定出優選的閘底脚傾斜角度對應的反應離子蝕刻功率和等離子體蝕刻功率。
具體而言，如果用於RIE的功率較大，即在RIE和PE同時蝕刻的步驟中偏重RIE，則閘底脚的傾斜角度大，即閘底脚比較陡；如果用於PE的功率較大，即在RIE和PE同時蝕刻的步驟中偏重PE，則閘底脚的傾斜角度小，即閘底脚平緩。
因而，例如，如果通過SEM方法分析確定所形成的閘底脚傾斜角度與優選的閘底脚傾斜角度相比較大，則可以在後續的製造過程中，調高用於PE的功率，而調低用於RIE的功率，使得後續形成的閘底脚變緩。
在本申請提供的LTPS TFT製造方法中，在蝕刻閘極層和SiNx的步驟中，進行PE和RIE兩種蝕刻(例如，可以在能够進行PE和RIE這兩種蝕刻的機台中進行蝕刻)，並且可以减小用於RIE的功率，也就是說，减小在該蝕刻步驟中RIE所占的比重，從而减小了物理蝕刻的作用，避免了在蝕刻SiNx和閘極層的過程中造成的SiOx損失。這樣，避免了由於SiOx損失造成的閾值偏移、漏電流路徑减小以及漏電流變大等缺陷，提高了LTPS元件的可靠性。
而且，在本申請提供的LTPS-TFT製造方法中，通過SEM分析方法分析閘底脚的傾斜角度來確定PE和RIE的功率，通過增大用於PE的功率來减小閘底脚的傾斜角度，即使得閘底脚平緩，從而獲得電氣性能優良的LDD。
可見，採用本申請提供的LTPS-TFT製造方法，既能够獲得滿足要求的SiNx底脚，使得LDD發揮其最大性能，又能够避免SiOx損失進而避免由於SiOx損失帶來的一系列問題。
在本申請圖6到圖10中主要是以P溝道TFT為例進行說明，然而，該TFT也可以是N溝道TFT，具體的製造工藝與P溝道TFT的類似，此處不再贅述。
雖然已參照幾個典型實施例描述了本申請，但應當理解，所
用的術語是說明和示例性、而非限制性的術語。由於本申請能够以多種形式具體實施而不脫離發明的精神或實質，所以應當理解，上述實施例不限於任何前述的細節，而應在隨附申請專利範圍所限定的精神和範圍內廣泛地解釋，因此落入申請專利範圍或其等效範圍內的全部變化和改型都應為隨附申請專利範圍所涵蓋。
S101~S106‧‧‧步驟
Claims (5)
- 一種低溫多晶矽薄膜電晶體製造方法，包括：在基板上形成多晶矽層；在所述多晶矽層上依序形成具有氧化矽和氮化矽層疊結構的閘絕緣層以及閘極層；在所述閘極層上形成圖案化光致抗蝕劑；對於所述基板進行等離子體蝕刻和反應離子蝕刻，以去除未被所述光致抗蝕劑覆蓋的氮化矽和閘極層；移除所述閘極層，以形成閘底脚和閘極；移除所述光致抗蝕劑，利用所述閘極和所述閘底脚為掩模進行重摻雜工藝，形成源/洩極和輕摻雜洩極，其中，在對於所述基板進行蝕刻的過程中，所使用的溫度小於60攝氏度。
- 根據申請專利範圍第1項所述的低溫多晶矽薄膜電晶體製造方法，其中，在對於所述基板進行等離子體蝕刻和反應離子蝕刻的過程中，使用氟化硫和氧氣的混合氣體作為反應氣體。
- 根據申請專利範圍第2項所述的低溫多晶矽薄膜電晶體製造方法，其中，所述氟化硫和氧氣的比例由蝕刻率和薄膜電晶體的良率來確定。
- 根據申請專利範圍第1項所述的低溫多晶矽薄膜電晶體製造方法，其中，在對於所述基板進行蝕刻的過程中，所使用的溫度是25攝氏度。
- 根據申請專利範圍第1項所述的低溫多晶矽薄膜電晶體製造方法，還包括：對所形成的薄膜電晶體的閘底脚的傾斜角度進行分析；確定閘底脚傾斜角度對應的反應離子蝕刻功率和等離子體蝕刻功率；由閘底脚傾斜角度對應的反應離子蝕刻功率和等離子體蝕刻功率來進行反應離子蝕刻和等離子體蝕刻。
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