CN106898651A - 一种选择性刻蚀的ldmos器件的制造方法 - Google Patents

一种选择性刻蚀的ldmos器件的制造方法 Download PDF

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CN106898651A
CN106898651A CN201710066412.9A CN201710066412A CN106898651A CN 106898651 A CN106898651 A CN 106898651A CN 201710066412 A CN201710066412 A CN 201710066412A CN 106898651 A CN106898651 A CN 106898651A
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CN106898651B (zh
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柳志亨
郑志星
乔伊·迈克格雷格
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Chengdu Monolithic Power Systems Co Ltd
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Abstract

本发明提出了一种制造位于半导体衬底上的阱区内的LDMOS器件的方法，包括：通过阱区之上的多晶硅层窗口，在阱区内形成体区和源极层，其中体区具有比源极层更深的结深；在多晶硅层窗口内侧的侧壁处形成间隔；以及通过间隔所形成的窗口，对源极层进行刻蚀至源极层被穿通，其中源极层中位于间隔正下方的区域在源极层被刻蚀的过程中受到保护，并被定义成LDMOS器件的源极区。源极区宽度由间隔的厚度决定。本发明采用间隔和选择性刻蚀形成较窄的N+/P+/N+源极/体区，从而既减小了源极区，又有效降低了制造LDMOS的成本。

Description

一种选择性刻蚀的LDMOS器件的制造方法
技术领域
本发明涉及半导体器件，更具体地说，本发明涉及制造横向扩散型金属氧化物半导体(LDMOS，Laterally Diffused Metal Oxide Semiconductor)器件的方法。
背景技术
LDMOS器件因其高击穿电压、大电流及良好的温度特性而广泛应用于笔记本电脑、服务器和DC/DC电压转换电路。
如图1所示，LDMOS器件包括阱区16、漏极接触区11、源极区12、栅极13、体区14以及体接触区15。本领域普通技术人员应该知道，阱区16也称作漏极漂移区。出于对性能和成本的考虑，现在许多应用场合都要求封装更小的功率器件。为了得到更小的功率器件，大量的研究关注于减小漏极区尺寸的工艺，例如降低表面电场RESURF(Reduced Surface Field)及梯度掺杂漏极(Graded Dope Drain)等。而有一部分研究则关注于减小源极区的工艺。如图1所示，源极/体区内包括位于中心的体接触区15和分布在体接触区两边的源极区12，从而形成一个N+/P+/N+区域，减小该N+/P+/N+区域可减小源极区。但N+/P+/N+的最小面积通常会受到光掩模设备性能的限制。
发明内容
本发明的目的是提供一种工艺，该工艺在一道掩膜工序中，采用间隔形成自对准的源极区和体接触区，替代因囿于设备性能限制而无法产生更小的源极/体区窗口的光掩膜工序。因此，本发明减小了LDMOS器件的源极区，并且有效降低了制造LDMOS器件的成本。
本发明的实施例旨在提供一种制造LDMOS器件的工艺流程，其中该LDMOS器件位于半导体衬底中的具有第一掺杂类型的阱区，包括：在阱区上形成薄栅氧层；在薄栅氧层上形成多晶硅层；在多晶硅层上形成阻隔层，该阻隔层的刻蚀速度比薄栅氧层的刻蚀速度快；通过在阻隔层之上的第一掩膜层的窗口，对阻隔层和多晶硅层进行刻蚀；通过第一掩膜层的窗口，向阱区注入具有第二掺杂类型的杂质，形成体区；通过第一掩膜层的窗口，向体区注入具有第一掺杂类型的杂质，形成源极层；形成间隔，该间隔包裹刻蚀后所形成的多晶硅层窗口内侧的侧壁；通过间隔所形成的窗口，对源极层进行刻蚀至源极层被穿通，形成源极区；通过间隔所形成的窗口，向体区注入具有第二掺杂类型的杂质，形成体接触区；通过刻蚀移除间隔和阻隔层；通过第二掩膜层的窗口，对多晶硅层进行刻蚀，形成栅极；以及通过第三掩膜层的窗口，向阱区注入具有第一掺杂类型的杂质，形成漏极接触区。
本发明的实施例旨在描述一种制造LDMOS器件的方法，包括：通过阱区之上的多晶硅层窗口，在阱区内形成体区和源极层，其中体区具有比源极层更深的结深；在多晶硅层窗口内侧的侧壁处形成间隔；以及通过间隔所形成的窗口，对源极层进行刻蚀至源极层被穿通，其中源极层中位于间隔正下方的区域在源极层被刻蚀的过程中受到保护，并被定义成LDMOS器件的源极区。
本发明的实施例旨在进一步描述一种制造LDMOS器件的工艺流程，包括：在半导体衬底内形成阱区；在阱区上形成薄栅氧层；在薄栅氧层上形成多晶硅层；在多晶硅层上按顺序依次形成栅极密封层、氮化硅层和第一掩膜层，其中第一掩膜层包括至少一个通向氮化硅层表面的窗口；通过第一掩膜层的窗口，对氮化硅层、栅极密封层和多晶硅层进行刻蚀，暴露出阱区中对应于体区的窗口；通过体区窗口，向阱区注入P型杂质，在阱区内形成体区；通过体区窗口，向体区注入N型杂质，在体区内形成源极层，随后移除第一掩膜层；对多晶硅层窗口内侧的侧壁进行氧化；在多晶硅层窗口内侧被氧化的侧壁处形成间隔；通过间隔所形成的窗口，对源极层进行刻蚀至源极层被穿通，形成位于间隔正下方的源极区；向体区中位于源极区之间的被刻蚀的区域注入P型杂质，形成体接触区；通过刻蚀移除氮化硅层和间隔；在栅极密封层上形成第二掩膜层，其中第二掩膜层具有位置预定的窗口；通过第二掩膜层的窗口，对栅极密封层和多晶硅层进行刻蚀，形成栅极，随后移除第二掩膜层；在栅极和薄栅氧层上形成第三掩膜层，该第三掩膜层包含至少一个对应于漏极接触区的窗口；以及通过第三掩膜层的窗口，向阱区注入N型杂质，形成漏极接触区，随后移除第三掩膜层。
附图说明
为了更好的理解本发明，将根据以下附图对本发明的实施例进行描述。这些附图仅用于示意说明，相似的部分具有相似的数字标号。附图仅示出器件的部分特征，并且不一定按照比例进行绘制，附图的尺寸和比例可能与实际的尺寸和比例不一致。
图1示出了现有的LDMOS器件的剖面图；
图2示出了现有的制造LDMOS器件的工艺流程概要图；
图3a-3i示出了根据本发明一实施例的制造具有小源极区的LDMOS器件的制程；
图4示出了根据本发明一实施例的用于制造图3a-3i所示出的LDMOS器件的工艺流程概要图。
具体实施方式
下面将详细描述本发明的具体实施例。应当理解的是，这些实施例只用于举例说明，并不用于限制本发明。相反地，本发明应当涵盖替代、修改和等效等方式，这些方式可能在附加的权利要求所定义的精神和范围之内。另外，在以下描述中，为了提供对本发明的透彻理解，阐述了大量特定细节。然而，对于本领域普通技术人员显而易见的是：不必采用这些特定细节来实行本发明。在其他实例中，为了避免混淆本发明，未具体描述公知的电路、材料或方法。
说明书和权利要求书中表示方位的用语，例如“左““右”“里”“外”“前”“后”“上”“下”“顶部”“底部”“正上方”“正下方”等，只用于描述，并不意味着这些相对位置是永久不变的。应当理解的是，以上术语在适当的情况下是可以互换的，从而使得相应的实施例可以在其它方向上正常工作。
图2示出了现有的制造LDMOS器件的工艺流程概要图。该现有工艺可能包括以下步骤：前端工序、薄栅氧层形成、多晶硅层淀积、栅极区掩膜工序、多晶硅层刻蚀、掩膜层移除、多晶硅栅氧化、体区掩膜工序、体区注入、掩膜层移除、N+区掩膜工序、源极/漏极区注入、掩膜层移除、P+区掩膜工序、体接触区注入、掩膜层移除和后端工序。前端工序可包括：准备初始衬底、形成N型埋层、生长外延层和定义有源区。在一些应用中，前端工序还包括形成厚栅氧层。后端工序可包括：形成源极区电极、形成漏极区电极、形成体接触区电极、形成栅极电极和分布金属层。本领域普通技术人员应当知道，掩膜工序(例如“栅极区掩膜工序”)，意味着形成具有若干窗口的掩膜层，这些窗口对应于半导体衬底上表面的特定区域。例如，体区掩膜工序包括以下步骤：在半导体衬底的上表面形成掩膜层；对掩膜层进行显影，暴露出通向体区的窗口。掩膜可包括光刻胶。
由图2可知，体区、体接触区和源极/漏极区通过传统的光掩模和离子注入工艺形成。因此，源极/体区的窗口大小，即图1中所示出的N+/P+/N+区显然会受到光掩膜设备性能的限制。
图3a-3i示出了根据本发明一实施例的制造具有小源极区的LDMOS器件的制程。
图3a示出了半导体衬底301。所述半导体衬底301包括初始衬底318、N型埋层(NBL)319、外延层320和阱区321，其中阱区321也被称作漏极漂移区。初始衬底318可以为N型、P型或本征半导体材料；N型埋层319可以用其他结构替代；外延层320可以为N型、P型或本征半导体材料。阱区321可以是轻掺杂的高压阱区。所述LDMOS器件形成于阱区321之内。半导体衬底301还可能集成其他电路、器件或系统。例如，在BCD(Bipolar-CMOS-DMOS)工艺中，双极型晶体管(BJT，Bipolar Junction Transistor)、互补型金属氧化物半导体器件(CMOS，Complementary Metal Oxide Semiconductor)等其他多种器件会与LDMOS器件一起集成于同一衬底内。在一些实施例中，半导体衬底301可能具有其他构造，或不具有上述的部分区域。
图3a中，薄栅氧层302形成于半导体衬底301的上表面。随后，多晶硅层303通过淀积形成于薄栅氧层302之上。在后续工序中，该多晶硅层303将被刻蚀成LDMOS器件的多晶硅栅。接下来，在多晶硅层303的上表面进行氧化工序或氧化物淀积工序，形成栅极密封层304的一部分。随后，氮化硅层305通过淀积形成于栅极密封层304之上。接下来，第一掩膜层306通过掩膜工序形成于氮化硅层305之上。第一掩膜层306包括至少一个通向氮化硅层305的窗口OP1，该窗口可通过对第一掩膜层306进行曝光后溶解第一掩膜层306上特定的区域而形成。窗口OP1也被称作源极/体区窗口或者体区窗口。在一个实施例中，窗口OP1的宽度d1为0.3微米到0.5微米。在一些实施例中，第一掩膜层306可用光刻胶之外的其他材料替代。
薄栅氧层302被用作介电层，而多晶硅层303被用作LDMOS器件的栅极的导电层。本领域普通技术人员应当知道，薄栅氧层302和多晶硅层303可用其他合适的材料替代。
在图3b至图3i中，为清晰起见，初始衬底318、N型埋层319和外延层320未被示出。
图3b中，窗口OP1下的氮化硅层305、栅极密封层304和多晶硅层303被刻蚀，从而暴露出由薄栅氧层302所覆盖着的阱区321中对应源极/体区的区域表面。接下来，P型杂质通过窗口OP1注入至阱区321，形成体区307。第一掩膜层306在形成体区307和源极层331后被移除。
在一个实施例中，第一掩膜层306是在形成体区307后被移除。这种情况下，在N型杂质注入至体区307以形成源极层331的过程中，多晶硅层303、栅极密封层304和氮化硅层305被用作掩膜层。
在一个实施例中，退火工序可能会在形成体区307后被实施。在其他实施例中，退火工序可能会在形成体区307和源极层331后被实施。
图3c中，氧化工序被实施以形成栅极密封侧壁303S，来包裹窗口OP1内侧裸露的多晶硅层303的侧壁。栅极密封侧壁303S构成了栅极密封层304的一部分。
图3d中，形成氮化硅间隔308，以包裹栅极密封侧壁303S。氮化硅间隔308定义了源极区在体区307内的位置，即氮化硅间隔308正下方的区域。另外，间隔308还形成了窗口OP2，用于在体区307内定义体接触区332，该窗口OP2也称作体接触区窗口。
在一个实施例中，如图3d所示出的每个间隔308的厚度d2的范围为0.1微米到0.15微米。
图3e中，源极层331位于窗口OP2正下方的部分被刻蚀至穿通，从而形成源极区311。该源极区311为源极层331的一部分，在源极层331被刻蚀的过程中受到间隔308的保护。由于每个间隔308的厚度d2的范围为0.1微米到0.15微米，故每个源极区的宽度d3的范围也为0.1微米到0.15微米。在实际的器件中，栅极密封侧壁303S非常薄，其厚度可以被忽略。刻蚀源极层331的工序应当保证源极层331被穿通，但是在实际应用中，很难控制刻蚀工序以使得源极层331刚好被穿通且不破坏体区307中位于源极层331的被刻蚀区域的正下方的区域。因此，优选地，体区307应具有足够的结深，保证足以在源极层331的被刻蚀区域的正下方形成体接触区332。
图3f中，P型杂质通过窗口OP2注入至体区307，形成体接触区332。在此过程中，氮化硅305和间隔308的作用类似掩膜层。体接触区332具有比体区307更高的掺杂浓度。
图3g中，间隔308和氮化硅层305被刻蚀移除。
图3h中，第二掩膜层312通过掩膜工序形成于栅极密封层304之上。该第二掩膜层312包含位置确定的窗口，用于定义栅极。第二掩膜层312的窗口下的多晶硅层被刻蚀后形成栅极322。随后，第二掩膜层312被移除。之后，额外的氧化工序可能被实施以形成完整的栅极密封层304。
图3i中，第三掩膜层313通过光刻工序形成于栅极322和薄栅氧层302之上，该第三掩膜层313包含位置确定的窗口OP3，以定义漏极区314。第三掩膜层313也可同时被用于制作NMOS的N+源极区和漏极区，以及其他N+层，例如NPN双极晶体管的射极区和集极区。N型杂质通过窗口OP3注入至阱区321，形成漏极接触区314。随后，第三掩膜层313被移除。
图4示出了根据本发明一实施例的用于制造图3a-3i所示出的LDMOS器件的工艺流程概要图。相较于图2所示出的现有技术，本发明实施例在源极/体区窗口内侧的多晶硅层侧壁形成间隔，以定义源极区。在一些实施例中，该间隔厚度d2的范围为0.1微米到0.15微米。因此源极区宽度的范围可控制在0.1微米到0.15微米，远小于依现有工艺所制造的LDMOS器件源极区的宽度。本发明采用间隔和选择性刻蚀形成较窄的N+/P+/N+源极/体区，这是传统的光掩膜设备所无法实现的。
本领域普通技术人员应当知道，每个区域的掺杂类型可以替换，例如N型掺杂区可以用P型掺杂区替代，与此同时P型掺杂区用N型掺杂区替代。在如权利要求书所述的一个实施例中，第一掺杂类型为N型而第二掺杂类型为P型。在另一个实施例中，第一掺杂类型为P型而第二掺杂类型为N型。
N型杂质可在以下物质中择一：氮、磷、砷、锑、铋以及它们的组合。同时，P型杂质可在以下物质中择一：硼、铝、镓、铟、铊以及它们的组合。
根据以上教导，本发明的许多更改和变型方式显然也是可行的。因此，应当理解的是，在权利要求所限定的范围内，本发明可以不用按照上述特定的描述来实施。同样应当理解的是，上述公开只涉及到本发明一些优选实施例，在不脱离本发明权利要求所限定的精神和范围的前提下，可以对本发明作出更改。当只有一个优选实施例被公开，本领域普通技术人员不难想到改型并将其付诸于实施，而不脱离于本发明权利要求所限定的精神与范围。

Claims (10)

1.一种制造LDMOS器件的工艺流程，其中该LDMOS器件位于半导体衬底中的具有第一掺杂类型的阱区，包括：
在阱区上形成薄栅氧层；
在薄栅氧层上形成多晶硅层；
在多晶硅层上形成阻隔层，该阻隔层的刻蚀速度比薄栅氧层的刻蚀速度快；
通过在阻隔层之上的第一掩膜层的窗口，对阻隔层和多晶硅层进行刻蚀；
通过第一掩膜层的窗口，向阱区注入具有第二掺杂类型的杂质，形成体区；
通过第一掩膜层的窗口，向体区注入具有第一掺杂类型的杂质，形成源极层；
形成间隔，该间隔包裹刻蚀后所形成的多晶硅层窗口内侧的侧壁；
通过间隔所形成的窗口，对源极层进行刻蚀至源极层被穿通，形成源极区；
通过间隔所形成的窗口，向体区注入具有第二掺杂类型的杂质，形成体接触区；
通过刻蚀移除间隔和阻隔层；
通过第二掩膜层的窗口，对多晶硅层进行刻蚀，形成栅极；以及
通过第三掩膜层的窗口，向阱区注入具有第一掺杂类型的杂质，形成漏极接触区。
2.如权利要求1所述的制造LDMOS器件的工艺流程，其中间隔的材料和阻隔层的材料具有相同的刻蚀速度。
3.如权利要求1所述的制造LDMOS器件的工艺流程，其中间隔和阻隔层的材料为氮化硅。
4.如权利要求1所述的制造LDMOS器件的工艺流程，还包括在形成间隔之前，对多晶硅层窗口内侧的侧壁进行氧化。
5.如权利要求1所述的制造LDMOS器件的工艺流程，其中每个间隔的厚度范围为0.1微米到0.15微米。
6.如权利要求1所述的制造LDMOS器件的工艺流程，其中第一掩膜层的窗口宽度为0.3微米到0.5微米。
7.一种制造LDMOS器件的方法，包括：
通过阱区之上的多晶硅层窗口，在阱区内形成体区和源极层，其中体区具有比源极层更深的结深；
在多晶硅层窗口内侧的侧壁处形成间隔；以及
通过间隔所形成的窗口，对源极层进行刻蚀至源极层被穿通，其中源极层中位于间隔正下方的区域在源极层被刻蚀的过程中受到保护，并被定义成LDMOS器件的源极区。
8.如权利要求7所述的方法，还包括：
在源极层被刻蚀之后，向源极层被刻蚀的区域的正下方注入杂质，形成体接触区；以及
移除间隔。
9.如权利要求7所述的方法，其中间隔材料为氮化硅。
10.一种制造LDMOS器件的工艺流程，包括：
在半导体衬底内形成阱区；
在阱区上形成薄栅氧层；
在薄栅氧层上形成多晶硅层；
在多晶硅层上按顺序依次形成栅极密封层、氮化硅层和第一掩膜层，其中第一掩膜层包括至少一个通向氮化硅层表面的窗口；
通过第一掩膜层的窗口，对氮化硅层、栅极密封层和多晶硅层进行刻蚀，暴露出阱区中对应于体区的窗口；
通过体区窗口，向阱区注入P型杂质，在阱区内形成体区；
通过体区窗口，向体区注入N型杂质，在体区内形成源极层，随后移除第一掩膜层；
对多晶硅层窗口内侧的侧壁进行氧化；
在多晶硅层窗口内侧被氧化的侧壁处形成间隔；
通过间隔所形成的窗口，对源极层进行刻蚀至源极层被穿通，形成位于间隔正下方的源极区；
向体区中位于源极区之间的被刻蚀的区域注入P型杂质，形成体接触区；
通过刻蚀移除氮化硅层和间隔；
在栅极密封层上形成第二掩膜层，其中第二掩膜层具有位置预定的窗口；
通过第二掩膜层的窗口，对栅极密封层和多晶硅层进行刻蚀，形成栅极，随后移除第二掩膜层；
在栅极和薄栅氧层上形成第三掩膜层，该第三掩膜层包含至少一个对应于漏极接触区的窗口；以及
通过第三掩膜层的窗口，向阱区注入N型杂质，形成漏极接触区，随后移除第三掩膜层。
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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107742645A (zh) * 2016-09-28 2018-02-27 成都芯源系统有限公司 具有自对准体区的ldmos器件的制造方法
CN111370314A (zh) * 2020-04-30 2020-07-03 上海华虹宏力半导体制造有限公司 Bcd工艺制造nldmos器件的方法及其形成的器件
CN114985948A (zh) * 2021-06-16 2022-09-02 成都芯源系统有限公司 半导体晶圆的激光刻蚀方法

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11069777B1 (en) 2020-06-09 2021-07-20 Monolithic Power Systems, Inc. Manufacturing method of self-aligned DMOS body pickup
CN113707545A (zh) * 2021-08-18 2021-11-26 深圳市美浦森半导体有限公司 一种改善mosfet雪崩特性的方法及其器件
CN114188404A (zh) * 2021-11-30 2022-03-15 上海华虹宏力半导体制造有限公司 Ldmos器件的源端工艺方法
CN117476447A (zh) * 2023-12-28 2024-01-30 深圳腾睿微电子科技有限公司 碳化硅mos器件及其终端缓变结的制造方法

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20020100951A1 (en) * 2000-12-14 2002-08-01 Norio Yasuhara Offset-gate-type semiconductor device
US20060113627A1 (en) * 2004-11-29 2006-06-01 Chung-I Chen High-voltage transistor device having an interlayer dielectric etch stop layer for preventing leakage and improving breakdown voltage
CN102738215A (zh) * 2011-08-18 2012-10-17 成都芯源系统有限公司 横向双扩散金属氧化物半导体场效应晶体管及其制造方法

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6252278B1 (en) 1998-05-18 2001-06-26 Monolithic Power Systems, Inc. Self-aligned lateral DMOS with spacer drift region
US9159795B2 (en) 2013-06-28 2015-10-13 Monolithic Power Systems, Inc. High side DMOS and the method for forming thereof
US9502251B1 (en) 2015-09-29 2016-11-22 Monolithic Power Systems, Inc. Method for fabricating low-cost isolated resurf LDMOS and associated BCD manufacturing process

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20020100951A1 (en) * 2000-12-14 2002-08-01 Norio Yasuhara Offset-gate-type semiconductor device
US20060113627A1 (en) * 2004-11-29 2006-06-01 Chung-I Chen High-voltage transistor device having an interlayer dielectric etch stop layer for preventing leakage and improving breakdown voltage
CN102738215A (zh) * 2011-08-18 2012-10-17 成都芯源系统有限公司 横向双扩散金属氧化物半导体场效应晶体管及其制造方法

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107742645A (zh) * 2016-09-28 2018-02-27 成都芯源系统有限公司 具有自对准体区的ldmos器件的制造方法
CN111370314A (zh) * 2020-04-30 2020-07-03 上海华虹宏力半导体制造有限公司 Bcd工艺制造nldmos器件的方法及其形成的器件
CN114985948A (zh) * 2021-06-16 2022-09-02 成都芯源系统有限公司 半导体晶圆的激光刻蚀方法

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