CN112838118B - 超低导通电阻ldmos的制作方法 - Google Patents
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Abstract
本发明公开了一种超低导通电阻LDMOS的制作方法，该制作方法包括：在高压N型阱中形成N型漂移区和P阱；在高压N型阱上形成SiO2层；在SiO2层上积淀多晶硅层；在多晶硅层上涂光刻胶，对光刻胶进行曝光，显影后将掩膜图案转移到多晶硅层表面；对未被光刻胶覆盖的闸极多晶硅区域进行高阻注入；对未被光刻胶覆盖的闸极多晶硅区域进行高能注入；对P阱靠近闸极一侧区域和N型漂移区靠近STI区域进行N型注入；对P阱中STI区域之间进行P型注入；在闸极靠近N型漂移区一侧以及N型漂移区的上方形成合金阻挡层。本发明通过将高阻注入引入LDMOS制式提高LDMOS的表现，降低了制造超低导通电阻的成本，同时维持了关态击穿电压。
Description
技术领域
本发明设计半导体芯片技术领域，具体涉及一种在半导体制造工艺中制作超低导通电阻LDMOS(Laterally Diffused Metal Oxide Semiconductor，横向扩散金属氧化物半导体)的制作方法。
背景技术
LDMOS和高阻电阻广泛应用于模拟和功率电路中。其中LDMOS器件在如增益，线性度，开关性能，散热性能和减少级数等方面优势明显。
而高阻电阻如阱电阻通常通过离子注入来调节其阻值。在目前半导体BCD(Bipolar CMOS DMOS，双极型互补型双扩散型)工艺中这两种器件制作工艺兼容。
LDMOS器件的竞争力来自于关态击穿电压与导通电阻的妥协，通常当Rdson(导通电阻)较低时，BVoff(关态击穿电压)也较低，而当Rdson较高时，BVoff也较高。因此，在半导体BCD工艺中如何在不增加任何成本的情况下使得LDMOS器件具有较低的导通电阻而关态击穿电压相对不变，即如何实现导通电阻与关态击穿电压的折衷是制造LDMOS器件时需要解决的问题。
发明内容
本发明要解决的技术问题是为了克服现有技术中在半导体制造过程中LDMOS器件关态击穿电压BVoff与导通电阻Rdson之间的矛盾，提供一种超低导通电阻LDMOS的制作方法。
本发明是通过下述技术方案来解决上述技术问题：
本发明提供一种超低导通电阻LDMOS器件的制作方法，包括以下步骤：
在P型衬底上形成STI(Shallow Trench Isolation，浅沟槽隔离区)区域；
在所述STI区域下形成高压N型阱；
在所述高压N型阱中形成N型漂移区和P阱；
在所述高压N型阱上形成SiO2层；
在所述SiO2层上积淀多晶硅层；
在所述多晶硅层上涂光刻胶，对所述光刻胶进行曝光，显影后将掩膜图案转移到所述多晶硅层表面；
对未被所述光刻胶覆盖的闸极多晶硅区域进行高阻注入；
对未被所述光刻胶覆盖的闸极多晶硅区域进行高能注入；
去除所述光刻胶后再次涂所述光刻胶，再次对所述光刻胶曝光，显影后将闸极掩膜图案转移到所述多晶硅层表面；
对未被所述光刻胶覆盖的非闸极多晶硅区域进行刻蚀，并形成所述闸极的边墙；
对所述P阱靠近闸极一侧区域和所述N型漂移区靠近所述STI区域进行N型注入；
对所述P阱中所述STI区域之间进行P型注入；
在所述闸极靠近所述N型漂移区一侧以及N型漂移区的上方形成合金阻挡层。
较佳地，所述的超低导通电阻LDMOS的工作电压为10V-12V。
较佳地，所述高阻注入为半导体制作工艺中的阱电阻离子注入。
较佳地，所述高阻注入为硼离子注入，所述硼离子注入的浓度为1.05e15cm-3，所述硼离子注入的能量为2.5KeV。
较佳地，所述阱电阻离子注入的阱电阻阻值为每方块电阻1000Ω-2000Ω。
较佳地，所述高能注入为磷离子注入。
较佳地，所述磷离子注入的浓度为1.0e12cm-3-2.0e12cm-3，所述磷离子注入的能量为300KeV-450KeV。
较佳地，进行所述离子注入后均不需要热扩散工艺。
较佳地，对所述非闸极多晶硅区域进行刻蚀，所述刻蚀为干法刻蚀，刻蚀气体为CF4与O2。
本发明的积极进步效果在于：本发明通过将高阻注入引入LDMOS的制式提高LDMOS的表现，克服现有技术中在半导体制造过程中LDMOS器件关态击穿电压BVoff与导通电阻之间的矛盾，本发明通过将高阻注入引入LDMOS制式提高LDMOS的表现，降低了制造超低导通电阻的成本，同时维持了关态击穿电压。
附图说明
图1为本发明实施例1的一种超低导通电阻LDMOS的制作方法的流程图。
图2为本发明实施例1的一种超低导通电阻LDMOS的制作方法的流程中制作N型漂移调节区的步骤的示意图。
图3为本发明实施例1的一种超低导通电阻LDMOS的制作方法的流程中进行高阻和高能注入的步骤的示意图。
图4为本发明实施例1的一种超低导通电阻LDMOS的制作方法的流程中制作标准高阻电阻的步骤的示意图。
具体实施方式
下面通过实施例的方式进一步说明本发明，但并不因此将本发明限制在所述的实施例范围之中。
实施例1
本实施例提供一种超低导通电阻LDMOS的制作方法，参照图1，该制作方法包括如下步骤：
步骤S1：在P型衬底上形成STI区域。
步骤S2：在STI区域下形成高压N型阱。
本实施例中，P型衬底为P型硅衬底，在P型衬底上制作STI(Shallow TrenchIsolation，浅沟槽隔离区)区域5时，用掩膜版在高压N阱1中预设型样刻蚀沟槽，接下来，向沟槽内填充干氧生成的SiO2(二氧化硅)，然后利用器械对填充的SiO2的沟槽进行研磨，以形成STI区域5，STI区域5为浅沟槽隔离区。
步骤S3：在高压N型阱中形成N型漂移区和P阱。
具体的，参照图2，为超低导通电阻LDMOS的制作方法的流程中制作N型漂移调节区的步骤的示意图，从该图中可见，在高压N型阱1中形成N型漂移区2和P阱3。在制作低压P阱需要阱光罩，需要根据阱光罩的图形设置光胶6。
优选地，制作中该超低导通电阻LDMOS的工作电压为10V-12V。
步骤S4：在高压N型阱上形成SiO2层。
具体地，可以利用化学气相沉积形成SiO2钝化层。化学气相沉淀是一种化工技术，该技术主要是利用含有薄膜元素的一种或几种气相化合物或单质、在衬底表面上进行化学反应生成薄膜的方法。
步骤S5：在SiO2层上积淀多晶硅层。
具体的，参照图2，在高压N型阱1上形成的SiO2层，在SiO2层上沉淀多晶硅层7。
步骤S6：在多晶硅层上涂光刻胶，对光刻胶进行曝光，显影后将掩膜图案转移到多晶硅层表面。
在多晶硅层上涂抹光刻胶，用于进行后续高阻注入和高能注入时候的时候阻挡硼离子注入或者其他离子的注入。
优选地，对非闸极多晶硅区域进行刻蚀至硅表面，该刻蚀为干法刻蚀，刻蚀气体为CF4与O2。
步骤S7：对未被光刻胶覆盖的闸极多晶硅区域进行高阻注入。
进行离子注入后，现有技术需要进行扩散，通常温度为1100℃，在N2环境下进行30min(分钟)。参照图3，超低导通电阻LDMOS的制作方法的流程中进行高阻和高能注入的步骤的示意图。沿箭头所示方向向高阻多晶硅8中注入硼离子，并且为重掺杂硼离子，使硼离子停留在高阻多晶硅8中。高阻注入是本领域技术术语，本领域技术人员清楚高阻注入所采用的能量范围。本实施例中，主要应用于10～12V器件，不需要进行扩散，高阻注入为硼离子注入，硼离子注入的浓度为1.05e15cm-3，该硼离子注入的能量为2.5KeV。
优选地，高阻注入为半导体制作工艺中的阱电阻离子注入。
在一种可能实现的方式中，采用硼离子注入的深度可以为1微米，注入角度可以为3-6度或者注入深度、注入角度可以根据具体工艺而定。
步骤S8：对未被光刻胶覆盖的闸极多晶硅区域进行高能注入。
本实施例中，参照图3，对未被光刻胶覆盖的闸极多晶硅区域进行高能注入时，沿箭头所示方向进行注入。从高阻多晶硅8中注入磷离子，使磷离子穿透高阻多晶硅8形成N型漂移调节区4。高能注入磷离子是为了调节漂移区的浓度，磷离子注入的浓度为1.0e12cm-3-2.0e12cm-3，该磷离子注入的能量为300KeV-450KeV。高能量注入是本领域技术术语，本领域技术人员清楚高能量注入所采用的能量范围，通常注入能量超过300KeV时满足高能量注入，并且注入离子浓度越高，导通电阻越低，同时需要考虑击穿电压降低的因素。在本实施例中，高能量注入磷离子时，注入深度、注入角度可以根据具体工艺而定。
优选地，该进行磷离子注入后不需要实施热扩散工艺。
步骤S9：去除光刻胶后再次涂光刻胶，再次对光刻胶曝光，显影后将闸极掩膜图案转移到多晶硅层表面。
在半导体基片的上表面设置光胶，以形成透射区和阻挡取，透射区与低压阱的位置相对对应，再次涂光刻胶，对光刻胶进行曝光，显影后将闸极上铺设图形转移至多晶硅层表面上。
步骤S10：对未被光刻胶覆盖的非闸极多晶硅区域进行刻蚀，并形成闸极的边墙。
对经过显影后图形铺设的多晶硅层表面进行刻蚀后形成闸极的边墙。
步骤S11：对P阱靠近闸极一侧区域和N型漂移区靠近STI区域进行N型注入。
具体地，参照图3，P阱靠近闸极一侧区域和N型漂移区2靠近STI区域5进行N型注入，形成两个相互独立的N+型区域9。
步骤S12：对P阱中STI区域之间进行P型注入。
参照图3，P阱3中STI区域5之间的区域进行P型注入，形成了P+型区域10。
步骤S13：在闸极靠近N型漂移区一侧以及N型漂移区的上方形成合金阻挡层。
合金层可以为氮化钛合金层，在改未被合金阻挡层覆盖的区域也可以形成金属层，金属层可以为钛金属层。之后，本实施例在未被合金阻挡层覆盖的区域形成合金层，从该合金层引出电极。
优选地，参照图4，为超低导通电阻LDMOS的制作方法的流程中制作标准高阻电阻的步骤，包括高阻多晶硅8、STI区域5、P型阱2、高压N型阱1以及两个独立的P+型区域10，其与上述制作N型漂移调节区和进行高阻和高能注入的步骤类似，此处就不再赘述。
本发明通过将高阻注入引入LDMOS的制式提高LDMOS的表现，克服现有技术中在半导体制造过程中LDMOS器件关态击穿电压BVoff与导通电阻之间的矛盾，本发明通过将高阻注入引入LDMOS制式提高LDMOS的表现，降低了制造超低导通电阻的成本，同时维持了关态击穿电压。
虽然以上描述了本发明的具体实施方式，但是本领域的技术人员应当理解，这仅是举例说明，本发明的保护范围是由所附权利要求书限定的。本领域的技术人员在不背离本发明的原理和实质的前提下，可以对这些实施方式做出多种变更或修改，但这些变更和修改均落入本发明的保护范围。
Claims (9)
1.一种超低导通电阻LDMOS的制作方法，其特征在于，所述制作方法包括：
在P型衬底上形成STI区域；
在所述STI区域下形成高压N型阱；
在所述高压N型阱中形成N型漂移区和P阱；
在所述高压N型阱上形成SiO2层；
在所述SiO2层上积淀多晶硅层；
在所述多晶硅层上涂光刻胶，对所述光刻胶进行曝光，显影后将掩膜图案转移到所述多晶硅层表面；
对未被所述光刻胶覆盖的闸极多晶硅区域进行高阻注入；
对未被所述光刻胶覆盖的闸极多晶硅区域进行高能注入；
去除所述光刻胶后再次涂所述光刻胶，再次对所述光刻胶曝光，显影后将闸极掩膜图案转移到所述多晶硅层表面；
对未被所述光刻胶覆盖的非闸极多晶硅区域进行刻蚀，并形成所述闸极的边墙；
对所述P阱靠近闸极一侧区域和所述N型漂移区靠近所述STI区域进行N型注入；
对所述P阱中所述STI区域之间进行P型注入；
在所述闸极靠近所述N型漂移区一侧以及N型漂移区的上方形成合金阻挡层。
2.如权利要求1所述的超低导通电阻LDMOS的制作方法，其特征在于，所述的超低导通电阻LDMOS的工作电压为10V-12V。
3.如权利要求1所述的超低导通电阻LDMOS的制作方法，其特征在于，所述高阻注入为半导体制作工艺中的阱电阻离子注入。
4.如权利要求3所述的超低导通电阻LDMOS的制作方法，其特征在于，所述高阻注入为硼离子注入，所述硼离子注入的浓度为1.05e15cm-3，所述硼离子注入的能量为2.5KeV。
5.如权利要求3所述的超低导通电阻LDMOS的制作方法，其特征在于，所述阱电阻离子注入的阱电阻阻值为每方块电阻1000Ω-2000Ω。
6.如权利要求1所述的超低导通电阻LDMOS的制作方法，其特征在于，所述高能注入为磷离子注入。
7.如权利要求6所述的超低导通电阻LDMOS的制作方法，其特征在于，所述磷离子注入的浓度为1.0e12cm-3-2.0e12cm-3，所述磷离子注入的能量为300KeV-450KeV。
8.如权利要求3-7任一项所述的超低导通电阻LDMOS的制作方法，其特征在于，进行所述离子注入后均不需要热扩散工艺。
9.如权利要求1所述的超低导通电阻LDMOS的制作方法，其特征在于，对所述非闸极多晶硅区域进行刻蚀，所述刻蚀为干法刻蚀，刻蚀气体为CF4与O2。
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| CN102306661A (zh) * | 2011-09-20 | 2012-01-04 | 上海先进半导体制造股份有限公司 | Ldmos晶体管结构及其形成方法 |
| WO2017092408A1 (zh) * | 2015-12-01 | 2017-06-08 | 无锡华润上华半导体有限公司 | 一种多晶硅高阻的制造方法 |
| CN107887437A (zh) * | 2016-09-30 | 2018-04-06 | 中芯国际集成电路制造(上海)有限公司 | Ldmos晶体管及其形成方法、半导体器件及其形成方法 |
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| CN102306661A (zh) * | 2011-09-20 | 2012-01-04 | 上海先进半导体制造股份有限公司 | Ldmos晶体管结构及其形成方法 |
| WO2017092408A1 (zh) * | 2015-12-01 | 2017-06-08 | 无锡华润上华半导体有限公司 | 一种多晶硅高阻的制造方法 |
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