JP4741187B2 - ドープカラムを含む高電圧電力mosfet - Google Patents
ドープカラムを含む高電圧電力mosfet Download PDFInfo
- Publication number
- JP4741187B2 JP4741187B2 JP2003558933A JP2003558933A JP4741187B2 JP 4741187 B2 JP4741187 B2 JP 4741187B2 JP 2003558933 A JP2003558933 A JP 2003558933A JP 2003558933 A JP2003558933 A JP 2003558933A JP 4741187 B2 JP4741187 B2 JP 4741187B2
- Authority
- JP
- Japan
- Prior art keywords
- trench
- region
- doped
- layer
- dopant
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 238000000034 method Methods 0.000 claims description 37
- 239000000463 material Substances 0.000 claims description 27
- 210000000746 body region Anatomy 0.000 claims description 24
- 239000002019 doping agent Substances 0.000 claims description 22
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 18
- 239000004065 semiconductor Substances 0.000 claims description 16
- 239000000758 substrate Substances 0.000 claims description 15
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 9
- 235000012239 silicon dioxide Nutrition 0.000 claims description 9
- 239000000377 silicon dioxide Substances 0.000 claims description 9
- 238000005530 etching Methods 0.000 claims description 8
- 229920005591 polysilicon Polymers 0.000 claims description 8
- 230000004888 barrier function Effects 0.000 claims description 7
- 238000000151 deposition Methods 0.000 claims description 6
- 239000003989 dielectric material Substances 0.000 claims description 6
- 230000000873 masking effect Effects 0.000 claims description 6
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical group [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 claims description 3
- 229910052796 boron Inorganic materials 0.000 claims description 3
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 2
- 238000009792 diffusion process Methods 0.000 description 12
- 230000015556 catabolic process Effects 0.000 description 8
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 4
- 238000002513 implantation Methods 0.000 description 4
- 229910052710 silicon Inorganic materials 0.000 description 4
- 239000010703 silicon Substances 0.000 description 4
- 230000002411 adverse Effects 0.000 description 2
- 229910052785 arsenic Inorganic materials 0.000 description 2
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 2
- 238000001020 plasma etching Methods 0.000 description 2
- 230000002441 reversible effect Effects 0.000 description 2
- 238000000137 annealing Methods 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000000903 blocking effect Effects 0.000 description 1
- 238000003486 chemical etching Methods 0.000 description 1
- 230000001419 dependent effect Effects 0.000 description 1
- 238000005137 deposition process Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 239000007943 implant Substances 0.000 description 1
- 238000001465 metallisation Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 230000000149 penetrating effect Effects 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 238000001953 recrystallisation Methods 0.000 description 1
- 230000002459 sustained effect Effects 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/74—Thyristor-type devices, e.g. having four-zone regenerative action
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
- H01L29/063—Reduced surface field [RESURF] pn-junction structures
- H01L29/0634—Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0642—Isolation within the component, i.e. internal isolation
- H01L29/0649—Dielectric regions, e.g. SiO2 regions, air gaps
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1095—Body region, i.e. base region, of DMOS transistors or IGBTs
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Description
本発明によると、電力半導体装置を形成する方法が提供される。同方法では、最初に第1の導電型の基板が設けられ、続いて、基板上に電圧維持領域が形成される。電圧維持領域は、基板上に第1の導電型のエピタキシャル層が堆積され、少なくとも1つのトレンチをエピタキシャル層に形成されることにより得られる。バリア材料がトレンチの壁に沿って堆積される。第2の導電型のドーパントがバリア材料を通ってトレンチの底部に隣接し、且つ、下にあるエピタキシャル層の部分中に注入される。ドーパントは、拡散され、エピタキシャル層に第1のドープ層が形成され、バリア材料が少なくともトレンチの底部から除去される。トレンチは第1のドープ層を通ってエッチングされる。第2のドープ層が第1のドープ層と同様に形成される。第2のドープ層は第1のドープ層の垂直方向に下の位置にある。充填材料はトレンチに堆積されトレンチが略充填される。第1および第2のドープ層中のドーパントは拡散され、第1および第2のドープ層が互いに対してオーバーラップされ、電圧維持領域が完成される。最後に、間に接合を定めるよう第2の導電型の少なくとも1つの領域が電圧維持領域上に形成される。
Claims (14)
- 電力半導体装置を形成する方法であって、
A.第1または第2の導電型の基板を用意する工程と;
B.
1.前記基板上に第1の導電型を有するエピタキシャル層を堆積し、
2.前記エピタキシャル層に少なくとも1つのトレンチを形成し、
3.前記トレンチの壁に沿ってバリア材料を堆積し、
4.前記バリア材料を通って前記トレンチの底部に隣接し、且つ、下にある前記エピタキシャル層の部分に第2の導電型のドーパントを注入し、
5.前記ドーパントを拡散して、前記エピタキシャル層に第1のドープ層を形成し、
6.少なくとも前記トレンチの前記底部から前記バリア材料を除去し、
7.前記第1のドープ層を通って前記トレンチをエッチングし、前記(B.3)から(B.6)を繰り返して前記第1のドープ層の垂直方向に下の位置に第2のドープ層を形成し、
8.前記トレンチに誘電体材料を堆積し前記トレンチを略充填し、
9.前記トレンチが略充填された後に、前記第1および前記第2のドープ層中の前記ドーパントを拡散して前記第1のおよび前記第2のドープ層を互いに対してオーバーラップさせる、
ことによって前記基板上に電圧維持領域を形成する工程と;および
C.前記電圧維持領域上に前記第2の導電型の少なくとも1つの領域を形成して接合を間に定め工程と、
を備える方法。 - 前記第2のドープ層を通って前記トレンチをエッチングする工程を更に備える、請求項1記載の方法。
- 前記電圧維持領域上の前記第2の導電型の前記少なくとも1つの領域は、間にドリフト領域を画定するための前記エピタキシャル層内の第1および第2のボディ領域を備え、
前記第1および第2のボディ領域の上方のゲート誘電体領域の上にゲート電極を形成する工程と、
前記第1および前記第2のボディ領域それぞれに前記第1の導電型の第1および第2のソース領域を形成する工程と、
を更に備える、請求項1記載の方法。 - 前記バリア材料は酸化物材料である、請求項1記載の方法。
- 前記酸化物材料は二酸化珪素である、請求項4記載の方法。
- 前記トレンチを充填する前記材料は高抵抗のポリシリコンである、請求項1記載の方法。
- 前記トレンチを充填する前記材料は誘電体材料である、請求項1記載の方法。
- 前記誘電体材料は二酸化珪素である、請求項7記載の方法。
- 前記誘電体材料は窒化珪素である、請求項7記載の方法。
- 前記ドーパントはボロンである、請求項1記載の方法。
- 前記ボディ領域は深いボディ領域を含む、請求項3記載の方法。
- 前記トレンチは、少なくとも1つのトレンチを画定するマスキング層を設け、前記マスキング層によって画定される前記トレンチをエッチングすることで形成される、請求項1記載の方法。
- 前記ボディ領域は前記基板にドーパントを注入し拡散することで形成される、請求項3記載の方法。
- 前記電力半導体装置は、縦型DMOS、V溝DMOSおよびトレンチDMOS MOSFET、IGBT、および、バイポーラトランジスタからなる群から選択される、請求項1記載の方法。
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US10/038,845 | 2001-12-31 | ||
US10/038,845 US6656797B2 (en) | 2001-12-31 | 2001-12-31 | High voltage power MOSFET having a voltage sustaining region that includes doped columns formed by trench etching and ion implantation |
PCT/US2002/041790 WO2003058722A1 (en) | 2001-12-31 | 2002-12-30 | High voltage power mosfet includes doped columns |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2005514794A JP2005514794A (ja) | 2005-05-19 |
JP4741187B2 true JP4741187B2 (ja) | 2011-08-03 |
Family
ID=21902232
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2003558933A Expired - Fee Related JP4741187B2 (ja) | 2001-12-31 | 2002-12-30 | ドープカラムを含む高電圧電力mosfet |
Country Status (8)
Country | Link |
---|---|
US (2) | US6656797B2 (ja) |
EP (1) | EP1468452B1 (ja) |
JP (1) | JP4741187B2 (ja) |
KR (1) | KR100990294B1 (ja) |
CN (1) | CN100342544C (ja) |
AU (1) | AU2002364365A1 (ja) |
TW (1) | TWI263282B (ja) |
WO (1) | WO2003058722A1 (ja) |
Families Citing this family (28)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
FR2803094B1 (fr) * | 1999-12-22 | 2003-07-25 | St Microelectronics Sa | Fabrication de composants unipolaires |
US6727528B1 (en) * | 2001-03-22 | 2004-04-27 | T-Ram, Inc. | Thyristor-based device including trench dielectric isolation for thyristor-body regions |
US7456439B1 (en) | 2001-03-22 | 2008-11-25 | T-Ram Semiconductor, Inc. | Vertical thyristor-based memory with trench isolation and its method of fabrication |
DE10131704A1 (de) * | 2001-06-29 | 2003-01-16 | Atmel Germany Gmbh | Verfahren zur Dotierung eines Halbleiterkörpers |
US6750104B2 (en) * | 2001-12-31 | 2004-06-15 | General Semiconductor, Inc. | High voltage power MOSFET having a voltage sustaining region that includes doped columns formed by trench etching using an etchant gas that is also a doping source |
US6576516B1 (en) * | 2001-12-31 | 2003-06-10 | General Semiconductor, Inc. | High voltage power MOSFET having a voltage sustaining region that includes doped columns formed by trench etching and diffusion from regions of oppositely doped polysilicon |
US6686244B2 (en) * | 2002-03-21 | 2004-02-03 | General Semiconductor, Inc. | Power semiconductor device having a voltage sustaining region that includes doped columns formed with a single ion implantation step |
DE10346838A1 (de) * | 2002-10-08 | 2004-05-13 | International Rectifier Corp., El Segundo | Superjunction-Bauteil |
US20040248403A1 (en) * | 2003-06-09 | 2004-12-09 | Dubin Valery M. | Method for forming electroless metal low resistivity interconnects |
DE10345347A1 (de) | 2003-09-19 | 2005-04-14 | Atmel Germany Gmbh | Verfahren zur Herstellung eines DMOS-Transistors mit lateralem Driftregionen-Dotierstoffprofil |
JP2005340626A (ja) * | 2004-05-28 | 2005-12-08 | Toshiba Corp | 半導体装置 |
CN100388445C (zh) * | 2004-12-08 | 2008-05-14 | 上海华虹Nec电子有限公司 | 小线宽沟槽型结构大功率mos管制造方法 |
JP4939760B2 (ja) * | 2005-03-01 | 2012-05-30 | 株式会社東芝 | 半導体装置 |
US20070012983A1 (en) * | 2005-07-15 | 2007-01-18 | Yang Robert K | Terminations for semiconductor devices with floating vertical series capacitive structures |
US7554137B2 (en) * | 2005-10-25 | 2009-06-30 | Infineon Technologies Austria Ag | Power semiconductor component with charge compensation structure and method for the fabrication thereof |
US7378717B2 (en) * | 2005-11-15 | 2008-05-27 | International Business Machines Corporation | Semiconductor optical sensors |
KR101279574B1 (ko) * | 2006-11-15 | 2013-06-27 | 페어차일드코리아반도체 주식회사 | 고전압 반도체 소자 및 그 제조 방법 |
US8133781B2 (en) * | 2010-02-15 | 2012-03-13 | International Business Machines Corporation | Method of forming a buried plate by ion implantation |
CN102339851B (zh) * | 2010-07-15 | 2014-04-23 | 科轩微电子股份有限公司 | 具有沟槽底部多晶硅结构的功率半导体及其制造方法 |
TWI405271B (zh) * | 2010-12-30 | 2013-08-11 | Anpec Electronics Corp | 製作具有超級介面之功率半導體元件之方法 |
US9245986B2 (en) * | 2012-11-29 | 2016-01-26 | Samsung Electro-Mechanics Co., Ltd. | Power semiconductor device and method of manufacturing the same |
TWI458097B (zh) * | 2012-12-12 | 2014-10-21 | Beyond Innovation Tech Co Ltd | 溝渠式閘極金氧半場效電晶體及其製造方法 |
US9741851B2 (en) * | 2013-05-13 | 2017-08-22 | Alpha And Omega Semiconductor Incorporated | Trench junction barrier controlled Schottky |
KR101514537B1 (ko) * | 2013-08-09 | 2015-04-22 | 삼성전기주식회사 | 전력 반도체 소자 및 그 제조 방법 |
DE102013217768A1 (de) * | 2013-09-05 | 2015-03-05 | Robert Bosch Gmbh | Verfahren zur Herstellung eines Substrats, Substrat, Metall-Oxid-Halbleiter-Feldeffekttransistor mit einem Substrat, mikroelektromechanisches System mit einem Substrat, und Kraftfahrzeug |
EP3510637A4 (en) * | 2016-09-09 | 2020-04-15 | United Silicon Carbide Inc. | VERTICAL TRENCH JFET WITH IMPROVED THRESHOLD VOLTAGE CONTROL |
CN111725318B (zh) * | 2020-06-18 | 2024-04-09 | 湖南国芯半导体科技有限公司 | 一种功率半导体器件的元胞结构及其制作方法 |
US11569345B2 (en) * | 2020-11-23 | 2023-01-31 | Alpha And Omega Semiconductor (Cayman) Ltd. | Gas dopant doped deep trench super junction high voltage MOSFET |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS63119546A (ja) * | 1986-11-07 | 1988-05-24 | Sony Corp | 半導体装置の製造方法 |
JP2001127289A (ja) * | 1999-10-28 | 2001-05-11 | Denso Corp | 半導体装置および半導体装置の製造方法 |
WO2001095398A1 (en) * | 2000-06-02 | 2001-12-13 | General Semiconductor, Inc. | Power mosfet and method of making the same |
JP2002525877A (ja) * | 1998-09-24 | 2002-08-13 | インフィネオン テクノロジース アクチエンゲゼルシャフト | 半導体構成素子の製造方法 |
Family Cites Families (27)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US117715A (en) * | 1871-08-01 | Improvement in fanning-mills | ||
US122189A (en) * | 1871-12-26 | Improvement in car-couplings | ||
US4140558A (en) | 1978-03-02 | 1979-02-20 | Bell Telephone Laboratories, Incorporated | Isolation of integrated circuits utilizing selective etching and diffusion |
US4419150A (en) | 1980-12-29 | 1983-12-06 | Rockwell International Corporation | Method of forming lateral bipolar transistors |
US4569701A (en) | 1984-04-05 | 1986-02-11 | At&T Bell Laboratories | Technique for doping from a polysilicon transfer layer |
JPS61133656A (ja) * | 1984-12-03 | 1986-06-20 | Hitachi Ltd | 半導体装置およびその製造方法 |
US4711017A (en) | 1986-03-03 | 1987-12-08 | Trw Inc. | Formation of buried diffusion devices |
US4893160A (en) | 1987-11-13 | 1990-01-09 | Siliconix Incorporated | Method for increasing the performance of trenched devices and the resulting structure |
US4980742A (en) * | 1988-05-31 | 1990-12-25 | Siemens Aktiengesellschaft | Turn-off thyristor |
JP2733271B2 (ja) | 1988-12-23 | 1998-03-30 | シャープ株式会社 | 半導体装置の製造方法 |
CN1019720B (zh) | 1991-03-19 | 1992-12-30 | 电子科技大学 | 半导体功率器件 |
KR0120572B1 (ko) * | 1994-05-04 | 1997-10-20 | 김주용 | 반도체 소자 및 그 제조방법 |
EP0922554B1 (en) * | 1997-12-08 | 2003-06-25 | Dow Deutschland Inc. | Multilayer foams, method of production and use |
US6303448B1 (en) * | 1998-11-05 | 2001-10-16 | Taiwan Semiconductor Manufacturing Company | Method for fabricating raised source/drain structures |
US6245639B1 (en) * | 1999-02-08 | 2001-06-12 | Taiwan Semiconductor Manufacturing Company | Method to reduce a reverse narrow channel effect for MOSFET devices |
US6316336B1 (en) * | 1999-03-01 | 2001-11-13 | Richard A. Blanchard | Method for forming buried layers with top-side contacts and the resulting structure |
DE19922187C2 (de) * | 1999-05-12 | 2001-04-26 | Siemens Ag | Niederohmiges VDMOS-Halbleiterbauelement und Verfahren zu dessen Herstellung |
DE19943143B4 (de) * | 1999-09-09 | 2008-04-24 | Infineon Technologies Ag | Halbleiterbauelement für hohe Sperrspannungen bei gleichzeitig niedrigem Einschaltwiderstand und Verfahren zu dessen Herstellung |
JP4371521B2 (ja) | 2000-03-06 | 2009-11-25 | 株式会社東芝 | 電力用半導体素子およびその製造方法 |
GB0010041D0 (en) | 2000-04-26 | 2000-06-14 | Koninkl Philips Electronics Nv | Trench semiconductor device manufacture |
US6465304B1 (en) | 2001-10-04 | 2002-10-15 | General Semiconductor, Inc. | Method for fabricating a power semiconductor device having a floating island voltage sustaining layer |
US6649477B2 (en) | 2001-10-04 | 2003-11-18 | General Semiconductor, Inc. | Method for fabricating a power semiconductor device having a voltage sustaining layer with a terraced trench facilitating formation of floating islands |
US6576516B1 (en) | 2001-12-31 | 2003-06-10 | General Semiconductor, Inc. | High voltage power MOSFET having a voltage sustaining region that includes doped columns formed by trench etching and diffusion from regions of oppositely doped polysilicon |
US6750104B2 (en) | 2001-12-31 | 2004-06-15 | General Semiconductor, Inc. | High voltage power MOSFET having a voltage sustaining region that includes doped columns formed by trench etching using an etchant gas that is also a doping source |
US6566201B1 (en) | 2001-12-31 | 2003-05-20 | General Semiconductor, Inc. | Method for fabricating a high voltage power MOSFET having a voltage sustaining region that includes doped columns formed by rapid diffusion |
JP3897298B2 (ja) * | 2002-11-27 | 2007-03-22 | 株式会社タチエス | リア・シート・アームレスト |
GB2401311A (en) * | 2003-05-08 | 2004-11-10 | Autoliv Dev | A child safety seat with a latch mechanism |
-
2001
- 2001-12-31 US US10/038,845 patent/US6656797B2/en not_active Expired - Lifetime
-
2002
- 2002-12-24 TW TW091137178A patent/TWI263282B/zh not_active IP Right Cessation
- 2002-12-30 EP EP02799348.4A patent/EP1468452B1/en not_active Expired - Fee Related
- 2002-12-30 WO PCT/US2002/041790 patent/WO2003058722A1/en active Application Filing
- 2002-12-30 AU AU2002364365A patent/AU2002364365A1/en not_active Abandoned
- 2002-12-30 JP JP2003558933A patent/JP4741187B2/ja not_active Expired - Fee Related
- 2002-12-30 CN CNB028265459A patent/CN100342544C/zh not_active Expired - Fee Related
- 2002-12-30 KR KR1020047010417A patent/KR100990294B1/ko not_active IP Right Cessation
-
2003
- 2003-12-01 US US10/724,849 patent/US7091552B2/en not_active Expired - Fee Related
Patent Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS63119546A (ja) * | 1986-11-07 | 1988-05-24 | Sony Corp | 半導体装置の製造方法 |
JP2002525877A (ja) * | 1998-09-24 | 2002-08-13 | インフィネオン テクノロジース アクチエンゲゼルシャフト | 半導体構成素子の製造方法 |
JP2001127289A (ja) * | 1999-10-28 | 2001-05-11 | Denso Corp | 半導体装置および半導体装置の製造方法 |
WO2001095398A1 (en) * | 2000-06-02 | 2001-12-13 | General Semiconductor, Inc. | Power mosfet and method of making the same |
JP2004509452A (ja) * | 2000-06-02 | 2004-03-25 | ゼネラル セミコンダクター,インク. | パワー金属酸化膜半導体電界効果トランジスタ及びその製造方法 |
Also Published As
Publication number | Publication date |
---|---|
WO2003058722A1 (en) | 2003-07-17 |
EP1468452B1 (en) | 2018-10-10 |
CN1610973A (zh) | 2005-04-27 |
EP1468452A4 (en) | 2009-01-07 |
AU2002364365A1 (en) | 2003-07-24 |
CN100342544C (zh) | 2007-10-10 |
US20040110333A1 (en) | 2004-06-10 |
JP2005514794A (ja) | 2005-05-19 |
KR100990294B1 (ko) | 2010-10-26 |
TWI263282B (en) | 2006-10-01 |
EP1468452A1 (en) | 2004-10-20 |
US20030122188A1 (en) | 2003-07-03 |
TW200301525A (en) | 2003-07-01 |
US6656797B2 (en) | 2003-12-02 |
US7091552B2 (en) | 2006-08-15 |
KR20040071773A (ko) | 2004-08-12 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JP4741187B2 (ja) | ドープカラムを含む高電圧電力mosfet | |
JP4833517B2 (ja) | 迅速な拡散によって形成されるドープカラムを含む電圧維持領域を有する高電圧電力mosfetを製造する方法 | |
JP4786872B2 (ja) | 単一のイオン注入工程によって形成されたドープされたコラムを含む電圧維持領域を有するパワー半導体デバイス及びそれらの製造方法 | |
JP4880199B2 (ja) | トレンチのエッチングおよび反対にドープされたポリシリコンの領域からの拡散によって形成されるドープカラムを含む電圧維持領域を有する高電圧電力mosfet | |
JP4743744B2 (ja) | フローティングアイランド電圧維持層を有する半導体パワーデバイス | |
US7736976B2 (en) | Method for fabricating a power semiconductor device having a voltage sustaining layer with a terraced trench facilitating formation of floating islands | |
US6750104B2 (en) | High voltage power MOSFET having a voltage sustaining region that includes doped columns formed by trench etching using an etchant gas that is also a doping source | |
JP4615217B2 (ja) | フローティングアイランドを形成するための雛壇状のトレンチを有する電圧維持層を備える半導体パワーデバイスの製造方法 | |
JP4511190B2 (ja) | 低オン抵抗を有する高電圧電力mosfet |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A621 | Written request for application examination |
Free format text: JAPANESE INTERMEDIATE CODE: A621 Effective date: 20051216 |
|
A977 | Report on retrieval |
Free format text: JAPANESE INTERMEDIATE CODE: A971007 Effective date: 20091214 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20100105 |
|
A601 | Written request for extension of time |
Free format text: JAPANESE INTERMEDIATE CODE: A601 Effective date: 20100405 |
|
A602 | Written permission of extension of time |
Free format text: JAPANESE INTERMEDIATE CODE: A602 Effective date: 20100412 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20100705 |
|
A02 | Decision of refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A02 Effective date: 20100921 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20110121 |
|
A911 | Transfer to examiner for re-examination before appeal (zenchi) |
Free format text: JAPANESE INTERMEDIATE CODE: A911 Effective date: 20110128 |
|
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20110405 |
|
A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20110506 |
|
R150 | Certificate of patent or registration of utility model |
Free format text: JAPANESE INTERMEDIATE CODE: R150 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20140513 Year of fee payment: 3 |
|
LAPS | Cancellation because of no payment of annual fees |